1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
18 ComplexPattern<iPTR, 3, "selectAddr16", [frameindex], [SDNPWantParent]>;
22 def mem16 : Operand<i32> {
23 let PrintMethod = "printMemOperand";
24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16RegsPlusSP);
25 let EncoderMethod = "getMemEncoding";
28 def mem16_ea : Operand<i32> {
29 let PrintMethod = "printMemOperandEA";
30 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
31 let EncoderMethod = "getMemEncoding";
35 // I-type instruction format
37 // this is only used by bimm. the actual assembly value is a 12 bit signed
40 class FI16_ins<bits<5> op, string asmstr, InstrItinClass itin>:
41 FI16<op, (outs), (ins brtarget:$imm16),
42 !strconcat(asmstr, "\t$imm16 # 16 bit inst"), [], itin>;
46 // I8 instruction format
49 class FI816_ins_base<bits<3> _func, string asmstr,
50 string asmstr2, InstrItinClass itin>:
51 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
54 class FI816_ins<bits<3> _func, string asmstr,
56 FI816_ins_base<_func, asmstr, "\t$imm # 16 bit inst", itin>;
58 class FI816_SP_ins<bits<3> _func, string asmstr,
60 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
63 // RI instruction format
67 class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
69 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
70 !strconcat(asmstr, asmstr2), [], itin>;
72 class FRI16_ins<bits<5> op, string asmstr,
74 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
76 class FRI16_TCP_ins<bits<5> _op, string asmstr,
78 FRI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size),
79 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin>;
81 class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2,
83 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
84 !strconcat(asmstr, asmstr2), [], itin>;
86 class FRI16R_ins<bits<5> op, string asmstr,
88 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
90 class F2RI16_ins<bits<5> _op, string asmstr,
92 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
93 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
94 let Constraints = "$rx_ = $rx";
97 class FRI16_B_ins<bits<5> _op, string asmstr,
99 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
100 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>;
102 // Compare a register and immediate and place result in CC
103 // Implicit use of T8
105 // EXT-CCRR Instruction format
107 class FEXT_CCRXI16_ins<string asmstr>:
108 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
109 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
111 let usesCustomInserter = 1;
114 // JAL and JALX instruction format
116 class FJAL16_ins<bits<1> _X, string asmstr,
117 InstrItinClass itin>:
118 FJAL16<_X, (outs), (ins simm20:$imm),
119 !strconcat(asmstr, "\t$imm\n\tnop"),[],
125 class FJALB16_ins<bits<1> _X, string asmstr,
126 InstrItinClass itin>:
127 FJAL16<_X, (outs), (ins simm20:$imm),
128 !strconcat(asmstr, "\t$imm\t# branch\n\tnop"),[],
135 // EXT-I instruction format
137 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
138 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
139 !strconcat(asmstr, "\t$imm16"),[], itin>;
142 // EXT-I8 instruction format
145 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
146 string asmstr2, InstrItinClass itin>:
147 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
150 class FEXT_I816_ins<bits<3> _func, string asmstr,
151 InstrItinClass itin>:
152 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
154 class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
155 InstrItinClass itin>:
156 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>;
159 // Assembler formats in alphabetical order.
160 // Natural and pseudos are mixed together.
162 // Compare two registers and place result in CC
163 // Implicit use of T8
165 // CC-RR Instruction format
167 class FCCRR16_ins<string asmstr> :
168 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
169 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
171 let usesCustomInserter = 1;
175 // EXT-RI instruction format
178 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
179 InstrItinClass itin>:
180 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
181 !strconcat(asmstr, asmstr2), [], itin>;
183 class FEXT_RI16_ins<bits<5> _op, string asmstr,
184 InstrItinClass itin>:
185 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
187 class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2,
188 InstrItinClass itin>:
189 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm),
190 !strconcat(asmstr, asmstr2), [], itin>;
192 class FEXT_RI16R_ins<bits<5> _op, string asmstr,
193 InstrItinClass itin>:
194 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
196 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
197 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
199 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
200 InstrItinClass itin>:
201 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
202 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
204 class FEXT_RI16_TCP_ins<bits<5> _op, string asmstr,
205 InstrItinClass itin>:
206 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size),
207 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
209 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
210 InstrItinClass itin>:
211 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
212 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
213 let Constraints = "$rx_ = $rx";
217 // this has an explicit sp argument that we ignore to work around a problem
219 class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
220 InstrItinClass itin>:
221 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
222 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
224 class FEXT_RI16_SP_Store_explicit_ins<bits<5> _op, string asmstr,
225 InstrItinClass itin>:
226 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm),
227 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
230 // EXT-RRI instruction format
233 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
234 InstrItinClass itin>:
235 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
236 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
238 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
239 InstrItinClass itin>:
240 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
241 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
245 // EXT-RRI-A instruction format
248 class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
249 InstrItinClass itin>:
250 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
251 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
254 // EXT-SHIFT instruction format
256 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
257 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa),
258 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
263 class FEXT_T8I816_ins<string asmstr, string asmstr2>:
265 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
266 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
267 !strconcat(asmstr, "\t$imm"))),[]> {
269 let usesCustomInserter = 1;
275 class FEXT_T8I8I16_ins<string asmstr, string asmstr2>:
277 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
278 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
279 !strconcat(asmstr, "\t$targ"))), []> {
281 let usesCustomInserter = 1;
287 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
289 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
290 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32),
291 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
294 // I8_MOV32R instruction format (used only by MOV32R instruction)
297 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
298 FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz),
299 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
302 // This are pseudo formats for multiply
303 // This first one can be changed to non-pseudo now.
307 class FMULT16_ins<string asmstr, InstrItinClass itin> :
308 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
309 !strconcat(asmstr, "\t$rx, $ry"), []>;
314 class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
315 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
316 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
321 // RR-type instruction format
324 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
325 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
326 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
329 class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> :
330 FRRBreak16<(outs), (ins), asmstr, [], itin> {
334 class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> :
335 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
336 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
339 class FRRTR16_ins<string asmstr> :
340 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
341 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
344 // maybe refactor but need a $zero as a dummy first parameter
346 class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
347 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
348 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
350 class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
351 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
352 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
355 class FRR16_M_ins<bits<5> f, string asmstr,
356 InstrItinClass itin> :
357 FRR16<f, (outs CPU16Regs:$rx), (ins),
358 !strconcat(asmstr, "\t$rx"), [], itin>;
360 class FRxRxRy16_ins<bits<5> f, string asmstr,
361 InstrItinClass itin> :
362 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
363 !strconcat(asmstr, "\t$rz, $ry"),
365 let Constraints = "$rx = $rz";
369 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
370 string asmstr, InstrItinClass itin>:
371 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
375 class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
376 string asmstr, InstrItinClass itin>:
377 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
378 !strconcat(asmstr, "\t $rx"), [], itin> ;
381 <bits<5> _funct, bits<3> _subfunc,
382 string asmstr, InstrItinClass itin>:
383 FRR_SF16<_funct, _subfunc, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_),
384 !strconcat(asmstr, "\t $rx"),
386 let Constraints = "$rx_ = $rx";
389 // RRR-type instruction format
392 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
393 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
394 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
397 // These Sel patterns support the generation of conditional move
398 // pseudo instructions.
400 // The nomenclature uses the components making up the pseudo and may
401 // be a bit counter intuitive when compared with the end result we seek.
402 // For example using a bqez in the example directly below results in the
403 // conditional move being done if the tested register is not zero.
404 // I considered in easier to check by keeping the pseudo consistent with
405 // it's components but it could have been done differently.
407 // The simplest case is when can test and operand directly and do the
408 // conditional move based on a simple mips16 conditional
409 // branch instruction.
411 // if $op == beqz or bnez:
416 // if $op == beqz, then if $rt != 0, then the conditional assignment
417 // $rd = $rs is done.
419 // if $op == bnez, then if $rt == 0, then the conditional assignment
420 // $rd = $rs is done.
422 // So this pseudo class only has one operand, i.e. op
424 class Sel<string op>:
425 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
427 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> {
428 //let isCodeGenOnly=1;
429 let Constraints = "$rd = $rd_";
430 let usesCustomInserter = 1;
434 // The next two instruction classes allow for an operand which tests
435 // two operands and returns a value in register T8 and
436 //then does a conditional branch based on the value of T8
439 // op2 can be cmpi or slti/sltiu
440 // op1 can bteqz or btnez
441 // the operands for op2 are a register and a signed constant
443 // $op2 $t, $imm ;test register t and branch conditionally
444 // $op1 .+4 ;op1 is a conditional branch
448 class SeliT<string op1, string op2>:
449 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
450 CPU16Regs:$rl, simm16:$imm),
452 !strconcat("\t$rl, $imm\n\t",
453 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
455 let Constraints = "$rd = $rd_";
456 let usesCustomInserter = 1;
460 // op2 can be cmp or slt/sltu
461 // op1 can be bteqz or btnez
462 // the operands for op2 are two registers
463 // op1 is a conditional branch
466 // $op2 $rl, $rr ;test registers rl,rr
467 // $op1 .+4 ;op2 is a conditional branch
471 class SelT<string op1, string op2>:
472 MipsPseudo16<(outs CPU16Regs:$rd_),
473 (ins CPU16Regs:$rd, CPU16Regs:$rs,
474 CPU16Regs:$rl, CPU16Regs:$rr),
476 !strconcat("\t$rl, $rr\n\t",
477 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
479 let Constraints = "$rd = $rd_";
480 let usesCustomInserter = 1;
486 def imm32: Operand<i32>;
489 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
492 MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm, imm32:$constid),
493 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
497 // Some general instruction class info
501 class ArithLogic16Defs<bit isCom=0> {
503 bit isCommutable = isCom;
504 bit isReMaterializable = 1;
505 bit hasSideEffects = 0;
510 bit isTerminator = 1;
516 bit isTerminator = 1;
529 // Format: ADDIU rx, immediate MIPS16e
530 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
531 // To add a constant to a 32-bit integer.
533 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
535 def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>,
536 ArithLogic16Defs<0> {
537 let AddedComplexity = 5;
539 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
540 ArithLogic16Defs<0> {
541 let isCodeGenOnly = 1;
544 def AddiuRxRyOffMemX16:
545 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>;
549 // Format: ADDIU rx, pc, immediate MIPS16e
550 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
551 // To add a constant to the program counter.
553 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
556 // Format: ADDIU sp, immediate MIPS16e
557 // Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
558 // To add a constant to the stack pointer.
561 : FI816_SP_ins<0b011, "addiu", IIAlu> {
564 let AddedComplexity = 5;
568 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
574 // Format: ADDU rz, rx, ry MIPS16e
575 // Purpose: Add Unsigned Word (3-Operand)
576 // To add 32-bit integers.
579 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
582 // Format: AND rx, ry MIPS16e
584 // To do a bitwise logical AND.
586 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
590 // Format: BEQZ rx, offset MIPS16e
591 // Purpose: Branch on Equal to Zero
592 // To test a GPR then do a PC-relative conditional branch.
594 def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
598 // Format: BEQZ rx, offset MIPS16e
599 // Purpose: Branch on Equal to Zero (Extended)
600 // To test a GPR then do a PC-relative conditional branch.
602 def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
605 // Format: B offset MIPS16e
606 // Purpose: Unconditional Branch (Extended)
607 // To do an unconditional PC-relative branch.
610 def Bimm16: FI16_ins<0b00010, "b", IIAlu>, branch16;
612 // Format: B offset MIPS16e
613 // Purpose: Unconditional Branch
614 // To do an unconditional PC-relative branch.
616 def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
619 // Format: BNEZ rx, offset MIPS16e
620 // Purpose: Branch on Not Equal to Zero
621 // To test a GPR then do a PC-relative conditional branch.
623 def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
626 // Format: BNEZ rx, offset MIPS16e
627 // Purpose: Branch on Not Equal to Zero (Extended)
628 // To test a GPR then do a PC-relative conditional branch.
630 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
634 //Format: BREAK immediate
635 // Purpose: Breakpoint
636 // To cause a Breakpoint exception.
638 def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>;
640 // Format: BTEQZ offset MIPS16e
641 // Purpose: Branch on T Equal to Zero (Extended)
642 // To test special register T then do a PC-relative conditional branch.
644 def Bteqz16: FI816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
648 def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
652 def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16;
654 def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">,
657 def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16;
659 def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;
661 def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16;
663 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
667 // Format: BTNEZ offset MIPS16e
668 // Purpose: Branch on T Not Equal to Zero (Extended)
669 // To test special register T then do a PC-relative conditional branch.
672 def Btnez16: FI816_ins<0b001, "btnez", IIAlu>, cbranch16 {
676 def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 {
680 def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16;
682 def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16;
684 def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16;
686 def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;
688 def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16;
690 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
694 // Format: CMP rx, ry MIPS16e
696 // To compare the contents of two GPRs.
698 def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> {
703 // Format: CMPI rx, immediate MIPS16e
704 // Purpose: Compare Immediate
705 // To compare a constant with the contents of a GPR.
707 def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> {
712 // Format: CMPI rx, immediate MIPS16e
713 // Purpose: Compare Immediate (Extended)
714 // To compare a constant with the contents of a GPR.
716 def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> {
722 // Format: DIV rx, ry MIPS16e
723 // Purpose: Divide Word
724 // To divide 32-bit signed integers.
726 def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
727 let Defs = [HI0, LO0];
731 // Format: DIVU rx, ry MIPS16e
732 // Purpose: Divide Unsigned Word
733 // To divide 32-bit unsigned integers.
735 def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
736 let Defs = [HI0, LO0];
739 // Format: JAL target MIPS16e
740 // Purpose: Jump and Link
741 // To execute a procedure call within the current 256 MB-aligned
742 // region and preserve the current ISA.
745 def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
746 let hasDelaySlot = 0; // not true, but we add the nop for now
751 def JalB16 : FJALB16_ins<0b0, "jal", IIAlu>, branch16 {
752 let hasDelaySlot = 0; // not true, but we add the nop for now
758 // Format: JR ra MIPS16e
759 // Purpose: Jump Register Through Register ra
760 // To execute a branch to the instruction address in the return
764 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
766 let isIndirectBranch = 1;
767 let hasDelaySlot = 1;
772 def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> {
774 let isIndirectBranch = 1;
779 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
781 let isIndirectBranch = 1;
786 // Format: LB ry, offset(rx) MIPS16e
787 // Purpose: Load Byte (Extended)
788 // To load a byte from memory as a signed value.
790 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, II_LB>, MayLoad{
791 let isCodeGenOnly = 1;
795 // Format: LBU ry, offset(rx) MIPS16e
796 // Purpose: Load Byte Unsigned (Extended)
797 // To load a byte from memory as a unsigned value.
799 def LbuRxRyOffMemX16:
800 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, II_LBU>, MayLoad {
801 let isCodeGenOnly = 1;
805 // Format: LH ry, offset(rx) MIPS16e
806 // Purpose: Load Halfword signed (Extended)
807 // To load a halfword from memory as a signed value.
809 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, II_LH>, MayLoad{
810 let isCodeGenOnly = 1;
814 // Format: LHU ry, offset(rx) MIPS16e
815 // Purpose: Load Halfword unsigned (Extended)
816 // To load a halfword from memory as an unsigned value.
818 def LhuRxRyOffMemX16:
819 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, II_LHU>, MayLoad {
820 let isCodeGenOnly = 1;
824 // Format: LI rx, immediate MIPS16e
825 // Purpose: Load Immediate
826 // To load a constant into a GPR.
828 def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>;
831 // Format: LI rx, immediate MIPS16e
832 // Purpose: Load Immediate (Extended)
833 // To load a constant into a GPR.
835 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
837 def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIAlu> {
838 let isCodeGenOnly = 1;
842 // Format: LW ry, offset(rx) MIPS16e
843 // Purpose: Load Word (Extended)
844 // To load a word from memory as a signed value.
846 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, II_LW>, MayLoad{
847 let isCodeGenOnly = 1;
850 // Format: LW rx, offset(sp) MIPS16e
851 // Purpose: Load Word (SP-Relative, Extended)
852 // To load an SP-relative word from memory as a signed value.
854 def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10010, "lw", II_LW>, MayLoad{
858 def LwRxPcTcp16: FRI16_TCP_ins<0b10110, "lw", II_LW>, MayLoad;
860 def LwRxPcTcpX16: FEXT_RI16_TCP_ins<0b10110, "lw", II_LW>, MayLoad;
862 // Format: MOVE r32, rz MIPS16e
864 // To move the contents of a GPR to a GPR.
866 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
869 // Format: MOVE ry, r32 MIPS16e
871 // To move the contents of a GPR to a GPR.
873 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
876 // Format: MFHI rx MIPS16e
877 // Purpose: Move From HI Register
878 // To copy the special purpose HI register to a GPR.
880 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
882 let hasSideEffects = 0;
886 // Format: MFLO rx MIPS16e
887 // Purpose: Move From LO Register
888 // To copy the special purpose LO register to a GPR.
890 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
892 let hasSideEffects = 0;
896 // Pseudo Instruction for mult
898 def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
899 let isCommutable = 1;
900 let hasSideEffects = 0;
901 let Defs = [HI0, LO0];
904 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
905 let isCommutable = 1;
906 let hasSideEffects = 0;
907 let Defs = [HI0, LO0];
911 // Format: MULT rx, ry MIPS16e
912 // Purpose: Multiply Word
913 // To multiply 32-bit signed integers.
915 def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
916 let isCommutable = 1;
917 let hasSideEffects = 0;
918 let Defs = [HI0, LO0];
922 // Format: MULTU rx, ry MIPS16e
923 // Purpose: Multiply Unsigned Word
924 // To multiply 32-bit unsigned integers.
926 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
927 let isCommutable = 1;
928 let hasSideEffects = 0;
929 let Defs = [HI0, LO0];
933 // Format: NEG rx, ry MIPS16e
935 // To negate an integer value.
937 def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
940 // Format: NOT rx, ry MIPS16e
942 // To complement an integer value
944 def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
947 // Format: OR rx, ry MIPS16e
949 // To do a bitwise logical OR.
951 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
954 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
955 // (All args are optional) MIPS16e
956 // Purpose: Restore Registers and Deallocate Stack Frame
957 // To deallocate a stack frame before exit from a subroutine,
958 // restoring return address and static registers, and adjusting
963 FI8_SVRS16<0b1, (outs), (ins variable_ops),
964 "", [], II_RESTORE >, MayLoad {
965 let isCodeGenOnly = 1;
972 FI8_SVRS16<0b1, (outs), (ins variable_ops),
973 "", [], II_RESTORE >, MayLoad {
974 let isCodeGenOnly = 1;
980 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
982 // Purpose: Save Registers and Set Up Stack Frame
983 // To set up a stack frame on entry to a subroutine,
984 // saving return address and static registers, and adjusting stack
987 FI8_SVRS16<0b1, (outs), (ins variable_ops),
988 "", [], II_SAVE >, MayStore {
989 let isCodeGenOnly = 1;
995 FI8_SVRS16<0b1, (outs), (ins variable_ops),
996 "", [], II_SAVE >, MayStore {
997 let isCodeGenOnly = 1;
1002 // Format: SB ry, offset(rx) MIPS16e
1003 // Purpose: Store Byte (Extended)
1004 // To store a byte to memory.
1006 def SbRxRyOffMemX16:
1007 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, II_SB>, MayStore;
1010 // Format: SEB rx MIPS16e
1011 // Purpose: Sign-Extend Byte
1012 // Sign-extend least significant byte in register rx.
1015 : FRR_SF16_ins<0b10001, 0b100, "seb", IIAlu>;
1018 // Format: SEH rx MIPS16e
1019 // Purpose: Sign-Extend Halfword
1020 // Sign-extend least significant word in register rx.
1023 : FRR_SF16_ins<0b10001, 0b101, "seh", IIAlu>;
1026 // The Sel(T) instructions are pseudos
1027 // T means that they use T8 implicitly.
1030 // Format: SelBeqZ rd, rs, rt
1031 // Purpose: if rt==0, do nothing
1034 def SelBeqZ: Sel<"beqz">;
1037 // Format: SelTBteqZCmp rd, rs, rl, rr
1038 // Purpose: b = Cmp rl, rr.
1039 // If b==0 then do nothing.
1040 // if b!=0 then rd = rs
1042 def SelTBteqZCmp: SelT<"bteqz", "cmp">;
1045 // Format: SelTBteqZCmpi rd, rs, rl, rr
1046 // Purpose: b = Cmpi rl, imm.
1047 // If b==0 then do nothing.
1048 // if b!=0 then rd = rs
1050 def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">;
1053 // Format: SelTBteqZSlt rd, rs, rl, rr
1054 // Purpose: b = Slt rl, rr.
1055 // If b==0 then do nothing.
1056 // if b!=0 then rd = rs
1058 def SelTBteqZSlt: SelT<"bteqz", "slt">;
1061 // Format: SelTBteqZSlti rd, rs, rl, rr
1062 // Purpose: b = Slti rl, imm.
1063 // If b==0 then do nothing.
1064 // if b!=0 then rd = rs
1066 def SelTBteqZSlti: SeliT<"bteqz", "slti">;
1069 // Format: SelTBteqZSltu rd, rs, rl, rr
1070 // Purpose: b = Sltu rl, rr.
1071 // If b==0 then do nothing.
1072 // if b!=0 then rd = rs
1074 def SelTBteqZSltu: SelT<"bteqz", "sltu">;
1077 // Format: SelTBteqZSltiu rd, rs, rl, rr
1078 // Purpose: b = Sltiu rl, imm.
1079 // If b==0 then do nothing.
1080 // if b!=0 then rd = rs
1082 def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">;
1085 // Format: SelBnez rd, rs, rt
1086 // Purpose: if rt!=0, do nothing
1089 def SelBneZ: Sel<"bnez">;
1092 // Format: SelTBtneZCmp rd, rs, rl, rr
1093 // Purpose: b = Cmp rl, rr.
1094 // If b!=0 then do nothing.
1095 // if b0=0 then rd = rs
1097 def SelTBtneZCmp: SelT<"btnez", "cmp">;
1100 // Format: SelTBtnezCmpi rd, rs, rl, rr
1101 // Purpose: b = Cmpi rl, imm.
1102 // If b!=0 then do nothing.
1103 // if b==0 then rd = rs
1105 def SelTBtneZCmpi: SeliT<"btnez", "cmpi">;
1108 // Format: SelTBtneZSlt rd, rs, rl, rr
1109 // Purpose: b = Slt rl, rr.
1110 // If b!=0 then do nothing.
1111 // if b==0 then rd = rs
1113 def SelTBtneZSlt: SelT<"btnez", "slt">;
1116 // Format: SelTBtneZSlti rd, rs, rl, rr
1117 // Purpose: b = Slti rl, imm.
1118 // If b!=0 then do nothing.
1119 // if b==0 then rd = rs
1121 def SelTBtneZSlti: SeliT<"btnez", "slti">;
1124 // Format: SelTBtneZSltu rd, rs, rl, rr
1125 // Purpose: b = Sltu rl, rr.
1126 // If b!=0 then do nothing.
1127 // if b==0 then rd = rs
1129 def SelTBtneZSltu: SelT<"btnez", "sltu">;
1132 // Format: SelTBtneZSltiu rd, rs, rl, rr
1133 // Purpose: b = Slti rl, imm.
1134 // If b!=0 then do nothing.
1135 // if b==0 then rd = rs
1137 def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
1140 // Format: SH ry, offset(rx) MIPS16e
1141 // Purpose: Store Halfword (Extended)
1142 // To store a halfword to memory.
1144 def ShRxRyOffMemX16:
1145 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, II_SH>, MayStore;
1148 // Format: SLL rx, ry, sa MIPS16e
1149 // Purpose: Shift Word Left Logical (Extended)
1150 // To execute a left-shift of a word by a fixed number of bits-0 to 31 bits.
1152 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
1155 // Format: SLLV ry, rx MIPS16e
1156 // Purpose: Shift Word Left Logical Variable
1157 // To execute a left-shift of a word by a variable number of bits.
1159 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
1161 // Format: SLTI rx, immediate MIPS16e
1162 // Purpose: Set on Less Than Immediate
1163 // To record the result of a less-than comparison with a constant.
1166 def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> {
1171 // Format: SLTI rx, immediate MIPS16e
1172 // Purpose: Set on Less Than Immediate (Extended)
1173 // To record the result of a less-than comparison with a constant.
1176 def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> {
1180 def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
1182 // Format: SLTIU rx, immediate MIPS16e
1183 // Purpose: Set on Less Than Immediate Unsigned
1184 // To record the result of a less-than comparison with a constant.
1187 def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> {
1192 // Format: SLTI rx, immediate MIPS16e
1193 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1194 // To record the result of a less-than comparison with a constant.
1197 def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> {
1201 // Format: SLTIU rx, immediate MIPS16e
1202 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1203 // To record the result of a less-than comparison with a constant.
1205 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
1208 // Format: SLT rx, ry MIPS16e
1209 // Purpose: Set on Less Than
1210 // To record the result of a less-than comparison.
1212 def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{
1216 def SltCCRxRy16: FCCRR16_ins<"slt">;
1218 // Format: SLTU rx, ry MIPS16e
1219 // Purpose: Set on Less Than Unsigned
1220 // To record the result of an unsigned less-than comparison.
1222 def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{
1226 def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
1227 let isCodeGenOnly=1;
1232 def SltuCCRxRy16: FCCRR16_ins<"sltu">;
1234 // Format: SRAV ry, rx MIPS16e
1235 // Purpose: Shift Word Right Arithmetic Variable
1236 // To execute an arithmetic right-shift of a word by a variable
1239 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
1243 // Format: SRA rx, ry, sa MIPS16e
1244 // Purpose: Shift Word Right Arithmetic (Extended)
1245 // To execute an arithmetic right-shift of a word by a fixed
1246 // number of bits-1 to 8 bits.
1248 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
1252 // Format: SRLV ry, rx MIPS16e
1253 // Purpose: Shift Word Right Logical Variable
1254 // To execute a logical right-shift of a word by a variable
1257 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
1261 // Format: SRL rx, ry, sa MIPS16e
1262 // Purpose: Shift Word Right Logical (Extended)
1263 // To execute a logical right-shift of a word by a fixed
1264 // number of bits-1 to 31 bits.
1266 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
1269 // Format: SUBU rz, rx, ry MIPS16e
1270 // Purpose: Subtract Unsigned Word
1271 // To subtract 32-bit integers
1273 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
1276 // Format: SW ry, offset(rx) MIPS16e
1277 // Purpose: Store Word (Extended)
1278 // To store a word to memory.
1280 def SwRxRyOffMemX16:
1281 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, II_SW>, MayStore;
1284 // Format: SW rx, offset(sp) MIPS16e
1285 // Purpose: Store Word rx (SP-Relative)
1286 // To store an SP-relative word to memory.
1288 def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins
1289 <0b11010, "sw", II_SW>, MayStore;
1293 // Format: XOR rx, ry MIPS16e
1295 // To do a bitwise logical XOR.
1297 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
1299 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
1300 let Predicates = [InMips16Mode];
1303 // Unary Arith/Logic
1305 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1306 Mips16Pat<(OpNode CPU16Regs:$r),
1309 def: ArithLogicU_pat<not, NotRxRy16>;
1310 def: ArithLogicU_pat<ineg, NegRxRy16>;
1312 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1313 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1314 (I CPU16Regs:$l, CPU16Regs:$r)>;
1316 def: ArithLogic16_pat<add, AdduRxRyRz16>;
1317 def: ArithLogic16_pat<and, AndRxRxRy16>;
1318 def: ArithLogic16_pat<mul, MultRxRyRz16>;
1319 def: ArithLogic16_pat<or, OrRxRxRy16>;
1320 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
1321 def: ArithLogic16_pat<xor, XorRxRxRy16>;
1323 // Arithmetic and logical instructions with 2 register operands.
1325 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1326 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1327 (I CPU16Regs:$in, imm_type:$imm)>;
1329 def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>;
1330 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
1331 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
1332 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
1333 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
1335 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1336 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1337 (I CPU16Regs:$r, CPU16Regs:$ra)>;
1339 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
1340 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
1341 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
1343 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1344 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
1346 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
1347 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
1348 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
1349 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
1350 def: LoadM16_pat<load, LwRxRyOffMemX16>;
1352 class StoreM16_pat<PatFrag OpNode, Instruction I> :
1353 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr),
1354 (I CPU16Regs:$r, addr16:$addr)>;
1356 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
1357 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
1358 def: StoreM16_pat<store, SwRxRyOffMemX16>;
1360 // Unconditional branch
1361 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
1362 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1363 let Predicates = [InMips16Mode];
1366 def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1367 (Jal16 tglobaladdr:$dst)>;
1369 def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)),
1370 (Jal16 texternalsym:$dst)>;
1373 def: Mips16Pat<(brind CPU16Regs:$rs), (JrcRx16 CPU16Regs:$rs)> {
1374 // Ensure that the addition of MIPS32r6/MIPS64r6 support does not change
1375 // MIPS16's behaviour.
1376 let AddedComplexity = 1;
1379 // Jump and Link (Call)
1380 let isCall=1, hasDelaySlot=0 in
1382 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
1383 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch> {
1388 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
1389 hasExtraSrcRegAllocReq = 1 in
1390 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
1395 class SetCC_R16<PatFrag cond_op, Instruction I>:
1396 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1397 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1399 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1400 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1401 (I CPU16Regs:$rx, imm_type:$imm16)>;
1404 def: Mips16Pat<(i32 addr16:$addr),
1405 (AddiuRxRyOffMemX16 addr16:$addr)>;
1408 // Large (>16 bit) immediate loads
1409 def : Mips16Pat<(i32 imm:$imm), (LwConstant32 imm:$imm, -1)>;
1411 // Carry MipsPatterns
1412 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
1413 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1414 def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
1415 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1416 def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
1417 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
1420 // Some branch conditional patterns are not generated by llvm at this time.
1421 // Some are for seemingly arbitrary reasons not used: i.e. with signed number
1422 // comparison they are used and for unsigned a different pattern is used.
1423 // I am pushing upstream from the full mips16 port and it seemed that I needed
1424 // these earlier and the mips32 port has these but now I cannot create test
1425 // cases that use these patterns. While I sort this all out I will leave these
1426 // extra patterns commented out and if I can be sure they are really not used,
1427 // I will delete the code. I don't want to check the code in uncommented without
1428 // a valid test case. In some cases, the compiler is generating patterns with
1429 // setcc instead and earlier I had implemented setcc first so may have masked
1430 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
1431 // figure out how to enable the brcond patterns or else possibly new
1432 // combinations of of brcond and setcc.
1438 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1439 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1444 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1445 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1449 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1450 (BeqzRxImm16 CPU16Regs:$rx, bb:$targ16)
1454 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1457 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1458 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1465 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1466 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1470 // never called because compiler transforms a >= k to a > (k-1)
1472 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1473 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1480 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1481 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1485 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1486 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1493 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1494 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1501 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1502 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1506 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1507 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1511 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1512 (BnezRxImm16 CPU16Regs:$rx, bb:$targ16)
1516 // This needs to be there but I forget which code will generate it
1519 <(brcond CPU16Regs:$rx, bb:$targ16),
1520 (BnezRxImm16 CPU16Regs:$rx, bb:$targ16)
1529 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1530 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1537 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1538 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1546 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1547 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1550 def: UncondBranch16_pat<br, Bimm16>;
1553 def: Mips16Pat<(i32 immSExt16:$in),
1554 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
1556 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
1562 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry),
1563 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1569 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry),
1570 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1575 // if !(a < b) x = y
1577 def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1578 CPU16Regs:$x, CPU16Regs:$y),
1579 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1580 CPU16Regs:$a, CPU16Regs:$b)>;
1587 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1588 CPU16Regs:$x, CPU16Regs:$y),
1589 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
1590 CPU16Regs:$b, CPU16Regs:$a)>;
1595 // if !(a < b) x = y;
1598 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
1599 CPU16Regs:$x, CPU16Regs:$y),
1600 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1601 CPU16Regs:$a, CPU16Regs:$b)>;
1608 def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
1609 CPU16Regs:$x, CPU16Regs:$y),
1610 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
1611 CPU16Regs:$b, CPU16Regs:$a)>;
1615 // due to an llvm optimization, i don't think that this will ever
1616 // be used. This is transformed into x = (a > k-1)?x:y
1621 // (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1622 // CPU16Regs:$T, CPU16Regs:$F),
1623 // (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
1624 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1627 // (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
1628 // CPU16Regs:$T, CPU16Regs:$F),
1629 // (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
1630 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1635 // if !(a < k) x = y;
1638 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1639 CPU16Regs:$x, CPU16Regs:$y),
1640 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
1641 CPU16Regs:$a, immSExt16:$b)>;
1647 // x = (a <= b)? x : y
1651 def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
1652 CPU16Regs:$x, CPU16Regs:$y),
1653 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1654 CPU16Regs:$b, CPU16Regs:$a)>;
1658 // x = (a <= b)? x : y
1662 def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
1663 CPU16Regs:$x, CPU16Regs:$y),
1664 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1665 CPU16Regs:$b, CPU16Regs:$a)>;
1669 // x = (a == b)? x : y
1671 // if (a != b) x = y
1673 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
1674 CPU16Regs:$x, CPU16Regs:$y),
1675 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
1676 CPU16Regs:$b, CPU16Regs:$a)>;
1680 // x = (a == 0)? x : y
1682 // if (a != 0) x = y
1684 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
1685 CPU16Regs:$x, CPU16Regs:$y),
1686 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
1692 // x = (a == k)? x : y
1694 // if (a != k) x = y
1696 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
1697 CPU16Regs:$x, CPU16Regs:$y),
1698 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
1699 CPU16Regs:$a, immZExt16:$k)>;
1704 // x = (a != b)? x : y
1706 // if (a == b) x = y
1709 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1710 CPU16Regs:$x, CPU16Regs:$y),
1711 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
1712 CPU16Regs:$b, CPU16Regs:$a)>;
1716 // x = (a != 0)? x : y
1718 // if (a == 0) x = y
1720 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1721 CPU16Regs:$x, CPU16Regs:$y),
1722 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1730 def : Mips16Pat<(select CPU16Regs:$a,
1731 CPU16Regs:$x, CPU16Regs:$y),
1732 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1738 // x = (a != k)? x : y
1740 // if (a == k) x = y
1742 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1743 CPU16Regs:$x, CPU16Regs:$y),
1744 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
1745 CPU16Regs:$a, immZExt16:$k)>;
1748 // When writing C code to test setxx these patterns,
1749 // some will be transformed into
1750 // other things. So we test using C code but using -O3 and -O0
1755 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
1756 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
1759 <(seteq CPU16Regs:$lhs, 0),
1760 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
1768 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1769 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1773 // For constants, llvm transforms this to:
1774 // x > (k - 1) and then reverses the operands to use setlt. So this pattern
1775 // is not used now by the compiler. (Presumably checking that k-1 does not
1776 // overflow). The compiler never uses this at the current time, due to
1777 // other optimizations.
1780 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
1781 // (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
1782 // (LiRxImmX16 1))>;
1784 // This catches the x >= -32768 case by transforming it to x > -32769
1787 <(setgt CPU16Regs:$lhs, -32769),
1788 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
1797 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
1798 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1804 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
1805 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>;
1810 def: SetCC_R16<setlt, SltCCRxRy16>;
1812 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
1818 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
1819 (SltuCCRxRy16 (LiRxImmX16 0),
1820 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1827 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1828 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1831 // this pattern will never be used because the compiler will transform
1832 // x >= k to x > (k - 1) and then use SLT
1835 // <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1836 // (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1837 // (LiRxImmX16 1))>;
1843 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1844 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1850 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1851 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1856 def: SetCC_R16<setult, SltuCCRxRy16>;
1858 def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1860 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1861 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
1864 def : Mips16Pat<(MipsHi tblockaddress:$in),
1865 (SllX16 (LiRxImmX16 tblockaddress:$in), 16)>;
1866 def : Mips16Pat<(MipsHi tglobaladdr:$in),
1867 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>;
1868 def : Mips16Pat<(MipsHi tjumptable:$in),
1869 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>;
1870 def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
1871 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
1873 def : Mips16Pat<(MipsLo tblockaddress:$in), (LiRxImmX16 tblockaddress:$in)>;
1876 class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1877 Mips16Pat<(MipsWrapper RC:$gp, node:$in),
1878 (ADDiuOp RC:$gp, node:$in)>;
1881 def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>;
1882 def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
1884 def : Mips16Pat<(i32 (extloadi8 addr16:$src)),
1885 (LbuRxRyOffMemX16 addr16:$src)>;
1886 def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
1887 (LhuRxRyOffMemX16 addr16:$src)>;
1889 def: Mips16Pat<(trap), (Break16)>;
1891 def : Mips16Pat<(sext_inreg CPU16Regs:$val, i8),
1892 (SebRx16 CPU16Regs:$val)>;
1894 def : Mips16Pat<(sext_inreg CPU16Regs:$val, i16),
1895 (SehRx16 CPU16Regs:$val)>;
1899 (outs CPU16Regs:$rh, CPU16Regs:$rl),
1900 (ins simm16:$immHi, simm16:$immLo),
1901 "li\t$rh, $immHi\n\taddiu\t$rl, $$pc, $immLo\n ",[]> ;
1903 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
1904 def cpinst_operand : Operand<i32> {
1905 // let PrintMethod = "printCPInstOperand";
1908 // CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1909 // the function. The first operand is the ID# for this instruction, the second
1910 // is the index into the MachineConstantPool that this is, the third is the
1911 // size in bytes of this constant pool entry.
1913 let hasSideEffects = 0, isNotDuplicable = 1 in
1914 def CONSTPOOL_ENTRY :
1915 MipsPseudo16<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1916 i32imm:$size), "foo", []>;