1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
18 ComplexPattern<iPTR, 3, "SelectAddr16", [frameindex], [SDNPWantParent]>;
22 def mem16 : Operand<i32> {
23 let PrintMethod = "printMemOperand";
24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16Regs);
25 let EncoderMethod = "getMemEncoding";
28 def mem16_ea : Operand<i32> {
29 let PrintMethod = "printMemOperandEA";
30 let MIOperandInfo = (ops CPU16Regs, simm16);
31 let EncoderMethod = "getMemEncoding";
36 // I8 instruction format
39 class FI816_ins_base<bits<3> _func, string asmstr,
40 string asmstr2, InstrItinClass itin>:
41 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
45 class FI816_SP_ins<bits<3> _func, string asmstr,
47 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
50 // RI instruction format
54 class F2RI16_ins<bits<5> _op, string asmstr,
56 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
57 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
58 let Constraints = "$rx_ = $rx";
62 // Compare a register and immediate and place result in CC
65 // EXT-CCRR Instruction format
67 class FEXT_CCRXI16_ins<bits<5> _op, string asmstr,
69 FEXT_RI16<_op, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
70 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), [], itin> {
74 // JAL and JALX instruction format
76 class FJAL16_ins<bits<1> _X, string asmstr,
78 FJAL16<_X, (outs), (ins simm20:$imm),
79 !strconcat(asmstr, "\t$imm\n\tnop"),[],
84 // EXT-I instruction format
86 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
87 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
88 !strconcat(asmstr, "\t$imm16"),[], itin>;
91 // EXT-I8 instruction format
94 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
95 string asmstr2, InstrItinClass itin>:
96 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
99 class FEXT_I816_ins<bits<3> _func, string asmstr,
100 InstrItinClass itin>:
101 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
103 class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
104 InstrItinClass itin>:
105 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>;
108 // Assembler formats in alphabetical order.
109 // Natural and pseudos are mixed together.
111 // Compare two registers and place result in CC
112 // Implicit use of T8
114 // CC-RR Instruction format
116 class FCCRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
117 FRR16<f, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
118 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), [], itin> {
123 // EXT-RI instruction format
126 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
127 InstrItinClass itin>:
128 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
129 !strconcat(asmstr, asmstr2), [], itin>;
131 class FEXT_RI16_ins<bits<5> _op, string asmstr,
132 InstrItinClass itin>:
133 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
135 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
136 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
138 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
139 InstrItinClass itin>:
140 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
141 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
143 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
144 InstrItinClass itin>:
145 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
146 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
147 let Constraints = "$rx_ = $rx";
151 // this has an explicit sp argument that we ignore to work around a problem
153 class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
154 InstrItinClass itin>:
155 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
156 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
159 // EXT-RRI instruction format
162 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
163 InstrItinClass itin>:
164 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
165 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
167 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
168 InstrItinClass itin>:
169 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
170 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
174 // EXT-RRI-A instruction format
177 class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
178 InstrItinClass itin>:
179 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
180 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
183 // EXT-SHIFT instruction format
185 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
186 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
187 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
192 class FEXT_T8I816_ins<bits<3> _func, string asmstr, string asmstr2,
193 InstrItinClass itin>:
194 FEXT_I816<_func, (outs),
195 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
196 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
197 !strconcat(asmstr, "\t$imm"))),[], itin> {
204 class FEXT_T8I8I16_ins<bits<3> _func, string asmstr, string asmstr2,
205 InstrItinClass itin>:
206 FEXT_I816<_func, (outs),
207 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
208 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
209 !strconcat(asmstr, "\t$targ"))), [], itin> {
216 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
218 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
219 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32),
220 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
223 // I8_MOV32R instruction format (used only by MOV32R instruction)
226 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
227 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
228 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
231 // This are pseudo formats for multiply
232 // This first one can be changed to non pseudo now.
236 class FMULT16_ins<string asmstr, InstrItinClass itin> :
237 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
238 !strconcat(asmstr, "\t$rx, $ry"), []>;
243 class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
244 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
245 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
250 // RR-type instruction format
253 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
254 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
255 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
258 class FRRTR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
259 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
260 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), [], itin> ;
263 // maybe refactor but need a $zero as a dummy first parameter
265 class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
266 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
267 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
269 class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
270 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
271 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
274 class FRR16_M_ins<bits<5> f, string asmstr,
275 InstrItinClass itin> :
276 FRR16<f, (outs CPU16Regs:$rx), (ins),
277 !strconcat(asmstr, "\t$rx"), [], itin>;
279 class FRxRxRy16_ins<bits<5> f, string asmstr,
280 InstrItinClass itin> :
281 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
282 !strconcat(asmstr, "\t$rz, $ry"),
284 let Constraints = "$rx = $rz";
288 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
289 string asmstr, InstrItinClass itin>:
290 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
294 class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
295 string asmstr, InstrItinClass itin>:
296 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
297 !strconcat(asmstr, "\t $rx"), [], itin> ;
300 // RRR-type instruction format
303 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
304 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
305 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
308 // These Sel patterns support the generation of conditional move
309 // pseudo instructions.
311 // The nomenclature uses the components making up the pseudo and may
312 // be a bit counter intuitive when compared with the end result we seek.
313 // For example using a bqez in the example directly below results in the
314 // conditional move being done if the tested register is not zero.
315 // I considered in easier to check by keeping the pseudo consistent with
316 // it's components but it could have been done differently.
318 // The simplest case is when can test and operand directly and do the
319 // conditional move based on a simple mips16 conditional
320 // branch instruction.
322 // if $op == beqz or bnez:
327 // if $op == beqz, then if $rt != 0, then the conditional assignment
328 // $rd = $rs is done.
330 // if $op == bnez, then if $rt == 0, then the conditional assignment
331 // $rd = $rs is done.
333 // So this pseudo class only has one operand, i.e. op
335 class Sel<bits<5> f1, string op, InstrItinClass itin>:
336 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
338 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), [], itin> {
340 let Constraints = "$rd = $rd_";
344 // The next two instruction classes allow for an operand which tests
345 // two operands and returns a value in register T8 and
346 //then does a conditional branch based on the value of T8
349 // op2 can be cmpi or slti/sltiu
350 // op1 can bteqz or btnez
351 // the operands for op2 are a register and a signed constant
353 // $op2 $t, $imm ;test register t and branch conditionally
354 // $op1 .+4 ;op1 is a conditional branch
358 class SeliT<bits<5> f1, string op1, bits<5> f2, string op2,
359 InstrItinClass itin>:
360 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
361 CPU16Regs:$rl, simm16:$imm),
363 !strconcat("\t$rl, $imm\n\t",
364 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin> {
366 let Constraints = "$rd = $rd_";
370 // op2 can be cmp or slt/sltu
371 // op1 can be bteqz or btnez
372 // the operands for op2 are two registers
373 // op1 is a conditional branch
376 // $op2 $rl, $rr ;test registers rl,rr
377 // $op1 .+4 ;op2 is a conditional branch
381 class SelT<bits<5> f1, string op1, bits<5> f2, string op2,
382 InstrItinClass itin>:
383 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
384 CPU16Regs:$rl, CPU16Regs:$rr),
386 !strconcat("\t$rl, $rr\n\t",
387 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin> {
389 let Constraints = "$rd = $rd_";
395 def imm32: Operand<i32>;
398 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
401 MipsPseudo16<(outs), (ins CPU16Regs:$rx, imm32:$imm),
402 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
406 // Some general instruction class info
410 class ArithLogic16Defs<bit isCom=0> {
412 bit isCommutable = isCom;
413 bit isReMaterializable = 1;
414 bit neverHasSideEffects = 1;
419 bit isTerminator = 1;
425 bit isTerminator = 1;
437 // Format: ADDIU rx, immediate MIPS16e
438 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
439 // To add a constant to a 32-bit integer.
441 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
443 def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>,
444 ArithLogic16Defs<0> {
445 let AddedComplexity = 5;
447 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
448 ArithLogic16Defs<0> {
449 let isCodeGenOnly = 1;
452 def AddiuRxRyOffMemX16:
453 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>;
457 // Format: ADDIU rx, pc, immediate MIPS16e
458 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
459 // To add a constant to the program counter.
461 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
464 // Format: ADDIU sp, immediate MIPS16e
465 // Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
466 // To add a constant to the stack pointer.
469 : FI816_SP_ins<0b011, "addiu", IIAlu> {
472 let AddedComplexity = 5;
476 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
482 // Format: ADDU rz, rx, ry MIPS16e
483 // Purpose: Add Unsigned Word (3-Operand)
484 // To add 32-bit integers.
487 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
490 // Format: AND rx, ry MIPS16e
492 // To do a bitwise logical AND.
494 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
498 // Format: BEQZ rx, offset MIPS16e
499 // Purpose: Branch on Equal to Zero (Extended)
500 // To test a GPR then do a PC-relative conditional branch.
502 def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
504 // Format: B offset MIPS16e
505 // Purpose: Unconditional Branch
506 // To do an unconditional PC-relative branch.
508 def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
511 // Format: BNEZ rx, offset MIPS16e
512 // Purpose: Branch on Not Equal to Zero (Extended)
513 // To test a GPR then do a PC-relative conditional branch.
515 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
518 // Format: BTEQZ offset MIPS16e
519 // Purpose: Branch on T Equal to Zero (Extended)
520 // To test special register T then do a PC-relative conditional branch.
522 def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16;
524 def BteqzT8CmpX16: FEXT_T8I816_ins<0b000, "bteqz", "cmp", IIAlu>, cbranch16;
526 def BteqzT8CmpiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "cmpi", IIAlu>,
529 def BteqzT8SltX16: FEXT_T8I816_ins<0b000, "bteqz", "slt", IIAlu>, cbranch16;
531 def BteqzT8SltuX16: FEXT_T8I816_ins<0b000, "bteqz", "sltu", IIAlu>, cbranch16;
533 def BteqzT8SltiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "slti", IIAlu>, cbranch16;
535 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<0b000, "bteqz", "sltiu", IIAlu>,
539 // Format: BTNEZ offset MIPS16e
540 // Purpose: Branch on T Not Equal to Zero (Extended)
541 // To test special register T then do a PC-relative conditional branch.
543 def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16;
545 def BtnezT8CmpX16: FEXT_T8I816_ins<0b000, "btnez", "cmp", IIAlu>, cbranch16;
547 def BtnezT8CmpiX16: FEXT_T8I8I16_ins<0b000, "btnez", "cmpi", IIAlu>, cbranch16;
549 def BtnezT8SltX16: FEXT_T8I816_ins<0b000, "btnez", "slt", IIAlu>, cbranch16;
551 def BtnezT8SltuX16: FEXT_T8I816_ins<0b000, "btnez", "sltu", IIAlu>, cbranch16;
553 def BtnezT8SltiX16: FEXT_T8I8I16_ins<0b000, "btnez", "slti", IIAlu>, cbranch16;
555 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<0b000, "btnez", "sltiu", IIAlu>,
559 // Format: DIV rx, ry MIPS16e
560 // Purpose: Divide Word
561 // To divide 32-bit signed integers.
563 def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
568 // Format: DIVU rx, ry MIPS16e
569 // Purpose: Divide Unsigned Word
570 // To divide 32-bit unsigned integers.
572 def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
576 // Format: JAL target MIPS16e
577 // Purpose: Jump and Link
578 // To execute a procedure call within the current 256 MB-aligned
579 // region and preserve the current ISA.
582 def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
584 let hasDelaySlot = 0; // not true, but we add the nop for now
590 // Format: JR ra MIPS16e
591 // Purpose: Jump Register Through Register ra
592 // To execute a branch to the instruction address in the return
596 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
598 let isIndirectBranch = 1;
599 let hasDelaySlot = 1;
604 def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> {
606 let isIndirectBranch = 1;
611 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
613 let isIndirectBranch = 1;
618 // Format: LB ry, offset(rx) MIPS16e
619 // Purpose: Load Byte (Extended)
620 // To load a byte from memory as a signed value.
622 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{
623 let isCodeGenOnly = 1;
627 // Format: LBU ry, offset(rx) MIPS16e
628 // Purpose: Load Byte Unsigned (Extended)
629 // To load a byte from memory as a unsigned value.
631 def LbuRxRyOffMemX16:
632 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad {
633 let isCodeGenOnly = 1;
637 // Format: LH ry, offset(rx) MIPS16e
638 // Purpose: Load Halfword signed (Extended)
639 // To load a halfword from memory as a signed value.
641 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{
642 let isCodeGenOnly = 1;
646 // Format: LHU ry, offset(rx) MIPS16e
647 // Purpose: Load Halfword unsigned (Extended)
648 // To load a halfword from memory as an unsigned value.
650 def LhuRxRyOffMemX16:
651 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad {
652 let isCodeGenOnly = 1;
656 // Format: LI rx, immediate MIPS16e
657 // Purpose: Load Immediate (Extended)
658 // To load a constant into a GPR.
660 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
663 // Format: LW ry, offset(rx) MIPS16e
664 // Purpose: Load Word (Extended)
665 // To load a word from memory as a signed value.
667 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{
668 let isCodeGenOnly = 1;
671 // Format: LW rx, offset(sp) MIPS16e
672 // Purpose: Load Word (SP-Relative, Extended)
673 // To load an SP-relative word from memory as a signed value.
675 def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{
680 // Format: MOVE r32, rz MIPS16e
682 // To move the contents of a GPR to a GPR.
684 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
687 // Format: MOVE ry, r32 MIPS16e
689 // To move the contents of a GPR to a GPR.
691 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
694 // Format: MFHI rx MIPS16e
695 // Purpose: Move From HI Register
696 // To copy the special purpose HI register to a GPR.
698 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
700 let neverHasSideEffects = 1;
704 // Format: MFLO rx MIPS16e
705 // Purpose: Move From LO Register
706 // To copy the special purpose LO register to a GPR.
708 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
710 let neverHasSideEffects = 1;
714 // Pseudo Instruction for mult
716 def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
717 let isCommutable = 1;
718 let neverHasSideEffects = 1;
722 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
723 let isCommutable = 1;
724 let neverHasSideEffects = 1;
729 // Format: MULT rx, ry MIPS16e
730 // Purpose: Multiply Word
731 // To multiply 32-bit signed integers.
733 def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
734 let isCommutable = 1;
735 let neverHasSideEffects = 1;
740 // Format: MULTU rx, ry MIPS16e
741 // Purpose: Multiply Unsigned Word
742 // To multiply 32-bit unsigned integers.
744 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
745 let isCommutable = 1;
746 let neverHasSideEffects = 1;
751 // Format: NEG rx, ry MIPS16e
753 // To negate an integer value.
755 def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
758 // Format: NOT rx, ry MIPS16e
760 // To complement an integer value
762 def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
765 // Format: OR rx, ry MIPS16e
767 // To do a bitwise logical OR.
769 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
772 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
773 // (All args are optional) MIPS16e
774 // Purpose: Restore Registers and Deallocate Stack Frame
775 // To deallocate a stack frame before exit from a subroutine,
776 // restoring return address and static registers, and adjusting
780 // fixed form for restoring RA and the frame
781 // for direct object emitter, encoding needs to be adjusted for the
784 let ra=1, s=0,s0=1,s1=1 in
786 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
787 "restore\t$$ra, $$s0, $$s1, $frame_size", [], IILoad >, MayLoad {
788 let isCodeGenOnly = 1;
789 let Defs = [S0, S1, RA, SP];
793 // Use Restore to increment SP since SP is not a Mip 16 register, this
794 // is an easy way to do that which does not require a register.
796 let ra=0, s=0,s0=0,s1=0 in
798 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
799 "restore\t$frame_size", [], IILoad >, MayLoad {
800 let isCodeGenOnly = 1;
806 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
808 // Purpose: Save Registers and Set Up Stack Frame
809 // To set up a stack frame on entry to a subroutine,
810 // saving return address and static registers, and adjusting stack
812 let ra=1, s=1,s0=1,s1=1 in
814 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
815 "save\t$$ra, $$s0, $$s1, $frame_size", [], IIStore >, MayStore {
816 let isCodeGenOnly = 1;
817 let Uses = [RA, SP, S0, S1];
822 // Use Save to decrement the SP by a constant since SP is not
823 // a Mips16 register.
825 let ra=0, s=0,s0=0,s1=0 in
827 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
828 "save\t$frame_size", [], IIStore >, MayStore {
829 let isCodeGenOnly = 1;
834 // Format: SB ry, offset(rx) MIPS16e
835 // Purpose: Store Byte (Extended)
836 // To store a byte to memory.
839 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
842 // The Sel(T) instructions are pseudos
843 // T means that they use T8 implicitly.
846 // Format: SelBeqZ rd, rs, rt
847 // Purpose: if rt==0, do nothing
850 def SelBeqZ: Sel<0b00100, "beqz", IIAlu>;
853 // Format: SelTBteqZCmp rd, rs, rl, rr
854 // Purpose: b = Cmp rl, rr.
855 // If b==0 then do nothing.
856 // if b!=0 then rd = rs
858 def SelTBteqZCmp: SelT<0b000, "bteqz", 0b01010, "cmp", IIAlu>;
861 // Format: SelTBteqZCmpi rd, rs, rl, rr
862 // Purpose: b = Cmpi rl, imm.
863 // If b==0 then do nothing.
864 // if b!=0 then rd = rs
866 def SelTBteqZCmpi: SeliT<0b000, "bteqz", 0b01110, "cmpi", IIAlu>;
869 // Format: SelTBteqZSlt rd, rs, rl, rr
870 // Purpose: b = Slt rl, rr.
871 // If b==0 then do nothing.
872 // if b!=0 then rd = rs
874 def SelTBteqZSlt: SelT<0b000, "bteqz", 0b00010, "slt", IIAlu>;
877 // Format: SelTBteqZSlti rd, rs, rl, rr
878 // Purpose: b = Slti rl, imm.
879 // If b==0 then do nothing.
880 // if b!=0 then rd = rs
882 def SelTBteqZSlti: SeliT<0b000, "bteqz", 0b01010, "slti", IIAlu>;
885 // Format: SelTBteqZSltu rd, rs, rl, rr
886 // Purpose: b = Sltu rl, rr.
887 // If b==0 then do nothing.
888 // if b!=0 then rd = rs
890 def SelTBteqZSltu: SelT<0b000, "bteqz", 0b00011, "sltu", IIAlu>;
893 // Format: SelTBteqZSltiu rd, rs, rl, rr
894 // Purpose: b = Sltiu rl, imm.
895 // If b==0 then do nothing.
896 // if b!=0 then rd = rs
898 def SelTBteqZSltiu: SeliT<0b000, "bteqz", 0b01011, "sltiu", IIAlu>;
901 // Format: SelBnez rd, rs, rt
902 // Purpose: if rt!=0, do nothing
905 def SelBneZ: Sel<0b00101, "bnez", IIAlu>;
908 // Format: SelTBtneZCmp rd, rs, rl, rr
909 // Purpose: b = Cmp rl, rr.
910 // If b!=0 then do nothing.
911 // if b0=0 then rd = rs
913 def SelTBtneZCmp: SelT<0b001, "btnez", 0b01010, "cmp", IIAlu>;
916 // Format: SelTBtnezCmpi rd, rs, rl, rr
917 // Purpose: b = Cmpi rl, imm.
918 // If b!=0 then do nothing.
919 // if b==0 then rd = rs
921 def SelTBtneZCmpi: SeliT<0b000, "btnez", 0b01110, "cmpi", IIAlu>;
924 // Format: SelTBtneZSlt rd, rs, rl, rr
925 // Purpose: b = Slt rl, rr.
926 // If b!=0 then do nothing.
927 // if b==0 then rd = rs
929 def SelTBtneZSlt: SelT<0b001, "btnez", 0b00010, "slt", IIAlu>;
932 // Format: SelTBtneZSlti rd, rs, rl, rr
933 // Purpose: b = Slti rl, imm.
934 // If b!=0 then do nothing.
935 // if b==0 then rd = rs
937 def SelTBtneZSlti: SeliT<0b001, "btnez", 0b01010, "slti", IIAlu>;
940 // Format: SelTBtneZSltu rd, rs, rl, rr
941 // Purpose: b = Sltu rl, rr.
942 // If b!=0 then do nothing.
943 // if b==0 then rd = rs
945 def SelTBtneZSltu: SelT<0b001, "btnez", 0b00011, "sltu", IIAlu>;
948 // Format: SelTBtneZSltiu rd, rs, rl, rr
949 // Purpose: b = Slti rl, imm.
950 // If b!=0 then do nothing.
951 // if b==0 then rd = rs
953 def SelTBtneZSltiu: SeliT<0b001, "btnez", 0b01011, "sltiu", IIAlu>;
956 // Format: SH ry, offset(rx) MIPS16e
957 // Purpose: Store Halfword (Extended)
958 // To store a halfword to memory.
961 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore;
964 // Format: SLL rx, ry, sa MIPS16e
965 // Purpose: Shift Word Left Logical (Extended)
966 // To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
968 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
971 // Format: SLLV ry, rx MIPS16e
972 // Purpose: Shift Word Left Logical Variable
973 // To execute a left-shift of a word by a variable number of bits.
975 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
978 // Format: SLTI rx, immediate MIPS16e
979 // Purpose: Set on Less Than Immediate (Extended)
980 // To record the result of a less-than comparison with a constant.
982 def SltiCCRxImmX16: FEXT_CCRXI16_ins<0b01010, "slti", IIAlu>;
985 // Format: SLTIU rx, immediate MIPS16e
986 // Purpose: Set on Less Than Immediate Unsigned (Extended)
987 // To record the result of a less-than comparison with a constant.
989 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<0b01011, "sltiu", IIAlu>;
992 // Format: SLT rx, ry MIPS16e
993 // Purpose: Set on Less Than
994 // To record the result of a less-than comparison.
996 def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>;
998 def SltCCRxRy16: FCCRR16_ins<0b00010, "slt", IIAlu>;
1000 // Format: SLTU rx, ry MIPS16e
1001 // Purpose: Set on Less Than Unsigned
1002 // To record the result of an unsigned less-than comparison.
1004 def SltuRxRyRz16: FRRTR16_ins<0b00011, "sltu", IIAlu> {
1005 let isCodeGenOnly=1;
1009 def SltuCCRxRy16: FCCRR16_ins<0b00011, "sltu", IIAlu>;
1011 // Format: SRAV ry, rx MIPS16e
1012 // Purpose: Shift Word Right Arithmetic Variable
1013 // To execute an arithmetic right-shift of a word by a variable
1016 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
1020 // Format: SRA rx, ry, sa MIPS16e
1021 // Purpose: Shift Word Right Arithmetic (Extended)
1022 // To execute an arithmetic right-shift of a word by a fixed
1023 // number of bits—1 to 8 bits.
1025 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
1029 // Format: SRLV ry, rx MIPS16e
1030 // Purpose: Shift Word Right Logical Variable
1031 // To execute a logical right-shift of a word by a variable
1034 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
1038 // Format: SRL rx, ry, sa MIPS16e
1039 // Purpose: Shift Word Right Logical (Extended)
1040 // To execute a logical right-shift of a word by a fixed
1041 // number of bits—1 to 31 bits.
1043 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
1046 // Format: SUBU rz, rx, ry MIPS16e
1047 // Purpose: Subtract Unsigned Word
1048 // To subtract 32-bit integers
1050 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
1053 // Format: SW ry, offset(rx) MIPS16e
1054 // Purpose: Store Word (Extended)
1055 // To store a word to memory.
1057 def SwRxRyOffMemX16:
1058 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore;
1061 // Format: SW rx, offset(sp) MIPS16e
1062 // Purpose: Store Word rx (SP-Relative)
1063 // To store an SP-relative word to memory.
1065 def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore;
1069 // Format: XOR rx, ry MIPS16e
1071 // To do a bitwise logical XOR.
1073 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
1075 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
1076 let Predicates = [InMips16Mode];
1079 // Unary Arith/Logic
1081 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1082 Mips16Pat<(OpNode CPU16Regs:$r),
1085 def: ArithLogicU_pat<not, NotRxRy16>;
1086 def: ArithLogicU_pat<ineg, NegRxRy16>;
1088 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1089 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1090 (I CPU16Regs:$l, CPU16Regs:$r)>;
1092 def: ArithLogic16_pat<add, AdduRxRyRz16>;
1093 def: ArithLogic16_pat<and, AndRxRxRy16>;
1094 def: ArithLogic16_pat<mul, MultRxRyRz16>;
1095 def: ArithLogic16_pat<or, OrRxRxRy16>;
1096 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
1097 def: ArithLogic16_pat<xor, XorRxRxRy16>;
1099 // Arithmetic and logical instructions with 2 register operands.
1101 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1102 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1103 (I CPU16Regs:$in, imm_type:$imm)>;
1105 def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>;
1106 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
1107 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
1108 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
1109 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
1111 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1112 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1113 (I CPU16Regs:$r, CPU16Regs:$ra)>;
1115 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
1116 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
1117 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
1119 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1120 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
1122 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
1123 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
1124 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
1125 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
1126 def: LoadM16_pat<load, LwRxRyOffMemX16>;
1128 class StoreM16_pat<PatFrag OpNode, Instruction I> :
1129 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr),
1130 (I CPU16Regs:$r, addr16:$addr)>;
1132 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
1133 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
1134 def: StoreM16_pat<store, SwRxRyOffMemX16>;
1136 // Unconditional branch
1137 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
1138 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1139 let Predicates = [InMips16Mode];
1142 def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1143 (Jal16 tglobaladdr:$dst)>;
1145 def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)),
1146 (Jal16 texternalsym:$dst)>;
1150 (brind CPU16Regs:$rs),
1151 (JrcRx16 CPU16Regs:$rs)>;
1153 // Jump and Link (Call)
1154 let isCall=1, hasDelaySlot=0 in
1156 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
1157 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
1160 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
1161 hasExtraSrcRegAllocReq = 1 in
1162 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
1167 class SetCC_R16<PatFrag cond_op, Instruction I>:
1168 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1169 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1171 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1172 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1173 (I CPU16Regs:$rx, imm_type:$imm16)>;
1176 def: Mips16Pat<(i32 addr16:$addr),
1177 (AddiuRxRyOffMemX16 addr16:$addr)>;
1180 // Large (>16 bit) immediate loads
1181 def : Mips16Pat<(i32 imm:$imm),
1182 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16),
1183 (LiRxImmX16 (LO16 imm:$imm)))>;
1185 // Carry MipsPatterns
1186 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
1187 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1188 def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
1189 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1190 def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
1191 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
1194 // Some branch conditional patterns are not generated by llvm at this time.
1195 // Some are for seemingly arbitrary reasons not used: i.e. with signed number
1196 // comparison they are used and for unsigned a different pattern is used.
1197 // I am pushing upstream from the full mips16 port and it seemed that I needed
1198 // these earlier and the mips32 port has these but now I cannot create test
1199 // cases that use these patterns. While I sort this all out I will leave these
1200 // extra patterns commented out and if I can be sure they are really not used,
1201 // I will delete the code. I don't want to check the code in uncommented without
1202 // a valid test case. In some cases, the compiler is generating patterns with
1203 // setcc instead and earlier I had implemented setcc first so may have masked
1204 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
1205 // figure out how to enable the brcond patterns or else possibly new
1206 // combinations of of brcond and setcc.
1212 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1213 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1218 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1219 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1223 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1224 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16)
1228 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1231 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1232 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1239 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1240 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1244 // never called because compiler transforms a >= k to a > (k-1)
1246 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1247 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1254 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1255 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1259 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1260 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1267 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1268 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1275 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1276 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1280 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1281 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1285 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1286 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1290 // This needs to be there but I forget which code will generate it
1293 <(brcond CPU16Regs:$rx, bb:$targ16),
1294 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1303 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1304 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1311 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1312 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1320 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1321 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1324 def: UncondBranch16_pat<br, BimmX16>;
1327 def: Mips16Pat<(i32 immSExt16:$in),
1328 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
1330 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
1336 <(MipsDivRem CPU16Regs:$rx, CPU16Regs:$ry),
1337 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1343 <(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry),
1344 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1349 // if !(a < b) x = y
1351 def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1352 CPU16Regs:$x, CPU16Regs:$y),
1353 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1354 CPU16Regs:$a, CPU16Regs:$b)>;
1361 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1362 CPU16Regs:$x, CPU16Regs:$y),
1363 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
1364 CPU16Regs:$b, CPU16Regs:$a)>;
1369 // if !(a < b) x = y;
1372 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
1373 CPU16Regs:$x, CPU16Regs:$y),
1374 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1375 CPU16Regs:$a, CPU16Regs:$b)>;
1382 def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
1383 CPU16Regs:$x, CPU16Regs:$y),
1384 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
1385 CPU16Regs:$b, CPU16Regs:$a)>;
1389 // due to an llvm optimization, i don't think that this will ever
1390 // be used. This is transformed into x = (a > k-1)?x:y
1395 // (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1396 // CPU16Regs:$T, CPU16Regs:$F),
1397 // (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
1398 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1401 // (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
1402 // CPU16Regs:$T, CPU16Regs:$F),
1403 // (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
1404 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1409 // if !(a < k) x = y;
1412 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1413 CPU16Regs:$x, CPU16Regs:$y),
1414 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
1415 CPU16Regs:$a, immSExt16:$b)>;
1421 // x = (a <= b)? x : y
1425 def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
1426 CPU16Regs:$x, CPU16Regs:$y),
1427 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1428 CPU16Regs:$b, CPU16Regs:$a)>;
1432 // x = (a <= b)? x : y
1436 def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
1437 CPU16Regs:$x, CPU16Regs:$y),
1438 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1439 CPU16Regs:$b, CPU16Regs:$a)>;
1443 // x = (a == b)? x : y
1445 // if (a != b) x = y
1447 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
1448 CPU16Regs:$x, CPU16Regs:$y),
1449 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
1450 CPU16Regs:$b, CPU16Regs:$a)>;
1454 // x = (a == 0)? x : y
1456 // if (a != 0) x = y
1458 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
1459 CPU16Regs:$x, CPU16Regs:$y),
1460 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
1466 // x = (a == k)? x : y
1468 // if (a != k) x = y
1470 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
1471 CPU16Regs:$x, CPU16Regs:$y),
1472 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
1473 CPU16Regs:$a, immZExt16:$k)>;
1478 // x = (a != b)? x : y
1480 // if (a == b) x = y
1483 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1484 CPU16Regs:$x, CPU16Regs:$y),
1485 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
1486 CPU16Regs:$b, CPU16Regs:$a)>;
1490 // x = (a != 0)? x : y
1492 // if (a == 0) x = y
1494 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1495 CPU16Regs:$x, CPU16Regs:$y),
1496 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1504 def : Mips16Pat<(select CPU16Regs:$a,
1505 CPU16Regs:$x, CPU16Regs:$y),
1506 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1512 // x = (a != k)? x : y
1514 // if (a == k) x = y
1516 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1517 CPU16Regs:$x, CPU16Regs:$y),
1518 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
1519 CPU16Regs:$a, immZExt16:$k)>;
1522 // When writing C code to test setxx these patterns,
1523 // some will be transformed into
1524 // other things. So we test using C code but using -O3 and -O0
1529 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
1530 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
1533 <(seteq CPU16Regs:$lhs, 0),
1534 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
1542 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1543 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1547 // For constants, llvm transforms this to:
1548 // x > (k -1) and then reverses the operands to use setlt. So this pattern
1549 // is not used now by the compiler. (Presumably checking that k-1 does not
1550 // overflow). The compiler never uses this at a the current time, due to
1551 // other optimizations.
1554 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
1555 // (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
1556 // (LiRxImmX16 1))>;
1558 // This catches the x >= -32768 case by transforming it to x > -32769
1561 <(setgt CPU16Regs:$lhs, -32769),
1562 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
1571 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
1572 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1578 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
1579 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1584 def: SetCC_R16<setlt, SltCCRxRy16>;
1586 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
1592 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
1593 (SltuCCRxRy16 (LiRxImmX16 0),
1594 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1601 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1602 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1605 // this pattern will never be used because the compiler will transform
1606 // x >= k to x > (k - 1) and then use SLT
1609 // <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1610 // (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1611 // (LiRxImmX16 1))>;
1617 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1618 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1624 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1625 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1630 def: SetCC_R16<setult, SltuCCRxRy16>;
1632 def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1634 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1635 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
1639 def : Mips16Pat<(MipsHi tglobaladdr:$in),
1640 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>;
1641 def : Mips16Pat<(MipsHi tjumptable:$in),
1642 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>;
1643 def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
1644 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
1647 class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1648 Mips16Pat<(MipsWrapper RC:$gp, node:$in),
1649 (ADDiuOp RC:$gp, node:$in)>;
1652 def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>;
1653 def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
1655 def : Mips16Pat<(i32 (extloadi8 addr16:$src)),
1656 (LbuRxRyOffMemX16 addr16:$src)>;
1657 def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
1658 (LhuRxRyOffMemX16 addr16:$src)>;