1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
18 ComplexPattern<iPTR, 3, "selectAddr16", [frameindex], [SDNPWantParent]>;
22 def mem16 : Operand<i32> {
23 let PrintMethod = "printMemOperand";
24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16Regs);
25 let EncoderMethod = "getMemEncoding";
28 def mem16_ea : Operand<i32> {
29 let PrintMethod = "printMemOperandEA";
30 let MIOperandInfo = (ops CPU16Regs, simm16);
31 let EncoderMethod = "getMemEncoding";
36 // I8 instruction format
39 class FI816_ins_base<bits<3> _func, string asmstr,
40 string asmstr2, InstrItinClass itin>:
41 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
45 class FI816_SP_ins<bits<3> _func, string asmstr,
47 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
50 // RI instruction format
54 class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
56 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
57 !strconcat(asmstr, asmstr2), [], itin>;
59 class FRI16_ins<bits<5> op, string asmstr,
61 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
63 class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2,
65 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
66 !strconcat(asmstr, asmstr2), [], itin>;
68 class FRI16R_ins<bits<5> op, string asmstr,
70 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
72 class F2RI16_ins<bits<5> _op, string asmstr,
74 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
75 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
76 let Constraints = "$rx_ = $rx";
79 class FRI16_B_ins<bits<5> _op, string asmstr,
81 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
82 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>;
84 // Compare a register and immediate and place result in CC
87 // EXT-CCRR Instruction format
89 class FEXT_CCRXI16_ins<string asmstr>:
90 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
91 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
93 let usesCustomInserter = 1;
96 // JAL and JALX instruction format
98 class FJAL16_ins<bits<1> _X, string asmstr,
100 FJAL16<_X, (outs), (ins simm20:$imm),
101 !strconcat(asmstr, "\t$imm\n\tnop"),[],
106 // EXT-I instruction format
108 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
109 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
110 !strconcat(asmstr, "\t$imm16"),[], itin>;
113 // EXT-I8 instruction format
116 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
117 string asmstr2, InstrItinClass itin>:
118 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
121 class FEXT_I816_ins<bits<3> _func, string asmstr,
122 InstrItinClass itin>:
123 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
125 class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
126 InstrItinClass itin>:
127 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>;
130 // Assembler formats in alphabetical order.
131 // Natural and pseudos are mixed together.
133 // Compare two registers and place result in CC
134 // Implicit use of T8
136 // CC-RR Instruction format
138 class FCCRR16_ins<string asmstr> :
139 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
140 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
142 let usesCustomInserter = 1;
146 // EXT-RI instruction format
149 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
150 InstrItinClass itin>:
151 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
152 !strconcat(asmstr, asmstr2), [], itin>;
154 class FEXT_RI16_ins<bits<5> _op, string asmstr,
155 InstrItinClass itin>:
156 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
158 class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2,
159 InstrItinClass itin>:
160 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm),
161 !strconcat(asmstr, asmstr2), [], itin>;
163 class FEXT_RI16R_ins<bits<5> _op, string asmstr,
164 InstrItinClass itin>:
165 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
167 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
168 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
170 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
171 InstrItinClass itin>:
172 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
173 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
175 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
176 InstrItinClass itin>:
177 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
178 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
179 let Constraints = "$rx_ = $rx";
183 // this has an explicit sp argument that we ignore to work around a problem
185 class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
186 InstrItinClass itin>:
187 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
188 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
191 // EXT-RRI instruction format
194 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
195 InstrItinClass itin>:
196 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
197 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
199 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
200 InstrItinClass itin>:
201 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
202 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
206 // EXT-RRI-A instruction format
209 class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
210 InstrItinClass itin>:
211 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
212 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
215 // EXT-SHIFT instruction format
217 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
218 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
219 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
224 class FEXT_T8I816_ins<string asmstr, string asmstr2>:
226 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
227 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
228 !strconcat(asmstr, "\t$imm"))),[]> {
230 let usesCustomInserter = 1;
236 class FEXT_T8I8I16_ins<string asmstr, string asmstr2>:
238 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
239 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
240 !strconcat(asmstr, "\t$targ"))), []> {
242 let usesCustomInserter = 1;
248 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
250 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
251 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32),
252 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
255 // I8_MOV32R instruction format (used only by MOV32R instruction)
258 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
259 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
260 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
263 // This are pseudo formats for multiply
264 // This first one can be changed to non pseudo now.
268 class FMULT16_ins<string asmstr, InstrItinClass itin> :
269 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
270 !strconcat(asmstr, "\t$rx, $ry"), []>;
275 class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
276 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
277 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
282 // RR-type instruction format
285 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
286 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
287 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
290 class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> :
291 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
292 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
295 class FRRTR16_ins<string asmstr> :
296 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
297 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
300 // maybe refactor but need a $zero as a dummy first parameter
302 class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
303 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
304 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
306 class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
307 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
308 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
311 class FRR16_M_ins<bits<5> f, string asmstr,
312 InstrItinClass itin> :
313 FRR16<f, (outs CPU16Regs:$rx), (ins),
314 !strconcat(asmstr, "\t$rx"), [], itin>;
316 class FRxRxRy16_ins<bits<5> f, string asmstr,
317 InstrItinClass itin> :
318 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
319 !strconcat(asmstr, "\t$rz, $ry"),
321 let Constraints = "$rx = $rz";
325 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
326 string asmstr, InstrItinClass itin>:
327 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
331 class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
332 string asmstr, InstrItinClass itin>:
333 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
334 !strconcat(asmstr, "\t $rx"), [], itin> ;
337 // RRR-type instruction format
340 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
341 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
342 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
345 // These Sel patterns support the generation of conditional move
346 // pseudo instructions.
348 // The nomenclature uses the components making up the pseudo and may
349 // be a bit counter intuitive when compared with the end result we seek.
350 // For example using a bqez in the example directly below results in the
351 // conditional move being done if the tested register is not zero.
352 // I considered in easier to check by keeping the pseudo consistent with
353 // it's components but it could have been done differently.
355 // The simplest case is when can test and operand directly and do the
356 // conditional move based on a simple mips16 conditional
357 // branch instruction.
359 // if $op == beqz or bnez:
364 // if $op == beqz, then if $rt != 0, then the conditional assignment
365 // $rd = $rs is done.
367 // if $op == bnez, then if $rt == 0, then the conditional assignment
368 // $rd = $rs is done.
370 // So this pseudo class only has one operand, i.e. op
372 class Sel<string op>:
373 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
375 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> {
376 //let isCodeGenOnly=1;
377 let Constraints = "$rd = $rd_";
378 let usesCustomInserter = 1;
382 // The next two instruction classes allow for an operand which tests
383 // two operands and returns a value in register T8 and
384 //then does a conditional branch based on the value of T8
387 // op2 can be cmpi or slti/sltiu
388 // op1 can bteqz or btnez
389 // the operands for op2 are a register and a signed constant
391 // $op2 $t, $imm ;test register t and branch conditionally
392 // $op1 .+4 ;op1 is a conditional branch
396 class SeliT<string op1, string op2>:
397 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
398 CPU16Regs:$rl, simm16:$imm),
400 !strconcat("\t$rl, $imm\n\t",
401 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
403 let Constraints = "$rd = $rd_";
404 let usesCustomInserter = 1;
408 // op2 can be cmp or slt/sltu
409 // op1 can be bteqz or btnez
410 // the operands for op2 are two registers
411 // op1 is a conditional branch
414 // $op2 $rl, $rr ;test registers rl,rr
415 // $op1 .+4 ;op2 is a conditional branch
419 class SelT<string op1, string op2>:
420 MipsPseudo16<(outs CPU16Regs:$rd_),
421 (ins CPU16Regs:$rd, CPU16Regs:$rs,
422 CPU16Regs:$rl, CPU16Regs:$rr),
424 !strconcat("\t$rl, $rr\n\t",
425 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
427 let Constraints = "$rd = $rd_";
428 let usesCustomInserter = 1;
434 def imm32: Operand<i32>;
437 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
440 MipsPseudo16<(outs), (ins CPU16Regs:$rx, imm32:$imm),
441 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
445 // Some general instruction class info
449 class ArithLogic16Defs<bit isCom=0> {
451 bit isCommutable = isCom;
452 bit isReMaterializable = 1;
453 bit neverHasSideEffects = 1;
458 bit isTerminator = 1;
464 bit isTerminator = 1;
477 // Format: ADDIU rx, immediate MIPS16e
478 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
479 // To add a constant to a 32-bit integer.
481 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
483 def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>,
484 ArithLogic16Defs<0> {
485 let AddedComplexity = 5;
487 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
488 ArithLogic16Defs<0> {
489 let isCodeGenOnly = 1;
492 def AddiuRxRyOffMemX16:
493 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>;
497 // Format: ADDIU rx, pc, immediate MIPS16e
498 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
499 // To add a constant to the program counter.
501 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
504 // Format: ADDIU sp, immediate MIPS16e
505 // Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
506 // To add a constant to the stack pointer.
509 : FI816_SP_ins<0b011, "addiu", IIAlu> {
512 let AddedComplexity = 5;
516 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
522 // Format: ADDU rz, rx, ry MIPS16e
523 // Purpose: Add Unsigned Word (3-Operand)
524 // To add 32-bit integers.
527 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
530 // Format: AND rx, ry MIPS16e
532 // To do a bitwise logical AND.
534 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
538 // Format: BEQZ rx, offset MIPS16e
539 // Purpose: Branch on Equal to Zero
540 // To test a GPR then do a PC-relative conditional branch.
542 def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
546 // Format: BEQZ rx, offset MIPS16e
547 // Purpose: Branch on Equal to Zero (Extended)
548 // To test a GPR then do a PC-relative conditional branch.
550 def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
552 // Format: B offset MIPS16e
553 // Purpose: Unconditional Branch
554 // To do an unconditional PC-relative branch.
556 def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
559 // Format: BNEZ rx, offset MIPS16e
560 // Purpose: Branch on Not Equal to Zero
561 // To test a GPR then do a PC-relative conditional branch.
563 def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
566 // Format: BNEZ rx, offset MIPS16e
567 // Purpose: Branch on Not Equal to Zero (Extended)
568 // To test a GPR then do a PC-relative conditional branch.
570 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
573 // Format: BTEQZ offset MIPS16e
574 // Purpose: Branch on T Equal to Zero (Extended)
575 // To test special register T then do a PC-relative conditional branch.
577 def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
581 def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16;
583 def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">,
586 def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16;
588 def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;
590 def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16;
592 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
596 // Format: BTNEZ offset MIPS16e
597 // Purpose: Branch on T Not Equal to Zero (Extended)
598 // To test special register T then do a PC-relative conditional branch.
600 def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 {
604 def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16;
606 def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16;
608 def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16;
610 def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;
612 def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16;
614 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
618 // Format: CMP rx, ry MIPS16e
620 // To compare the contents of two GPRs.
622 def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> {
627 // Format: CMPI rx, immediate MIPS16e
628 // Purpose: Compare Immediate
629 // To compare a constant with the contents of a GPR.
631 def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> {
636 // Format: CMPI rx, immediate MIPS16e
637 // Purpose: Compare Immediate (Extended)
638 // To compare a constant with the contents of a GPR.
640 def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> {
646 // Format: DIV rx, ry MIPS16e
647 // Purpose: Divide Word
648 // To divide 32-bit signed integers.
650 def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
655 // Format: DIVU rx, ry MIPS16e
656 // Purpose: Divide Unsigned Word
657 // To divide 32-bit unsigned integers.
659 def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
663 // Format: JAL target MIPS16e
664 // Purpose: Jump and Link
665 // To execute a procedure call within the current 256 MB-aligned
666 // region and preserve the current ISA.
669 def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
671 let hasDelaySlot = 0; // not true, but we add the nop for now
677 // Format: JR ra MIPS16e
678 // Purpose: Jump Register Through Register ra
679 // To execute a branch to the instruction address in the return
683 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
685 let isIndirectBranch = 1;
686 let hasDelaySlot = 1;
691 def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> {
693 let isIndirectBranch = 1;
698 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
700 let isIndirectBranch = 1;
705 // Format: LB ry, offset(rx) MIPS16e
706 // Purpose: Load Byte (Extended)
707 // To load a byte from memory as a signed value.
709 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{
710 let isCodeGenOnly = 1;
714 // Format: LBU ry, offset(rx) MIPS16e
715 // Purpose: Load Byte Unsigned (Extended)
716 // To load a byte from memory as a unsigned value.
718 def LbuRxRyOffMemX16:
719 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad {
720 let isCodeGenOnly = 1;
724 // Format: LH ry, offset(rx) MIPS16e
725 // Purpose: Load Halfword signed (Extended)
726 // To load a halfword from memory as a signed value.
728 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{
729 let isCodeGenOnly = 1;
733 // Format: LHU ry, offset(rx) MIPS16e
734 // Purpose: Load Halfword unsigned (Extended)
735 // To load a halfword from memory as an unsigned value.
737 def LhuRxRyOffMemX16:
738 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad {
739 let isCodeGenOnly = 1;
743 // Format: LI rx, immediate MIPS16e
744 // Purpose: Load Immediate
745 // To load a constant into a GPR.
747 def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>;
750 // Format: LI rx, immediate MIPS16e
751 // Purpose: Load Immediate (Extended)
752 // To load a constant into a GPR.
754 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
757 // Format: LW ry, offset(rx) MIPS16e
758 // Purpose: Load Word (Extended)
759 // To load a word from memory as a signed value.
761 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{
762 let isCodeGenOnly = 1;
765 // Format: LW rx, offset(sp) MIPS16e
766 // Purpose: Load Word (SP-Relative, Extended)
767 // To load an SP-relative word from memory as a signed value.
769 def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{
774 // Format: MOVE r32, rz MIPS16e
776 // To move the contents of a GPR to a GPR.
778 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
781 // Format: MOVE ry, r32 MIPS16e
783 // To move the contents of a GPR to a GPR.
785 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
788 // Format: MFHI rx MIPS16e
789 // Purpose: Move From HI Register
790 // To copy the special purpose HI register to a GPR.
792 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
794 let neverHasSideEffects = 1;
798 // Format: MFLO rx MIPS16e
799 // Purpose: Move From LO Register
800 // To copy the special purpose LO register to a GPR.
802 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
804 let neverHasSideEffects = 1;
808 // Pseudo Instruction for mult
810 def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
811 let isCommutable = 1;
812 let neverHasSideEffects = 1;
816 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
817 let isCommutable = 1;
818 let neverHasSideEffects = 1;
823 // Format: MULT rx, ry MIPS16e
824 // Purpose: Multiply Word
825 // To multiply 32-bit signed integers.
827 def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
828 let isCommutable = 1;
829 let neverHasSideEffects = 1;
834 // Format: MULTU rx, ry MIPS16e
835 // Purpose: Multiply Unsigned Word
836 // To multiply 32-bit unsigned integers.
838 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
839 let isCommutable = 1;
840 let neverHasSideEffects = 1;
845 // Format: NEG rx, ry MIPS16e
847 // To negate an integer value.
849 def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
852 // Format: NOT rx, ry MIPS16e
854 // To complement an integer value
856 def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
859 // Format: OR rx, ry MIPS16e
861 // To do a bitwise logical OR.
863 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
866 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
867 // (All args are optional) MIPS16e
868 // Purpose: Restore Registers and Deallocate Stack Frame
869 // To deallocate a stack frame before exit from a subroutine,
870 // restoring return address and static registers, and adjusting
874 // fixed form for restoring RA and the frame
875 // for direct object emitter, encoding needs to be adjusted for the
878 let ra=1, s=0,s0=1,s1=1 in
880 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
881 "restore\t$$ra, $$s0, $$s1, $frame_size", [], IILoad >, MayLoad {
882 let isCodeGenOnly = 1;
883 let Defs = [S0, S1, RA, SP];
887 // Use Restore to increment SP since SP is not a Mip 16 register, this
888 // is an easy way to do that which does not require a register.
890 let ra=0, s=0,s0=0,s1=0 in
892 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
893 "restore\t$frame_size", [], IILoad >, MayLoad {
894 let isCodeGenOnly = 1;
900 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
902 // Purpose: Save Registers and Set Up Stack Frame
903 // To set up a stack frame on entry to a subroutine,
904 // saving return address and static registers, and adjusting stack
906 let ra=1, s=1,s0=1,s1=1 in
908 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
909 "save\t$$ra, $$s0, $$s1, $frame_size", [], IIStore >, MayStore {
910 let isCodeGenOnly = 1;
911 let Uses = [RA, SP, S0, S1];
916 // Use Save to decrement the SP by a constant since SP is not
917 // a Mips16 register.
919 let ra=0, s=0,s0=0,s1=0 in
921 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
922 "save\t$frame_size", [], IIStore >, MayStore {
923 let isCodeGenOnly = 1;
928 // Format: SB ry, offset(rx) MIPS16e
929 // Purpose: Store Byte (Extended)
930 // To store a byte to memory.
933 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
936 // The Sel(T) instructions are pseudos
937 // T means that they use T8 implicitly.
940 // Format: SelBeqZ rd, rs, rt
941 // Purpose: if rt==0, do nothing
944 def SelBeqZ: Sel<"beqz">;
947 // Format: SelTBteqZCmp rd, rs, rl, rr
948 // Purpose: b = Cmp rl, rr.
949 // If b==0 then do nothing.
950 // if b!=0 then rd = rs
952 def SelTBteqZCmp: SelT<"bteqz", "cmp">;
955 // Format: SelTBteqZCmpi rd, rs, rl, rr
956 // Purpose: b = Cmpi rl, imm.
957 // If b==0 then do nothing.
958 // if b!=0 then rd = rs
960 def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">;
963 // Format: SelTBteqZSlt rd, rs, rl, rr
964 // Purpose: b = Slt rl, rr.
965 // If b==0 then do nothing.
966 // if b!=0 then rd = rs
968 def SelTBteqZSlt: SelT<"bteqz", "slt">;
971 // Format: SelTBteqZSlti rd, rs, rl, rr
972 // Purpose: b = Slti rl, imm.
973 // If b==0 then do nothing.
974 // if b!=0 then rd = rs
976 def SelTBteqZSlti: SeliT<"bteqz", "slti">;
979 // Format: SelTBteqZSltu rd, rs, rl, rr
980 // Purpose: b = Sltu rl, rr.
981 // If b==0 then do nothing.
982 // if b!=0 then rd = rs
984 def SelTBteqZSltu: SelT<"bteqz", "sltu">;
987 // Format: SelTBteqZSltiu rd, rs, rl, rr
988 // Purpose: b = Sltiu rl, imm.
989 // If b==0 then do nothing.
990 // if b!=0 then rd = rs
992 def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">;
995 // Format: SelBnez rd, rs, rt
996 // Purpose: if rt!=0, do nothing
999 def SelBneZ: Sel<"bnez">;
1002 // Format: SelTBtneZCmp rd, rs, rl, rr
1003 // Purpose: b = Cmp rl, rr.
1004 // If b!=0 then do nothing.
1005 // if b0=0 then rd = rs
1007 def SelTBtneZCmp: SelT<"btnez", "cmp">;
1010 // Format: SelTBtnezCmpi rd, rs, rl, rr
1011 // Purpose: b = Cmpi rl, imm.
1012 // If b!=0 then do nothing.
1013 // if b==0 then rd = rs
1015 def SelTBtneZCmpi: SeliT<"btnez", "cmpi">;
1018 // Format: SelTBtneZSlt rd, rs, rl, rr
1019 // Purpose: b = Slt rl, rr.
1020 // If b!=0 then do nothing.
1021 // if b==0 then rd = rs
1023 def SelTBtneZSlt: SelT<"btnez", "slt">;
1026 // Format: SelTBtneZSlti rd, rs, rl, rr
1027 // Purpose: b = Slti rl, imm.
1028 // If b!=0 then do nothing.
1029 // if b==0 then rd = rs
1031 def SelTBtneZSlti: SeliT<"btnez", "slti">;
1034 // Format: SelTBtneZSltu rd, rs, rl, rr
1035 // Purpose: b = Sltu rl, rr.
1036 // If b!=0 then do nothing.
1037 // if b==0 then rd = rs
1039 def SelTBtneZSltu: SelT<"btnez", "sltu">;
1042 // Format: SelTBtneZSltiu rd, rs, rl, rr
1043 // Purpose: b = Slti rl, imm.
1044 // If b!=0 then do nothing.
1045 // if b==0 then rd = rs
1047 def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
1050 // Format: SH ry, offset(rx) MIPS16e
1051 // Purpose: Store Halfword (Extended)
1052 // To store a halfword to memory.
1054 def ShRxRyOffMemX16:
1055 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore;
1058 // Format: SLL rx, ry, sa MIPS16e
1059 // Purpose: Shift Word Left Logical (Extended)
1060 // To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
1062 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
1065 // Format: SLLV ry, rx MIPS16e
1066 // Purpose: Shift Word Left Logical Variable
1067 // To execute a left-shift of a word by a variable number of bits.
1069 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
1071 // Format: SLTI rx, immediate MIPS16e
1072 // Purpose: Set on Less Than Immediate
1073 // To record the result of a less-than comparison with a constant.
1076 def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> {
1081 // Format: SLTI rx, immediate MIPS16e
1082 // Purpose: Set on Less Than Immediate (Extended)
1083 // To record the result of a less-than comparison with a constant.
1086 def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> {
1090 def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
1092 // Format: SLTIU rx, immediate MIPS16e
1093 // Purpose: Set on Less Than Immediate Unsigned
1094 // To record the result of a less-than comparison with a constant.
1097 def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> {
1102 // Format: SLTI rx, immediate MIPS16e
1103 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1104 // To record the result of a less-than comparison with a constant.
1107 def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> {
1111 // Format: SLTIU rx, immediate MIPS16e
1112 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1113 // To record the result of a less-than comparison with a constant.
1115 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
1118 // Format: SLT rx, ry MIPS16e
1119 // Purpose: Set on Less Than
1120 // To record the result of a less-than comparison.
1122 def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{
1126 def SltCCRxRy16: FCCRR16_ins<"slt">;
1128 // Format: SLTU rx, ry MIPS16e
1129 // Purpose: Set on Less Than Unsigned
1130 // To record the result of an unsigned less-than comparison.
1132 def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{
1136 def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
1137 let isCodeGenOnly=1;
1142 def SltuCCRxRy16: FCCRR16_ins<"sltu">;
1144 // Format: SRAV ry, rx MIPS16e
1145 // Purpose: Shift Word Right Arithmetic Variable
1146 // To execute an arithmetic right-shift of a word by a variable
1149 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
1153 // Format: SRA rx, ry, sa MIPS16e
1154 // Purpose: Shift Word Right Arithmetic (Extended)
1155 // To execute an arithmetic right-shift of a word by a fixed
1156 // number of bits—1 to 8 bits.
1158 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
1162 // Format: SRLV ry, rx MIPS16e
1163 // Purpose: Shift Word Right Logical Variable
1164 // To execute a logical right-shift of a word by a variable
1167 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
1171 // Format: SRL rx, ry, sa MIPS16e
1172 // Purpose: Shift Word Right Logical (Extended)
1173 // To execute a logical right-shift of a word by a fixed
1174 // number of bits—1 to 31 bits.
1176 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
1179 // Format: SUBU rz, rx, ry MIPS16e
1180 // Purpose: Subtract Unsigned Word
1181 // To subtract 32-bit integers
1183 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
1186 // Format: SW ry, offset(rx) MIPS16e
1187 // Purpose: Store Word (Extended)
1188 // To store a word to memory.
1190 def SwRxRyOffMemX16:
1191 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore;
1194 // Format: SW rx, offset(sp) MIPS16e
1195 // Purpose: Store Word rx (SP-Relative)
1196 // To store an SP-relative word to memory.
1198 def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore;
1202 // Format: XOR rx, ry MIPS16e
1204 // To do a bitwise logical XOR.
1206 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
1208 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
1209 let Predicates = [InMips16Mode];
1212 // Unary Arith/Logic
1214 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1215 Mips16Pat<(OpNode CPU16Regs:$r),
1218 def: ArithLogicU_pat<not, NotRxRy16>;
1219 def: ArithLogicU_pat<ineg, NegRxRy16>;
1221 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1222 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1223 (I CPU16Regs:$l, CPU16Regs:$r)>;
1225 def: ArithLogic16_pat<add, AdduRxRyRz16>;
1226 def: ArithLogic16_pat<and, AndRxRxRy16>;
1227 def: ArithLogic16_pat<mul, MultRxRyRz16>;
1228 def: ArithLogic16_pat<or, OrRxRxRy16>;
1229 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
1230 def: ArithLogic16_pat<xor, XorRxRxRy16>;
1232 // Arithmetic and logical instructions with 2 register operands.
1234 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1235 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1236 (I CPU16Regs:$in, imm_type:$imm)>;
1238 def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>;
1239 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
1240 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
1241 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
1242 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
1244 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1245 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1246 (I CPU16Regs:$r, CPU16Regs:$ra)>;
1248 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
1249 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
1250 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
1252 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1253 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
1255 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
1256 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
1257 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
1258 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
1259 def: LoadM16_pat<load, LwRxRyOffMemX16>;
1261 class StoreM16_pat<PatFrag OpNode, Instruction I> :
1262 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr),
1263 (I CPU16Regs:$r, addr16:$addr)>;
1265 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
1266 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
1267 def: StoreM16_pat<store, SwRxRyOffMemX16>;
1269 // Unconditional branch
1270 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
1271 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1272 let Predicates = [InMips16Mode];
1275 def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1276 (Jal16 tglobaladdr:$dst)>;
1278 def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)),
1279 (Jal16 texternalsym:$dst)>;
1283 (brind CPU16Regs:$rs),
1284 (JrcRx16 CPU16Regs:$rs)>;
1286 // Jump and Link (Call)
1287 let isCall=1, hasDelaySlot=0 in
1289 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
1290 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
1293 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
1294 hasExtraSrcRegAllocReq = 1 in
1295 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
1300 class SetCC_R16<PatFrag cond_op, Instruction I>:
1301 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1302 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1304 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1305 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1306 (I CPU16Regs:$rx, imm_type:$imm16)>;
1309 def: Mips16Pat<(i32 addr16:$addr),
1310 (AddiuRxRyOffMemX16 addr16:$addr)>;
1313 // Large (>16 bit) immediate loads
1314 def : Mips16Pat<(i32 imm:$imm),
1315 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16),
1316 (LiRxImmX16 (LO16 imm:$imm)))>;
1318 // Carry MipsPatterns
1319 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
1320 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1321 def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
1322 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1323 def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
1324 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
1327 // Some branch conditional patterns are not generated by llvm at this time.
1328 // Some are for seemingly arbitrary reasons not used: i.e. with signed number
1329 // comparison they are used and for unsigned a different pattern is used.
1330 // I am pushing upstream from the full mips16 port and it seemed that I needed
1331 // these earlier and the mips32 port has these but now I cannot create test
1332 // cases that use these patterns. While I sort this all out I will leave these
1333 // extra patterns commented out and if I can be sure they are really not used,
1334 // I will delete the code. I don't want to check the code in uncommented without
1335 // a valid test case. In some cases, the compiler is generating patterns with
1336 // setcc instead and earlier I had implemented setcc first so may have masked
1337 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
1338 // figure out how to enable the brcond patterns or else possibly new
1339 // combinations of of brcond and setcc.
1345 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1346 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1351 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1352 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1356 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1357 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16)
1361 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1364 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1365 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1372 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1373 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1377 // never called because compiler transforms a >= k to a > (k-1)
1379 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1380 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1387 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1388 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1392 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1393 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1400 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1401 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1408 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1409 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1413 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1414 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1418 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1419 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1423 // This needs to be there but I forget which code will generate it
1426 <(brcond CPU16Regs:$rx, bb:$targ16),
1427 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1436 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1437 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1444 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1445 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1453 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1454 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1457 def: UncondBranch16_pat<br, BimmX16>;
1460 def: Mips16Pat<(i32 immSExt16:$in),
1461 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
1463 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
1469 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry),
1470 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1476 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry),
1477 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1482 // if !(a < b) x = y
1484 def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1485 CPU16Regs:$x, CPU16Regs:$y),
1486 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1487 CPU16Regs:$a, CPU16Regs:$b)>;
1494 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1495 CPU16Regs:$x, CPU16Regs:$y),
1496 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
1497 CPU16Regs:$b, CPU16Regs:$a)>;
1502 // if !(a < b) x = y;
1505 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
1506 CPU16Regs:$x, CPU16Regs:$y),
1507 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1508 CPU16Regs:$a, CPU16Regs:$b)>;
1515 def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
1516 CPU16Regs:$x, CPU16Regs:$y),
1517 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
1518 CPU16Regs:$b, CPU16Regs:$a)>;
1522 // due to an llvm optimization, i don't think that this will ever
1523 // be used. This is transformed into x = (a > k-1)?x:y
1528 // (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1529 // CPU16Regs:$T, CPU16Regs:$F),
1530 // (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
1531 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1534 // (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
1535 // CPU16Regs:$T, CPU16Regs:$F),
1536 // (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
1537 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1542 // if !(a < k) x = y;
1545 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1546 CPU16Regs:$x, CPU16Regs:$y),
1547 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
1548 CPU16Regs:$a, immSExt16:$b)>;
1554 // x = (a <= b)? x : y
1558 def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
1559 CPU16Regs:$x, CPU16Regs:$y),
1560 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1561 CPU16Regs:$b, CPU16Regs:$a)>;
1565 // x = (a <= b)? x : y
1569 def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
1570 CPU16Regs:$x, CPU16Regs:$y),
1571 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1572 CPU16Regs:$b, CPU16Regs:$a)>;
1576 // x = (a == b)? x : y
1578 // if (a != b) x = y
1580 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
1581 CPU16Regs:$x, CPU16Regs:$y),
1582 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
1583 CPU16Regs:$b, CPU16Regs:$a)>;
1587 // x = (a == 0)? x : y
1589 // if (a != 0) x = y
1591 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
1592 CPU16Regs:$x, CPU16Regs:$y),
1593 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
1599 // x = (a == k)? x : y
1601 // if (a != k) x = y
1603 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
1604 CPU16Regs:$x, CPU16Regs:$y),
1605 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
1606 CPU16Regs:$a, immZExt16:$k)>;
1611 // x = (a != b)? x : y
1613 // if (a == b) x = y
1616 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1617 CPU16Regs:$x, CPU16Regs:$y),
1618 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
1619 CPU16Regs:$b, CPU16Regs:$a)>;
1623 // x = (a != 0)? x : y
1625 // if (a == 0) x = y
1627 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1628 CPU16Regs:$x, CPU16Regs:$y),
1629 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1637 def : Mips16Pat<(select CPU16Regs:$a,
1638 CPU16Regs:$x, CPU16Regs:$y),
1639 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1645 // x = (a != k)? x : y
1647 // if (a == k) x = y
1649 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1650 CPU16Regs:$x, CPU16Regs:$y),
1651 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
1652 CPU16Regs:$a, immZExt16:$k)>;
1655 // When writing C code to test setxx these patterns,
1656 // some will be transformed into
1657 // other things. So we test using C code but using -O3 and -O0
1662 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
1663 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
1666 <(seteq CPU16Regs:$lhs, 0),
1667 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
1675 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1676 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1680 // For constants, llvm transforms this to:
1681 // x > (k -1) and then reverses the operands to use setlt. So this pattern
1682 // is not used now by the compiler. (Presumably checking that k-1 does not
1683 // overflow). The compiler never uses this at a the current time, due to
1684 // other optimizations.
1687 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
1688 // (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
1689 // (LiRxImmX16 1))>;
1691 // This catches the x >= -32768 case by transforming it to x > -32769
1694 <(setgt CPU16Regs:$lhs, -32769),
1695 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
1704 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
1705 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1711 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
1712 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>;
1717 def: SetCC_R16<setlt, SltCCRxRy16>;
1719 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
1725 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
1726 (SltuCCRxRy16 (LiRxImmX16 0),
1727 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1734 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1735 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1738 // this pattern will never be used because the compiler will transform
1739 // x >= k to x > (k - 1) and then use SLT
1742 // <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1743 // (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1744 // (LiRxImmX16 1))>;
1750 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1751 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1757 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1758 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1763 def: SetCC_R16<setult, SltuCCRxRy16>;
1765 def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1767 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1768 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
1772 def : Mips16Pat<(MipsHi tglobaladdr:$in),
1773 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>;
1774 def : Mips16Pat<(MipsHi tjumptable:$in),
1775 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>;
1776 def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
1777 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
1780 class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1781 Mips16Pat<(MipsWrapper RC:$gp, node:$in),
1782 (ADDiuOp RC:$gp, node:$in)>;
1785 def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>;
1786 def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
1788 def : Mips16Pat<(i32 (extloadi8 addr16:$src)),
1789 (LbuRxRyOffMemX16 addr16:$src)>;
1790 def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
1791 (LhuRxRyOffMemX16 addr16:$src)>;