1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
15 // RRR-type instruction format
18 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
19 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
20 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
23 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
25 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
26 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32),
27 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
30 // I8_MOV32R instruction format (used only by MOV32R instruction)
32 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
33 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
34 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
37 // EXT-RI instruction format
40 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
42 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
43 !strconcat(asmstr, asmstr2), [], itin>;
45 class FEXT_RI16_ins<bits<5> _op, string asmstr,
47 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
49 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
50 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
53 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
55 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
56 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
57 let Constraints = "$rx_ = $rx";
62 // RR-type instruction format
65 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
66 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
67 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
70 class FRxRxRy16_ins<bits<5> f, string asmstr,
71 InstrItinClass itin> :
72 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
73 !strconcat(asmstr, "\t$rz, $ry"),
75 let Constraints = "$rx = $rz";
79 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
80 string asmstr, InstrItinClass itin>:
81 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
85 // EXT-RRI instruction format
88 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
90 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
91 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
93 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
95 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
96 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
99 // EXT-SHIFT instruction format
101 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
102 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
103 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
107 def mem16 : Operand<i32> {
108 let PrintMethod = "printMemOperand";
109 let MIOperandInfo = (ops CPU16Regs, simm16);
110 let EncoderMethod = "getMemEncoding";
114 // Some general instruction class info
118 class ArithLogic16Defs<bit isCom=0> {
120 bit isCommutable = isCom;
121 bit isReMaterializable = 1;
122 bit neverHasSideEffects = 1;
127 // Format: ADDIU rx, immediate MIPS16e
128 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
129 // To add a constant to a 32-bit integer.
131 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
133 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
138 // Format: ADDIU rx, pc, immediate MIPS16e
139 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
140 // To add a constant to the program counter.
142 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
144 // Format: ADDU rz, rx, ry MIPS16e
145 // Purpose: Add Unsigned Word (3-Operand)
146 // To add 32-bit integers.
149 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
152 // Format: AND rx, ry MIPS16e
154 // To do a bitwise logical AND.
156 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
159 // Format: JR ra MIPS16e
160 // Purpose: Jump Register Through Register ra
161 // To execute a branch to the instruction address in the return
165 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu>;
168 // Format: LB ry, offset(rx) MIPS16e
169 // Purpose: Load Byte (Extended)
170 // To load a byte from memory as a signed value.
172 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IIAlu>;
175 // Format: LBU ry, offset(rx) MIPS16e
176 // Purpose: Load Byte Unsigned (Extended)
177 // To load a byte from memory as a unsigned value.
179 def LbuRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IIAlu>;
182 // Format: LH ry, offset(rx) MIPS16e
183 // Purpose: Load Halfword signed (Extended)
184 // To load a halfword from memory as a signed value.
186 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IIAlu>;
189 // Format: LHU ry, offset(rx) MIPS16e
190 // Purpose: Load Halfword unsigned (Extended)
191 // To load a halfword from memory as an unsigned value.
193 def LhuRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IIAlu>;
196 // Format: LI rx, immediate MIPS16e
197 // Purpose: Load Immediate (Extended)
198 // To load a constant into a GPR.
200 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
203 // Format: LW ry, offset(rx) MIPS16e
204 // Purpose: Load Word (Extended)
205 // To load a word from memory as a signed value.
207 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IIAlu>;
210 // Format: MOVE r32, rz MIPS16e
212 // To move the contents of a GPR to a GPR.
214 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
217 // Format: MOVE ry, r32 MIPS16e
219 // To move the contents of a GPR to a GPR.
221 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
224 // Format: NEG rx, ry MIPS16e
226 // To negate an integer value.
228 def NegRxRy16: FRR16_ins<0b11101, "neg", IIAlu>;
231 // Format: NOT rx, ry MIPS16e
233 // To complement an integer value
235 def NotRxRy16: FRR16_ins<0b01111, "not", IIAlu>;
238 // Format: OR rx, ry MIPS16e
240 // To do a bitwise logical OR.
242 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
245 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
246 // (All args are optional) MIPS16e
247 // Purpose: Restore Registers and Deallocate Stack Frame
248 // To deallocate a stack frame before exit from a subroutine,
249 // restoring return address and static registers, and adjusting
253 // fixed form for restoring RA and the frame
254 // for direct object emitter, encoding needs to be adjusted for the
257 let ra=1, s=0,s0=1,s1=1 in
259 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
260 "restore \t$$ra, $$s0, $$s1, $frame_size", [], IILoad > {
261 let isCodeGenOnly = 1;
265 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
267 // Purpose: Save Registers and Set Up Stack Frame
268 // To set up a stack frame on entry to a subroutine,
269 // saving return address and static registers, and adjusting stack
271 let ra=1, s=1,s0=1,s1=1 in
273 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
274 "save \t$$ra, $$s0, $$s1, $frame_size", [], IILoad > {
275 let isCodeGenOnly = 1;
278 // Format: SB ry, offset(rx) MIPS16e
279 // Purpose: Store Byte (Extended)
280 // To store a byte to memory.
282 def SbRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIAlu>;
285 // Format: SH ry, offset(rx) MIPS16e
286 // Purpose: Store Halfword (Extended)
287 // To store a halfword to memory.
289 def ShRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIAlu>;
292 // Format: SLL rx, ry, sa MIPS16e
293 // Purpose: Shift Word Left Logical (Extended)
294 // To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
296 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
299 // Format: SLLV ry, rx MIPS16e
300 // Purpose: Shift Word Left Logical Variable
301 // To execute a left-shift of a word by a variable number of bits.
303 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
307 // Format: SRAV ry, rx MIPS16e
308 // Purpose: Shift Word Right Arithmetic Variable
309 // To execute an arithmetic right-shift of a word by a variable
312 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
316 // Format: SRA rx, ry, sa MIPS16e
317 // Purpose: Shift Word Right Arithmetic (Extended)
318 // To execute an arithmetic right-shift of a word by a fixed
319 // number of bits—1 to 8 bits.
321 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
325 // Format: SRLV ry, rx MIPS16e
326 // Purpose: Shift Word Right Logical Variable
327 // To execute a logical right-shift of a word by a variable
330 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
334 // Format: SRL rx, ry, sa MIPS16e
335 // Purpose: Shift Word Right Logical (Extended)
336 // To execute a logical right-shift of a word by a fixed
337 // number of bits—1 to 31 bits.
339 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
342 // Format: SUBU rz, rx, ry MIPS16e
343 // Purpose: Subtract Unsigned Word
344 // To subtract 32-bit integers
346 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
349 // Format: SW ry, offset(rx) MIPS16e
350 // Purpose: Store Word (Extended)
351 // To store a word to memory.
353 def SwRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIAlu>;
356 // Format: XOR rx, ry MIPS16e
358 // To do a bitwise logical XOR.
360 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
362 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
363 let Predicates = [InMips16Mode];
368 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
369 Mips16Pat<(OpNode CPU16Regs:$r),
372 def: ArithLogicU_pat<not, NotRxRy16>;
373 def: ArithLogicU_pat<ineg, NegRxRy16>;
375 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
376 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
377 (I CPU16Regs:$l, CPU16Regs:$r)>;
379 def: ArithLogic16_pat<add, AdduRxRyRz16>;
380 def: ArithLogic16_pat<and, AndRxRxRy16>;
381 def: ArithLogic16_pat<or, OrRxRxRy16>;
382 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
383 def: ArithLogic16_pat<xor, XorRxRxRy16>;
385 // Arithmetic and logical instructions with 2 register operands.
387 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
388 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
389 (I CPU16Regs:$in, imm_type:$imm)>;
391 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
392 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
393 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
394 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
396 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
397 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
398 (I CPU16Regs:$r, CPU16Regs:$ra)>;
400 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
401 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
402 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
404 class LoadM16_pat<PatFrag OpNode, Instruction I> :
405 Mips16Pat<(OpNode addr:$addr), (I addr:$addr)>;
407 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
408 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
409 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
410 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
411 def: LoadM16_pat<load, LwRxRyOffMemX16>;
413 class StoreM16_pat<PatFrag OpNode, Instruction I> :
414 Mips16Pat<(OpNode CPU16Regs:$r, addr:$addr), (I CPU16Regs:$r, addr:$addr)>;
416 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
417 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
418 def: StoreM16_pat<store, SwRxRyOffMemX16>;
421 // Jump and Link (Call)
422 let isCall=1, hasDelaySlot=1 in
424 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
425 "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
428 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
429 hasExtraSrcRegAllocReq = 1 in
430 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
433 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
435 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
436 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;