1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
18 ComplexPattern<iPTR, 3, "selectAddr16", [frameindex], [SDNPWantParent]>;
22 def mem16 : Operand<i32> {
23 let PrintMethod = "printMemOperand";
24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16RegsPlusSP);
25 let EncoderMethod = "getMemEncoding";
28 def mem16_ea : Operand<i32> {
29 let PrintMethod = "printMemOperandEA";
30 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
31 let EncoderMethod = "getMemEncoding";
36 // I8 instruction format
39 class FI816_ins_base<bits<3> _func, string asmstr,
40 string asmstr2, InstrItinClass itin>:
41 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
45 class FI816_SP_ins<bits<3> _func, string asmstr,
47 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
50 // RI instruction format
54 class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
56 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
57 !strconcat(asmstr, asmstr2), [], itin>;
59 class FRI16_ins<bits<5> op, string asmstr,
61 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
63 class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2,
65 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
66 !strconcat(asmstr, asmstr2), [], itin>;
68 class FRI16R_ins<bits<5> op, string asmstr,
70 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
72 class F2RI16_ins<bits<5> _op, string asmstr,
74 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
75 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
76 let Constraints = "$rx_ = $rx";
79 class FRI16_B_ins<bits<5> _op, string asmstr,
81 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
82 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>;
84 // Compare a register and immediate and place result in CC
87 // EXT-CCRR Instruction format
89 class FEXT_CCRXI16_ins<string asmstr>:
90 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
91 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
93 let usesCustomInserter = 1;
96 // JAL and JALX instruction format
98 class FJAL16_ins<bits<1> _X, string asmstr,
100 FJAL16<_X, (outs), (ins simm20:$imm),
101 !strconcat(asmstr, "\t$imm\n\tnop"),[],
106 // EXT-I instruction format
108 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
109 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
110 !strconcat(asmstr, "\t$imm16"),[], itin>;
113 // EXT-I8 instruction format
116 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
117 string asmstr2, InstrItinClass itin>:
118 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
121 class FEXT_I816_ins<bits<3> _func, string asmstr,
122 InstrItinClass itin>:
123 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
125 class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
126 InstrItinClass itin>:
127 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>;
130 // Assembler formats in alphabetical order.
131 // Natural and pseudos are mixed together.
133 // Compare two registers and place result in CC
134 // Implicit use of T8
136 // CC-RR Instruction format
138 class FCCRR16_ins<string asmstr> :
139 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
140 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
142 let usesCustomInserter = 1;
146 // EXT-RI instruction format
149 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
150 InstrItinClass itin>:
151 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
152 !strconcat(asmstr, asmstr2), [], itin>;
154 class FEXT_RI16_ins<bits<5> _op, string asmstr,
155 InstrItinClass itin>:
156 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
158 class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2,
159 InstrItinClass itin>:
160 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm),
161 !strconcat(asmstr, asmstr2), [], itin>;
163 class FEXT_RI16R_ins<bits<5> _op, string asmstr,
164 InstrItinClass itin>:
165 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
167 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
168 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
170 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
171 InstrItinClass itin>:
172 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
173 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
175 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
176 InstrItinClass itin>:
177 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
178 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
179 let Constraints = "$rx_ = $rx";
183 // this has an explicit sp argument that we ignore to work around a problem
185 class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
186 InstrItinClass itin>:
187 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
188 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
190 class FEXT_RI16_SP_Store_explicit_ins<bits<5> _op, string asmstr,
191 InstrItinClass itin>:
192 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm),
193 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
196 // EXT-RRI instruction format
199 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
200 InstrItinClass itin>:
201 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
202 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
204 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
205 InstrItinClass itin>:
206 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
207 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
211 // EXT-RRI-A instruction format
214 class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
215 InstrItinClass itin>:
216 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
217 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
220 // EXT-SHIFT instruction format
222 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
223 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa),
224 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
229 class FEXT_T8I816_ins<string asmstr, string asmstr2>:
231 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
232 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
233 !strconcat(asmstr, "\t$imm"))),[]> {
235 let usesCustomInserter = 1;
241 class FEXT_T8I8I16_ins<string asmstr, string asmstr2>:
243 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
244 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
245 !strconcat(asmstr, "\t$targ"))), []> {
247 let usesCustomInserter = 1;
253 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
255 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
256 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32),
257 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
260 // I8_MOV32R instruction format (used only by MOV32R instruction)
263 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
264 FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz),
265 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
268 // This are pseudo formats for multiply
269 // This first one can be changed to non pseudo now.
273 class FMULT16_ins<string asmstr, InstrItinClass itin> :
274 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
275 !strconcat(asmstr, "\t$rx, $ry"), []>;
280 class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
281 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
282 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
287 // RR-type instruction format
290 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
291 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
292 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
295 class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> :
296 FRRBreak16<(outs), (ins), asmstr, [], itin> {
300 class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> :
301 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
302 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
305 class FRRTR16_ins<string asmstr> :
306 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
307 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
310 // maybe refactor but need a $zero as a dummy first parameter
312 class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
313 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
314 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
316 class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
317 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
318 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
321 class FRR16_M_ins<bits<5> f, string asmstr,
322 InstrItinClass itin> :
323 FRR16<f, (outs CPU16Regs:$rx), (ins),
324 !strconcat(asmstr, "\t$rx"), [], itin>;
326 class FRxRxRy16_ins<bits<5> f, string asmstr,
327 InstrItinClass itin> :
328 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
329 !strconcat(asmstr, "\t$rz, $ry"),
331 let Constraints = "$rx = $rz";
335 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
336 string asmstr, InstrItinClass itin>:
337 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
341 class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
342 string asmstr, InstrItinClass itin>:
343 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
344 !strconcat(asmstr, "\t $rx"), [], itin> ;
347 // RRR-type instruction format
350 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
351 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
352 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
355 // These Sel patterns support the generation of conditional move
356 // pseudo instructions.
358 // The nomenclature uses the components making up the pseudo and may
359 // be a bit counter intuitive when compared with the end result we seek.
360 // For example using a bqez in the example directly below results in the
361 // conditional move being done if the tested register is not zero.
362 // I considered in easier to check by keeping the pseudo consistent with
363 // it's components but it could have been done differently.
365 // The simplest case is when can test and operand directly and do the
366 // conditional move based on a simple mips16 conditional
367 // branch instruction.
369 // if $op == beqz or bnez:
374 // if $op == beqz, then if $rt != 0, then the conditional assignment
375 // $rd = $rs is done.
377 // if $op == bnez, then if $rt == 0, then the conditional assignment
378 // $rd = $rs is done.
380 // So this pseudo class only has one operand, i.e. op
382 class Sel<string op>:
383 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
385 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> {
386 //let isCodeGenOnly=1;
387 let Constraints = "$rd = $rd_";
388 let usesCustomInserter = 1;
392 // The next two instruction classes allow for an operand which tests
393 // two operands and returns a value in register T8 and
394 //then does a conditional branch based on the value of T8
397 // op2 can be cmpi or slti/sltiu
398 // op1 can bteqz or btnez
399 // the operands for op2 are a register and a signed constant
401 // $op2 $t, $imm ;test register t and branch conditionally
402 // $op1 .+4 ;op1 is a conditional branch
406 class SeliT<string op1, string op2>:
407 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
408 CPU16Regs:$rl, simm16:$imm),
410 !strconcat("\t$rl, $imm\n\t",
411 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
413 let Constraints = "$rd = $rd_";
414 let usesCustomInserter = 1;
418 // op2 can be cmp or slt/sltu
419 // op1 can be bteqz or btnez
420 // the operands for op2 are two registers
421 // op1 is a conditional branch
424 // $op2 $rl, $rr ;test registers rl,rr
425 // $op1 .+4 ;op2 is a conditional branch
429 class SelT<string op1, string op2>:
430 MipsPseudo16<(outs CPU16Regs:$rd_),
431 (ins CPU16Regs:$rd, CPU16Regs:$rs,
432 CPU16Regs:$rl, CPU16Regs:$rr),
434 !strconcat("\t$rl, $rr\n\t",
435 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
437 let Constraints = "$rd = $rd_";
438 let usesCustomInserter = 1;
444 def imm32: Operand<i32>;
447 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
450 MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm),
451 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
455 // Some general instruction class info
459 class ArithLogic16Defs<bit isCom=0> {
461 bit isCommutable = isCom;
462 bit isReMaterializable = 1;
463 bit neverHasSideEffects = 1;
468 bit isTerminator = 1;
474 bit isTerminator = 1;
487 // Format: ADDIU rx, immediate MIPS16e
488 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
489 // To add a constant to a 32-bit integer.
491 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
493 def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>,
494 ArithLogic16Defs<0> {
495 let AddedComplexity = 5;
497 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
498 ArithLogic16Defs<0> {
499 let isCodeGenOnly = 1;
502 def AddiuRxRyOffMemX16:
503 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>;
507 // Format: ADDIU rx, pc, immediate MIPS16e
508 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
509 // To add a constant to the program counter.
511 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
514 // Format: ADDIU sp, immediate MIPS16e
515 // Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
516 // To add a constant to the stack pointer.
519 : FI816_SP_ins<0b011, "addiu", IIAlu> {
522 let AddedComplexity = 5;
526 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
532 // Format: ADDU rz, rx, ry MIPS16e
533 // Purpose: Add Unsigned Word (3-Operand)
534 // To add 32-bit integers.
537 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
540 // Format: AND rx, ry MIPS16e
542 // To do a bitwise logical AND.
544 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
548 // Format: BEQZ rx, offset MIPS16e
549 // Purpose: Branch on Equal to Zero
550 // To test a GPR then do a PC-relative conditional branch.
552 def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
556 // Format: BEQZ rx, offset MIPS16e
557 // Purpose: Branch on Equal to Zero (Extended)
558 // To test a GPR then do a PC-relative conditional branch.
560 def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
562 // Format: B offset MIPS16e
563 // Purpose: Unconditional Branch
564 // To do an unconditional PC-relative branch.
566 def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
569 // Format: BNEZ rx, offset MIPS16e
570 // Purpose: Branch on Not Equal to Zero
571 // To test a GPR then do a PC-relative conditional branch.
573 def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
576 // Format: BNEZ rx, offset MIPS16e
577 // Purpose: Branch on Not Equal to Zero (Extended)
578 // To test a GPR then do a PC-relative conditional branch.
580 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
584 //Format: BREAK immediate
585 // Purpose: Breakpoint
586 // To cause a Breakpoint exception.
588 def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>;
590 // Format: BTEQZ offset MIPS16e
591 // Purpose: Branch on T Equal to Zero (Extended)
592 // To test special register T then do a PC-relative conditional branch.
594 def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
598 def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16;
600 def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">,
603 def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16;
605 def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;
607 def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16;
609 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
613 // Format: BTNEZ offset MIPS16e
614 // Purpose: Branch on T Not Equal to Zero (Extended)
615 // To test special register T then do a PC-relative conditional branch.
617 def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 {
621 def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16;
623 def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16;
625 def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16;
627 def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;
629 def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16;
631 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
635 // Format: CMP rx, ry MIPS16e
637 // To compare the contents of two GPRs.
639 def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> {
644 // Format: CMPI rx, immediate MIPS16e
645 // Purpose: Compare Immediate
646 // To compare a constant with the contents of a GPR.
648 def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> {
653 // Format: CMPI rx, immediate MIPS16e
654 // Purpose: Compare Immediate (Extended)
655 // To compare a constant with the contents of a GPR.
657 def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> {
663 // Format: DIV rx, ry MIPS16e
664 // Purpose: Divide Word
665 // To divide 32-bit signed integers.
667 def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
668 let Defs = [HI0, LO0];
672 // Format: DIVU rx, ry MIPS16e
673 // Purpose: Divide Unsigned Word
674 // To divide 32-bit unsigned integers.
676 def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
677 let Defs = [HI0, LO0];
680 // Format: JAL target MIPS16e
681 // Purpose: Jump and Link
682 // To execute a procedure call within the current 256 MB-aligned
683 // region and preserve the current ISA.
686 def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
687 let hasDelaySlot = 0; // not true, but we add the nop for now
692 // Format: JR ra MIPS16e
693 // Purpose: Jump Register Through Register ra
694 // To execute a branch to the instruction address in the return
698 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
700 let isIndirectBranch = 1;
701 let hasDelaySlot = 1;
706 def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> {
708 let isIndirectBranch = 1;
713 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
715 let isIndirectBranch = 1;
720 // Format: LB ry, offset(rx) MIPS16e
721 // Purpose: Load Byte (Extended)
722 // To load a byte from memory as a signed value.
724 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{
725 let isCodeGenOnly = 1;
729 // Format: LBU ry, offset(rx) MIPS16e
730 // Purpose: Load Byte Unsigned (Extended)
731 // To load a byte from memory as a unsigned value.
733 def LbuRxRyOffMemX16:
734 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad {
735 let isCodeGenOnly = 1;
739 // Format: LH ry, offset(rx) MIPS16e
740 // Purpose: Load Halfword signed (Extended)
741 // To load a halfword from memory as a signed value.
743 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{
744 let isCodeGenOnly = 1;
748 // Format: LHU ry, offset(rx) MIPS16e
749 // Purpose: Load Halfword unsigned (Extended)
750 // To load a halfword from memory as an unsigned value.
752 def LhuRxRyOffMemX16:
753 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad {
754 let isCodeGenOnly = 1;
758 // Format: LI rx, immediate MIPS16e
759 // Purpose: Load Immediate
760 // To load a constant into a GPR.
762 def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>;
765 // Format: LI rx, immediate MIPS16e
766 // Purpose: Load Immediate (Extended)
767 // To load a constant into a GPR.
769 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
771 def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIAlu> {
772 let isCodeGenOnly = 1;
776 // Format: LW ry, offset(rx) MIPS16e
777 // Purpose: Load Word (Extended)
778 // To load a word from memory as a signed value.
780 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{
781 let isCodeGenOnly = 1;
784 // Format: LW rx, offset(sp) MIPS16e
785 // Purpose: Load Word (SP-Relative, Extended)
786 // To load an SP-relative word from memory as a signed value.
788 def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{
793 // Format: MOVE r32, rz MIPS16e
795 // To move the contents of a GPR to a GPR.
797 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
800 // Format: MOVE ry, r32 MIPS16e
802 // To move the contents of a GPR to a GPR.
804 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
807 // Format: MFHI rx MIPS16e
808 // Purpose: Move From HI Register
809 // To copy the special purpose HI register to a GPR.
811 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
813 let neverHasSideEffects = 1;
817 // Format: MFLO rx MIPS16e
818 // Purpose: Move From LO Register
819 // To copy the special purpose LO register to a GPR.
821 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
823 let neverHasSideEffects = 1;
827 // Pseudo Instruction for mult
829 def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
830 let isCommutable = 1;
831 let neverHasSideEffects = 1;
832 let Defs = [HI0, LO0];
835 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
836 let isCommutable = 1;
837 let neverHasSideEffects = 1;
838 let Defs = [HI0, LO0];
842 // Format: MULT rx, ry MIPS16e
843 // Purpose: Multiply Word
844 // To multiply 32-bit signed integers.
846 def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
847 let isCommutable = 1;
848 let neverHasSideEffects = 1;
849 let Defs = [HI0, LO0];
853 // Format: MULTU rx, ry MIPS16e
854 // Purpose: Multiply Unsigned Word
855 // To multiply 32-bit unsigned integers.
857 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
858 let isCommutable = 1;
859 let neverHasSideEffects = 1;
860 let Defs = [HI0, LO0];
864 // Format: NEG rx, ry MIPS16e
866 // To negate an integer value.
868 def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
871 // Format: NOT rx, ry MIPS16e
873 // To complement an integer value
875 def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
878 // Format: OR rx, ry MIPS16e
880 // To do a bitwise logical OR.
882 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
885 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
886 // (All args are optional) MIPS16e
887 // Purpose: Restore Registers and Deallocate Stack Frame
888 // To deallocate a stack frame before exit from a subroutine,
889 // restoring return address and static registers, and adjusting
893 // fixed form for restoring RA and the frame
894 // for direct object emitter, encoding needs to be adjusted for the
897 let ra=1, s=0,s0=1,s1=1 in
899 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
900 "restore\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IILoad >, MayLoad {
901 let isCodeGenOnly = 1;
902 let Defs = [S0, S1, S2, RA, SP];
906 // Use Restore to increment SP since SP is not a Mip 16 register, this
907 // is an easy way to do that which does not require a register.
909 let ra=0, s=0,s0=0,s1=0 in
911 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
912 "restore\t$frame_size", [], IILoad >, MayLoad {
913 let isCodeGenOnly = 1;
919 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
921 // Purpose: Save Registers and Set Up Stack Frame
922 // To set up a stack frame on entry to a subroutine,
923 // saving return address and static registers, and adjusting stack
925 let ra=1, s=1,s0=1,s1=1 in
927 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
928 "save\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IIStore >, MayStore {
929 let isCodeGenOnly = 1;
930 let Uses = [RA, SP, S0, S1, S2];
935 // Use Save to decrement the SP by a constant since SP is not
936 // a Mips16 register.
938 let ra=0, s=0,s0=0,s1=0 in
940 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
941 "save\t$frame_size", [], IIStore >, MayStore {
942 let isCodeGenOnly = 1;
947 // Format: SB ry, offset(rx) MIPS16e
948 // Purpose: Store Byte (Extended)
949 // To store a byte to memory.
952 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
955 // The Sel(T) instructions are pseudos
956 // T means that they use T8 implicitly.
959 // Format: SelBeqZ rd, rs, rt
960 // Purpose: if rt==0, do nothing
963 def SelBeqZ: Sel<"beqz">;
966 // Format: SelTBteqZCmp rd, rs, rl, rr
967 // Purpose: b = Cmp rl, rr.
968 // If b==0 then do nothing.
969 // if b!=0 then rd = rs
971 def SelTBteqZCmp: SelT<"bteqz", "cmp">;
974 // Format: SelTBteqZCmpi rd, rs, rl, rr
975 // Purpose: b = Cmpi rl, imm.
976 // If b==0 then do nothing.
977 // if b!=0 then rd = rs
979 def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">;
982 // Format: SelTBteqZSlt rd, rs, rl, rr
983 // Purpose: b = Slt rl, rr.
984 // If b==0 then do nothing.
985 // if b!=0 then rd = rs
987 def SelTBteqZSlt: SelT<"bteqz", "slt">;
990 // Format: SelTBteqZSlti rd, rs, rl, rr
991 // Purpose: b = Slti rl, imm.
992 // If b==0 then do nothing.
993 // if b!=0 then rd = rs
995 def SelTBteqZSlti: SeliT<"bteqz", "slti">;
998 // Format: SelTBteqZSltu rd, rs, rl, rr
999 // Purpose: b = Sltu rl, rr.
1000 // If b==0 then do nothing.
1001 // if b!=0 then rd = rs
1003 def SelTBteqZSltu: SelT<"bteqz", "sltu">;
1006 // Format: SelTBteqZSltiu rd, rs, rl, rr
1007 // Purpose: b = Sltiu rl, imm.
1008 // If b==0 then do nothing.
1009 // if b!=0 then rd = rs
1011 def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">;
1014 // Format: SelBnez rd, rs, rt
1015 // Purpose: if rt!=0, do nothing
1018 def SelBneZ: Sel<"bnez">;
1021 // Format: SelTBtneZCmp rd, rs, rl, rr
1022 // Purpose: b = Cmp rl, rr.
1023 // If b!=0 then do nothing.
1024 // if b0=0 then rd = rs
1026 def SelTBtneZCmp: SelT<"btnez", "cmp">;
1029 // Format: SelTBtnezCmpi rd, rs, rl, rr
1030 // Purpose: b = Cmpi rl, imm.
1031 // If b!=0 then do nothing.
1032 // if b==0 then rd = rs
1034 def SelTBtneZCmpi: SeliT<"btnez", "cmpi">;
1037 // Format: SelTBtneZSlt rd, rs, rl, rr
1038 // Purpose: b = Slt rl, rr.
1039 // If b!=0 then do nothing.
1040 // if b==0 then rd = rs
1042 def SelTBtneZSlt: SelT<"btnez", "slt">;
1045 // Format: SelTBtneZSlti rd, rs, rl, rr
1046 // Purpose: b = Slti rl, imm.
1047 // If b!=0 then do nothing.
1048 // if b==0 then rd = rs
1050 def SelTBtneZSlti: SeliT<"btnez", "slti">;
1053 // Format: SelTBtneZSltu rd, rs, rl, rr
1054 // Purpose: b = Sltu rl, rr.
1055 // If b!=0 then do nothing.
1056 // if b==0 then rd = rs
1058 def SelTBtneZSltu: SelT<"btnez", "sltu">;
1061 // Format: SelTBtneZSltiu rd, rs, rl, rr
1062 // Purpose: b = Slti rl, imm.
1063 // If b!=0 then do nothing.
1064 // if b==0 then rd = rs
1066 def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
1069 // Format: SH ry, offset(rx) MIPS16e
1070 // Purpose: Store Halfword (Extended)
1071 // To store a halfword to memory.
1073 def ShRxRyOffMemX16:
1074 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore;
1077 // Format: SLL rx, ry, sa MIPS16e
1078 // Purpose: Shift Word Left Logical (Extended)
1079 // To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
1081 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
1084 // Format: SLLV ry, rx MIPS16e
1085 // Purpose: Shift Word Left Logical Variable
1086 // To execute a left-shift of a word by a variable number of bits.
1088 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
1090 // Format: SLTI rx, immediate MIPS16e
1091 // Purpose: Set on Less Than Immediate
1092 // To record the result of a less-than comparison with a constant.
1095 def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> {
1100 // Format: SLTI rx, immediate MIPS16e
1101 // Purpose: Set on Less Than Immediate (Extended)
1102 // To record the result of a less-than comparison with a constant.
1105 def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> {
1109 def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
1111 // Format: SLTIU rx, immediate MIPS16e
1112 // Purpose: Set on Less Than Immediate Unsigned
1113 // To record the result of a less-than comparison with a constant.
1116 def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> {
1121 // Format: SLTI rx, immediate MIPS16e
1122 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1123 // To record the result of a less-than comparison with a constant.
1126 def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> {
1130 // Format: SLTIU rx, immediate MIPS16e
1131 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1132 // To record the result of a less-than comparison with a constant.
1134 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
1137 // Format: SLT rx, ry MIPS16e
1138 // Purpose: Set on Less Than
1139 // To record the result of a less-than comparison.
1141 def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{
1145 def SltCCRxRy16: FCCRR16_ins<"slt">;
1147 // Format: SLTU rx, ry MIPS16e
1148 // Purpose: Set on Less Than Unsigned
1149 // To record the result of an unsigned less-than comparison.
1151 def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{
1155 def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
1156 let isCodeGenOnly=1;
1161 def SltuCCRxRy16: FCCRR16_ins<"sltu">;
1163 // Format: SRAV ry, rx MIPS16e
1164 // Purpose: Shift Word Right Arithmetic Variable
1165 // To execute an arithmetic right-shift of a word by a variable
1168 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
1172 // Format: SRA rx, ry, sa MIPS16e
1173 // Purpose: Shift Word Right Arithmetic (Extended)
1174 // To execute an arithmetic right-shift of a word by a fixed
1175 // number of bits—1 to 8 bits.
1177 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
1181 // Format: SRLV ry, rx MIPS16e
1182 // Purpose: Shift Word Right Logical Variable
1183 // To execute a logical right-shift of a word by a variable
1186 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
1190 // Format: SRL rx, ry, sa MIPS16e
1191 // Purpose: Shift Word Right Logical (Extended)
1192 // To execute a logical right-shift of a word by a fixed
1193 // number of bits—1 to 31 bits.
1195 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
1198 // Format: SUBU rz, rx, ry MIPS16e
1199 // Purpose: Subtract Unsigned Word
1200 // To subtract 32-bit integers
1202 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
1205 // Format: SW ry, offset(rx) MIPS16e
1206 // Purpose: Store Word (Extended)
1207 // To store a word to memory.
1209 def SwRxRyOffMemX16:
1210 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore;
1213 // Format: SW rx, offset(sp) MIPS16e
1214 // Purpose: Store Word rx (SP-Relative)
1215 // To store an SP-relative word to memory.
1217 def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins
1218 <0b11010, "sw", IIStore>, MayStore;
1222 // Format: XOR rx, ry MIPS16e
1224 // To do a bitwise logical XOR.
1226 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
1228 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
1229 let Predicates = [InMips16Mode];
1232 // Unary Arith/Logic
1234 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1235 Mips16Pat<(OpNode CPU16Regs:$r),
1238 def: ArithLogicU_pat<not, NotRxRy16>;
1239 def: ArithLogicU_pat<ineg, NegRxRy16>;
1241 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1242 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1243 (I CPU16Regs:$l, CPU16Regs:$r)>;
1245 def: ArithLogic16_pat<add, AdduRxRyRz16>;
1246 def: ArithLogic16_pat<and, AndRxRxRy16>;
1247 def: ArithLogic16_pat<mul, MultRxRyRz16>;
1248 def: ArithLogic16_pat<or, OrRxRxRy16>;
1249 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
1250 def: ArithLogic16_pat<xor, XorRxRxRy16>;
1252 // Arithmetic and logical instructions with 2 register operands.
1254 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1255 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1256 (I CPU16Regs:$in, imm_type:$imm)>;
1258 def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>;
1259 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
1260 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
1261 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
1262 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
1264 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1265 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1266 (I CPU16Regs:$r, CPU16Regs:$ra)>;
1268 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
1269 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
1270 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
1272 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1273 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
1275 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
1276 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
1277 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
1278 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
1279 def: LoadM16_pat<load, LwRxRyOffMemX16>;
1281 class StoreM16_pat<PatFrag OpNode, Instruction I> :
1282 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr),
1283 (I CPU16Regs:$r, addr16:$addr)>;
1285 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
1286 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
1287 def: StoreM16_pat<store, SwRxRyOffMemX16>;
1289 // Unconditional branch
1290 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
1291 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1292 let Predicates = [InMips16Mode];
1295 def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1296 (Jal16 tglobaladdr:$dst)>;
1298 def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)),
1299 (Jal16 texternalsym:$dst)>;
1303 (brind CPU16Regs:$rs),
1304 (JrcRx16 CPU16Regs:$rs)>;
1306 // Jump and Link (Call)
1307 let isCall=1, hasDelaySlot=0 in
1309 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
1310 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
1313 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
1314 hasExtraSrcRegAllocReq = 1 in
1315 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
1320 class SetCC_R16<PatFrag cond_op, Instruction I>:
1321 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1322 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1324 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1325 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1326 (I CPU16Regs:$rx, imm_type:$imm16)>;
1329 def: Mips16Pat<(i32 addr16:$addr),
1330 (AddiuRxRyOffMemX16 addr16:$addr)>;
1333 // Large (>16 bit) immediate loads
1334 def : Mips16Pat<(i32 imm:$imm),
1335 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16),
1336 (LiRxImmX16 (LO16 imm:$imm)))>;
1338 // Carry MipsPatterns
1339 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
1340 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1341 def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
1342 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1343 def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
1344 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
1347 // Some branch conditional patterns are not generated by llvm at this time.
1348 // Some are for seemingly arbitrary reasons not used: i.e. with signed number
1349 // comparison they are used and for unsigned a different pattern is used.
1350 // I am pushing upstream from the full mips16 port and it seemed that I needed
1351 // these earlier and the mips32 port has these but now I cannot create test
1352 // cases that use these patterns. While I sort this all out I will leave these
1353 // extra patterns commented out and if I can be sure they are really not used,
1354 // I will delete the code. I don't want to check the code in uncommented without
1355 // a valid test case. In some cases, the compiler is generating patterns with
1356 // setcc instead and earlier I had implemented setcc first so may have masked
1357 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
1358 // figure out how to enable the brcond patterns or else possibly new
1359 // combinations of of brcond and setcc.
1365 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1366 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1371 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1372 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1376 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1377 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16)
1381 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1384 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1385 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1392 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1393 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1397 // never called because compiler transforms a >= k to a > (k-1)
1399 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1400 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1407 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1408 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1412 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1413 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1420 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1421 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1428 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1429 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1433 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1434 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1438 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1439 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1443 // This needs to be there but I forget which code will generate it
1446 <(brcond CPU16Regs:$rx, bb:$targ16),
1447 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1456 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1457 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1464 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1465 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1473 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1474 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1477 def: UncondBranch16_pat<br, BimmX16>;
1480 def: Mips16Pat<(i32 immSExt16:$in),
1481 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
1483 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
1489 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry),
1490 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1496 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry),
1497 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1502 // if !(a < b) x = y
1504 def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1505 CPU16Regs:$x, CPU16Regs:$y),
1506 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1507 CPU16Regs:$a, CPU16Regs:$b)>;
1514 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1515 CPU16Regs:$x, CPU16Regs:$y),
1516 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
1517 CPU16Regs:$b, CPU16Regs:$a)>;
1522 // if !(a < b) x = y;
1525 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
1526 CPU16Regs:$x, CPU16Regs:$y),
1527 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1528 CPU16Regs:$a, CPU16Regs:$b)>;
1535 def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
1536 CPU16Regs:$x, CPU16Regs:$y),
1537 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
1538 CPU16Regs:$b, CPU16Regs:$a)>;
1542 // due to an llvm optimization, i don't think that this will ever
1543 // be used. This is transformed into x = (a > k-1)?x:y
1548 // (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1549 // CPU16Regs:$T, CPU16Regs:$F),
1550 // (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
1551 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1554 // (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
1555 // CPU16Regs:$T, CPU16Regs:$F),
1556 // (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
1557 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1562 // if !(a < k) x = y;
1565 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1566 CPU16Regs:$x, CPU16Regs:$y),
1567 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
1568 CPU16Regs:$a, immSExt16:$b)>;
1574 // x = (a <= b)? x : y
1578 def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
1579 CPU16Regs:$x, CPU16Regs:$y),
1580 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1581 CPU16Regs:$b, CPU16Regs:$a)>;
1585 // x = (a <= b)? x : y
1589 def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
1590 CPU16Regs:$x, CPU16Regs:$y),
1591 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1592 CPU16Regs:$b, CPU16Regs:$a)>;
1596 // x = (a == b)? x : y
1598 // if (a != b) x = y
1600 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
1601 CPU16Regs:$x, CPU16Regs:$y),
1602 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
1603 CPU16Regs:$b, CPU16Regs:$a)>;
1607 // x = (a == 0)? x : y
1609 // if (a != 0) x = y
1611 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
1612 CPU16Regs:$x, CPU16Regs:$y),
1613 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
1619 // x = (a == k)? x : y
1621 // if (a != k) x = y
1623 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
1624 CPU16Regs:$x, CPU16Regs:$y),
1625 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
1626 CPU16Regs:$a, immZExt16:$k)>;
1631 // x = (a != b)? x : y
1633 // if (a == b) x = y
1636 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1637 CPU16Regs:$x, CPU16Regs:$y),
1638 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
1639 CPU16Regs:$b, CPU16Regs:$a)>;
1643 // x = (a != 0)? x : y
1645 // if (a == 0) x = y
1647 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1648 CPU16Regs:$x, CPU16Regs:$y),
1649 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1657 def : Mips16Pat<(select CPU16Regs:$a,
1658 CPU16Regs:$x, CPU16Regs:$y),
1659 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1665 // x = (a != k)? x : y
1667 // if (a == k) x = y
1669 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1670 CPU16Regs:$x, CPU16Regs:$y),
1671 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
1672 CPU16Regs:$a, immZExt16:$k)>;
1675 // When writing C code to test setxx these patterns,
1676 // some will be transformed into
1677 // other things. So we test using C code but using -O3 and -O0
1682 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
1683 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
1686 <(seteq CPU16Regs:$lhs, 0),
1687 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
1695 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1696 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1700 // For constants, llvm transforms this to:
1701 // x > (k -1) and then reverses the operands to use setlt. So this pattern
1702 // is not used now by the compiler. (Presumably checking that k-1 does not
1703 // overflow). The compiler never uses this at a the current time, due to
1704 // other optimizations.
1707 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
1708 // (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
1709 // (LiRxImmX16 1))>;
1711 // This catches the x >= -32768 case by transforming it to x > -32769
1714 <(setgt CPU16Regs:$lhs, -32769),
1715 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
1724 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
1725 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1731 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
1732 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>;
1737 def: SetCC_R16<setlt, SltCCRxRy16>;
1739 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
1745 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
1746 (SltuCCRxRy16 (LiRxImmX16 0),
1747 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1754 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1755 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1758 // this pattern will never be used because the compiler will transform
1759 // x >= k to x > (k - 1) and then use SLT
1762 // <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1763 // (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1764 // (LiRxImmX16 1))>;
1770 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1771 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1777 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1778 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1783 def: SetCC_R16<setult, SltuCCRxRy16>;
1785 def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1787 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1788 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
1792 def : Mips16Pat<(MipsHi tglobaladdr:$in),
1793 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>;
1794 def : Mips16Pat<(MipsHi tjumptable:$in),
1795 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>;
1796 def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
1797 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
1800 class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1801 Mips16Pat<(MipsWrapper RC:$gp, node:$in),
1802 (ADDiuOp RC:$gp, node:$in)>;
1805 def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>;
1806 def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
1808 def : Mips16Pat<(i32 (extloadi8 addr16:$src)),
1809 (LbuRxRyOffMemX16 addr16:$src)>;
1810 def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
1811 (LhuRxRyOffMemX16 addr16:$src)>;
1813 def: Mips16Pat<(trap), (Break16)>;
1817 (outs CPU16Regs:$rh, CPU16Regs:$rl),
1818 (ins simm16:$immHi, simm16:$immLo),
1819 ".align 2\n\tli\t$rh, $immHi\n\taddiu\t$rl, $$pc, $immLo\n ",[]> ;