1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
15 // RRR-type instruction format
18 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
19 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
20 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
23 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
25 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
26 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32),
27 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
30 // I8_MOV32R instruction format (used only by MOV32R instruction)
33 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
34 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
35 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
38 // EXT-RI instruction format
41 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
43 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
44 !strconcat(asmstr, asmstr2), [], itin>;
46 class FEXT_RI16_ins<bits<5> _op, string asmstr,
48 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
50 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
51 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
54 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
56 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
57 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
58 let Constraints = "$rx_ = $rx";
63 // RR-type instruction format
66 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
67 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
68 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
71 class FRxRxRy16_ins<bits<5> f, string asmstr,
72 InstrItinClass itin> :
73 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
74 !strconcat(asmstr, "\t$rz, $ry"),
76 let Constraints = "$rx = $rz";
80 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
81 string asmstr, InstrItinClass itin>:
82 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
86 // EXT-RRI instruction format
89 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
91 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
92 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
94 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
96 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
97 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
100 // EXT-SHIFT instruction format
102 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
103 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
104 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
108 def mem16 : Operand<i32> {
109 let PrintMethod = "printMemOperand";
110 let MIOperandInfo = (ops CPU16Regs, simm16);
111 let EncoderMethod = "getMemEncoding";
115 // Some general instruction class info
119 class ArithLogic16Defs<bit isCom=0> {
121 bit isCommutable = isCom;
122 bit isReMaterializable = 1;
123 bit neverHasSideEffects = 1;
128 // Format: ADDIU rx, immediate MIPS16e
129 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
130 // To add a constant to a 32-bit integer.
132 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
134 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
139 // Format: ADDIU rx, pc, immediate MIPS16e
140 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
141 // To add a constant to the program counter.
143 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
145 // Format: ADDU rz, rx, ry MIPS16e
146 // Purpose: Add Unsigned Word (3-Operand)
147 // To add 32-bit integers.
150 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
153 // Format: AND rx, ry MIPS16e
155 // To do a bitwise logical AND.
157 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
160 // Format: JR ra MIPS16e
161 // Purpose: Jump Register Through Register ra
162 // To execute a branch to the instruction address in the return
166 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu>;
169 // Format: LB ry, offset(rx) MIPS16e
170 // Purpose: Load Byte (Extended)
171 // To load a byte from memory as a signed value.
173 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IIAlu>;
176 // Format: LBU ry, offset(rx) MIPS16e
177 // Purpose: Load Byte Unsigned (Extended)
178 // To load a byte from memory as a unsigned value.
180 def LbuRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IIAlu>;
183 // Format: LH ry, offset(rx) MIPS16e
184 // Purpose: Load Halfword signed (Extended)
185 // To load a halfword from memory as a signed value.
187 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IIAlu>;
190 // Format: LHU ry, offset(rx) MIPS16e
191 // Purpose: Load Halfword unsigned (Extended)
192 // To load a halfword from memory as an unsigned value.
194 def LhuRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IIAlu>;
197 // Format: LI rx, immediate MIPS16e
198 // Purpose: Load Immediate (Extended)
199 // To load a constant into a GPR.
201 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
204 // Format: LW ry, offset(rx) MIPS16e
205 // Purpose: Load Word (Extended)
206 // To load a word from memory as a signed value.
208 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IIAlu>;
211 // Format: MOVE r32, rz MIPS16e
213 // To move the contents of a GPR to a GPR.
215 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
218 // Format: MOVE ry, r32 MIPS16e
220 // To move the contents of a GPR to a GPR.
222 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
225 // Format: NEG rx, ry MIPS16e
227 // To negate an integer value.
229 def NegRxRy16: FRR16_ins<0b11101, "neg", IIAlu>;
232 // Format: NOT rx, ry MIPS16e
234 // To complement an integer value
236 def NotRxRy16: FRR16_ins<0b01111, "not", IIAlu>;
239 // Format: OR rx, ry MIPS16e
241 // To do a bitwise logical OR.
243 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
246 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
247 // (All args are optional) MIPS16e
248 // Purpose: Restore Registers and Deallocate Stack Frame
249 // To deallocate a stack frame before exit from a subroutine,
250 // restoring return address and static registers, and adjusting
254 // fixed form for restoring RA and the frame
255 // for direct object emitter, encoding needs to be adjusted for the
258 let ra=1, s=0,s0=1,s1=1 in
260 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
261 "restore \t$$ra, $$s0, $$s1, $frame_size", [], IILoad > {
262 let isCodeGenOnly = 1;
266 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
268 // Purpose: Save Registers and Set Up Stack Frame
269 // To set up a stack frame on entry to a subroutine,
270 // saving return address and static registers, and adjusting stack
272 let ra=1, s=1,s0=1,s1=1 in
274 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
275 "save \t$$ra, $$s0, $$s1, $frame_size", [], IILoad > {
276 let isCodeGenOnly = 1;
279 // Format: SB ry, offset(rx) MIPS16e
280 // Purpose: Store Byte (Extended)
281 // To store a byte to memory.
283 def SbRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIAlu>;
286 // Format: SH ry, offset(rx) MIPS16e
287 // Purpose: Store Halfword (Extended)
288 // To store a halfword to memory.
290 def ShRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIAlu>;
293 // Format: SLL rx, ry, sa MIPS16e
294 // Purpose: Shift Word Left Logical (Extended)
295 // To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
297 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
300 // Format: SLLV ry, rx MIPS16e
301 // Purpose: Shift Word Left Logical Variable
302 // To execute a left-shift of a word by a variable number of bits.
304 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
308 // Format: SRAV ry, rx MIPS16e
309 // Purpose: Shift Word Right Arithmetic Variable
310 // To execute an arithmetic right-shift of a word by a variable
313 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
317 // Format: SRA rx, ry, sa MIPS16e
318 // Purpose: Shift Word Right Arithmetic (Extended)
319 // To execute an arithmetic right-shift of a word by a fixed
320 // number of bits—1 to 8 bits.
322 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
326 // Format: SRLV ry, rx MIPS16e
327 // Purpose: Shift Word Right Logical Variable
328 // To execute a logical right-shift of a word by a variable
331 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
335 // Format: SRL rx, ry, sa MIPS16e
336 // Purpose: Shift Word Right Logical (Extended)
337 // To execute a logical right-shift of a word by a fixed
338 // number of bits—1 to 31 bits.
340 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
343 // Format: SUBU rz, rx, ry MIPS16e
344 // Purpose: Subtract Unsigned Word
345 // To subtract 32-bit integers
347 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
350 // Format: SW ry, offset(rx) MIPS16e
351 // Purpose: Store Word (Extended)
352 // To store a word to memory.
354 def SwRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIAlu>;
357 // Format: XOR rx, ry MIPS16e
359 // To do a bitwise logical XOR.
361 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
363 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
364 let Predicates = [InMips16Mode];
369 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
370 Mips16Pat<(OpNode CPU16Regs:$r),
373 def: ArithLogicU_pat<not, NotRxRy16>;
374 def: ArithLogicU_pat<ineg, NegRxRy16>;
376 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
377 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
378 (I CPU16Regs:$l, CPU16Regs:$r)>;
380 def: ArithLogic16_pat<add, AdduRxRyRz16>;
381 def: ArithLogic16_pat<and, AndRxRxRy16>;
382 def: ArithLogic16_pat<or, OrRxRxRy16>;
383 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
384 def: ArithLogic16_pat<xor, XorRxRxRy16>;
386 // Arithmetic and logical instructions with 2 register operands.
388 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
389 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
390 (I CPU16Regs:$in, imm_type:$imm)>;
392 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
393 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
394 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
395 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
397 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
398 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
399 (I CPU16Regs:$r, CPU16Regs:$ra)>;
401 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
402 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
403 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
405 class LoadM16_pat<PatFrag OpNode, Instruction I> :
406 Mips16Pat<(OpNode addr:$addr), (I addr:$addr)>;
408 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
409 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
410 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
411 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
412 def: LoadM16_pat<load, LwRxRyOffMemX16>;
414 class StoreM16_pat<PatFrag OpNode, Instruction I> :
415 Mips16Pat<(OpNode CPU16Regs:$r, addr:$addr), (I CPU16Regs:$r, addr:$addr)>;
417 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
418 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
419 def: StoreM16_pat<store, SwRxRyOffMemX16>;
422 // Jump and Link (Call)
423 let isCall=1, hasDelaySlot=1 in
425 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
426 "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
429 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
430 hasExtraSrcRegAllocReq = 1 in
431 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
434 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
436 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
437 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;