1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
18 ComplexPattern<iPTR, 3, "SelectAddr16", [frameindex], [SDNPWantParent]>;
22 def mem16 : Operand<i32> {
23 let PrintMethod = "printMemOperand";
24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16Regs);
25 let EncoderMethod = "getMemEncoding";
28 def mem16_ea : Operand<i32> {
29 let PrintMethod = "printMemOperandEA";
30 let MIOperandInfo = (ops CPU16Regs, simm16);
31 let EncoderMethod = "getMemEncoding";
35 // Compare a register and immediate and place result in CC
38 // EXT-CCRR Instruction format
40 class FEXT_CCRXI16_ins<bits<5> _op, string asmstr,
42 FEXT_RI16<_op, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
43 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), [], itin> {
48 // EXT-I instruction format
50 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
51 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
52 !strconcat(asmstr, "\t$imm16"),[], itin>;
55 // EXT-I8 instruction format
58 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
59 string asmstr2, InstrItinClass itin>:
60 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
63 class FEXT_I816_ins<bits<3> _func, string asmstr,
65 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
67 class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
69 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>;
72 // Assembler formats in alphabetical order.
73 // Natural and pseudos are mixed together.
75 // Compare two registers and place result in CC
78 // CC-RR Instruction format
80 class FCCRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
81 FRR16<f, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
82 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), [], itin> {
87 // EXT-RI instruction format
90 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
92 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
93 !strconcat(asmstr, asmstr2), [], itin>;
95 class FEXT_RI16_ins<bits<5> _op, string asmstr,
97 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
99 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
100 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
102 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
103 InstrItinClass itin>:
104 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
105 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
107 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
108 InstrItinClass itin>:
109 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
110 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
111 let Constraints = "$rx_ = $rx";
115 // this has an explicit sp argument that we ignore to work around a problem
117 class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
118 InstrItinClass itin>:
119 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
120 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
123 // EXT-RRI instruction format
126 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
127 InstrItinClass itin>:
128 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
129 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
131 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
132 InstrItinClass itin>:
133 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
134 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
138 // EXT-RRI-A instruction format
141 class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
142 InstrItinClass itin>:
143 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
144 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
147 // EXT-SHIFT instruction format
149 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
150 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
151 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
156 class FEXT_T8I816_ins<bits<3> _func, string asmstr, string asmstr2,
157 InstrItinClass itin>:
158 FEXT_I816<_func, (outs),
159 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
160 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
161 !strconcat(asmstr, "\t$imm"))),[], itin> {
168 class FEXT_T8I8I16_ins<bits<3> _func, string asmstr, string asmstr2,
169 InstrItinClass itin>:
170 FEXT_I816<_func, (outs),
171 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
172 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
173 !strconcat(asmstr, "\t$targ"))), [], itin> {
180 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
182 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
183 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32),
184 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
187 // I8_MOV32R instruction format (used only by MOV32R instruction)
190 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
191 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
192 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
195 // This are pseudo formats for multiply
196 // This first one can be changed to non pseudo now.
200 class FMULT16_ins<string asmstr, InstrItinClass itin> :
201 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
202 !strconcat(asmstr, "\t$rx, $ry"), []>;
207 class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
208 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
209 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
214 // RR-type instruction format
217 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
218 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
219 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
222 class FRRTR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
223 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
224 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), [], itin> ;
227 // maybe refactor but need a $zero as a dummy first parameter
229 class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
230 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
231 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
233 class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
234 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
235 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
238 class FRR16_M_ins<bits<5> f, string asmstr,
239 InstrItinClass itin> :
240 FRR16<f, (outs CPU16Regs:$rx), (ins),
241 !strconcat(asmstr, "\t$rx"), [], itin>;
243 class FRxRxRy16_ins<bits<5> f, string asmstr,
244 InstrItinClass itin> :
245 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
246 !strconcat(asmstr, "\t$rz, $ry"),
248 let Constraints = "$rx = $rz";
252 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
253 string asmstr, InstrItinClass itin>:
254 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
258 class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
259 string asmstr, InstrItinClass itin>:
260 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
261 !strconcat(asmstr, "\t $rx"), [], itin> ;
264 // RRR-type instruction format
267 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
268 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
269 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
272 // These Sel patterns support the generation of conditional move
273 // pseudo instructions.
275 // The nomenclature uses the components making up the pseudo and may
276 // be a bit counter intuitive when compared with the end result we seek.
277 // For example using a bqez in the example directly below results in the
278 // conditional move being done if the tested register is not zero.
279 // I considered in easier to check by keeping the pseudo consistent with
280 // it's components but it could have been done differently.
282 // The simplest case is when can test and operand directly and do the
283 // conditional move based on a simple mips16 conditional
284 // branch instruction.
286 // if $op == beqz or bnez:
291 // if $op == beqz, then if $rt != 0, then the conditional assignment
292 // $rd = $rs is done.
294 // if $op == bnez, then if $rt == 0, then the conditional assignment
295 // $rd = $rs is done.
297 // So this pseudo class only has one operand, i.e. op
299 class Sel<bits<5> f1, string op, InstrItinClass itin>:
300 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
302 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), [], itin,
305 let Constraints = "$rd = $rd_";
309 // The next two instruction classes allow for an operand which tests
310 // two operands and returns a value in register T8 and
311 //then does a conditional branch based on the value of T8
314 // op2 can be cmpi or slti/sltiu
315 // op1 can bteqz or btnez
316 // the operands for op2 are a register and a signed constant
318 // $op2 $t, $imm ;test register t and branch conditionally
319 // $op1 .+4 ;op1 is a conditional branch
323 class SeliT<bits<5> f1, string op1, bits<5> f2, string op2,
324 InstrItinClass itin>:
325 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
326 CPU16Regs:$rl, simm16:$imm),
328 !strconcat("\t$rl, $imm\n\t",
329 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin,
332 let Constraints = "$rd = $rd_";
336 // op2 can be cmp or slt/sltu
337 // op1 can be bteqz or btnez
338 // the operands for op2 are two registers
339 // op1 is a conditional branch
342 // $op2 $rl, $rr ;test registers rl,rr
343 // $op1 .+4 ;op2 is a conditional branch
347 class SelT<bits<5> f1, string op1, bits<5> f2, string op2,
348 InstrItinClass itin>:
349 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
350 CPU16Regs:$rl, CPU16Regs:$rr),
352 !strconcat("\t$rl, $rr\n\t",
353 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin,
356 let Constraints = "$rd = $rd_";
362 def imm32: Operand<i32>;
365 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
368 MipsPseudo16<(outs), (ins CPU16Regs:$rx, imm32:$imm),
369 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
373 // Some general instruction class info
377 class ArithLogic16Defs<bit isCom=0> {
379 bit isCommutable = isCom;
380 bit isReMaterializable = 1;
381 bit neverHasSideEffects = 1;
386 bit isTerminator = 1;
392 bit isTerminator = 1;
404 // Format: ADDIU rx, immediate MIPS16e
405 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
406 // To add a constant to a 32-bit integer.
408 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
410 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
413 def AddiuRxRyOffMemX16:
414 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>;
418 // Format: ADDIU rx, pc, immediate MIPS16e
419 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
420 // To add a constant to the program counter.
422 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
425 // Format: ADDIU sp, immediate MIPS16e
426 // Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
427 // To add a constant to the stack pointer.
430 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
436 // Format: ADDU rz, rx, ry MIPS16e
437 // Purpose: Add Unsigned Word (3-Operand)
438 // To add 32-bit integers.
441 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
444 // Format: AND rx, ry MIPS16e
446 // To do a bitwise logical AND.
448 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
452 // Format: BEQZ rx, offset MIPS16e
453 // Purpose: Branch on Equal to Zero (Extended)
454 // To test a GPR then do a PC-relative conditional branch.
456 def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
458 // Format: B offset MIPS16e
459 // Purpose: Unconditional Branch
460 // To do an unconditional PC-relative branch.
462 def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
465 // Format: BNEZ rx, offset MIPS16e
466 // Purpose: Branch on Not Equal to Zero (Extended)
467 // To test a GPR then do a PC-relative conditional branch.
469 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
472 // Format: BTEQZ offset MIPS16e
473 // Purpose: Branch on T Equal to Zero (Extended)
474 // To test special register T then do a PC-relative conditional branch.
476 def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16;
478 def BteqzT8CmpX16: FEXT_T8I816_ins<0b000, "bteqz", "cmp", IIAlu>, cbranch16;
480 def BteqzT8CmpiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "cmpi", IIAlu>,
483 def BteqzT8SltX16: FEXT_T8I816_ins<0b000, "bteqz", "slt", IIAlu>, cbranch16;
485 def BteqzT8SltuX16: FEXT_T8I816_ins<0b000, "bteqz", "sltu", IIAlu>, cbranch16;
487 def BteqzT8SltiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "slti", IIAlu>, cbranch16;
489 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<0b000, "bteqz", "sltiu", IIAlu>,
493 // Format: BTNEZ offset MIPS16e
494 // Purpose: Branch on T Not Equal to Zero (Extended)
495 // To test special register T then do a PC-relative conditional branch.
497 def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16;
499 def BtnezT8CmpX16: FEXT_T8I816_ins<0b000, "btnez", "cmp", IIAlu>, cbranch16;
501 def BtnezT8CmpiX16: FEXT_T8I8I16_ins<0b000, "btnez", "cmpi", IIAlu>, cbranch16;
503 def BtnezT8SltX16: FEXT_T8I816_ins<0b000, "btnez", "slt", IIAlu>, cbranch16;
505 def BtnezT8SltuX16: FEXT_T8I816_ins<0b000, "btnez", "sltu", IIAlu>, cbranch16;
507 def BtnezT8SltiX16: FEXT_T8I8I16_ins<0b000, "btnez", "slti", IIAlu>, cbranch16;
509 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<0b000, "btnez", "sltiu", IIAlu>,
513 // Format: DIV rx, ry MIPS16e
514 // Purpose: Divide Word
515 // To divide 32-bit signed integers.
517 def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
522 // Format: DIVU rx, ry MIPS16e
523 // Purpose: Divide Unsigned Word
524 // To divide 32-bit unsigned integers.
526 def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
532 // Format: JR ra MIPS16e
533 // Purpose: Jump Register Through Register ra
534 // To execute a branch to the instruction address in the return
538 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
540 let isIndirectBranch = 1;
541 let hasDelaySlot = 1;
546 def JrcRa16: FRR16_JALRC_RA_only_ins<0, 0, "jrc", IIAlu> {
548 let isIndirectBranch = 1;
553 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
555 let isIndirectBranch = 1;
560 // Format: LB ry, offset(rx) MIPS16e
561 // Purpose: Load Byte (Extended)
562 // To load a byte from memory as a signed value.
564 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad;
567 // Format: LBU ry, offset(rx) MIPS16e
568 // Purpose: Load Byte Unsigned (Extended)
569 // To load a byte from memory as a unsigned value.
571 def LbuRxRyOffMemX16:
572 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad;
575 // Format: LH ry, offset(rx) MIPS16e
576 // Purpose: Load Halfword signed (Extended)
577 // To load a halfword from memory as a signed value.
579 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad;
582 // Format: LHU ry, offset(rx) MIPS16e
583 // Purpose: Load Halfword unsigned (Extended)
584 // To load a halfword from memory as an unsigned value.
586 def LhuRxRyOffMemX16:
587 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad;
590 // Format: LI rx, immediate MIPS16e
591 // Purpose: Load Immediate (Extended)
592 // To load a constant into a GPR.
594 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
597 // Format: LW ry, offset(rx) MIPS16e
598 // Purpose: Load Word (Extended)
599 // To load a word from memory as a signed value.
601 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad;
603 // Format: LW rx, offset(sp) MIPS16e
604 // Purpose: Load Word (SP-Relative, Extended)
605 // To load an SP-relative word from memory as a signed value.
607 def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{
612 // Format: MOVE r32, rz MIPS16e
614 // To move the contents of a GPR to a GPR.
616 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
619 // Format: MOVE ry, r32 MIPS16e
621 // To move the contents of a GPR to a GPR.
623 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
626 // Format: MFHI rx MIPS16e
627 // Purpose: Move From HI Register
628 // To copy the special purpose HI register to a GPR.
630 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
632 let neverHasSideEffects = 1;
636 // Format: MFLO rx MIPS16e
637 // Purpose: Move From LO Register
638 // To copy the special purpose LO register to a GPR.
640 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
642 let neverHasSideEffects = 1;
646 // Pseudo Instruction for mult
648 def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
649 let isCommutable = 1;
650 let neverHasSideEffects = 1;
654 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
655 let isCommutable = 1;
656 let neverHasSideEffects = 1;
661 // Format: MULT rx, ry MIPS16e
662 // Purpose: Multiply Word
663 // To multiply 32-bit signed integers.
665 def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
666 let isCommutable = 1;
667 let neverHasSideEffects = 1;
672 // Format: MULTU rx, ry MIPS16e
673 // Purpose: Multiply Unsigned Word
674 // To multiply 32-bit unsigned integers.
676 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
677 let isCommutable = 1;
678 let neverHasSideEffects = 1;
683 // Format: NEG rx, ry MIPS16e
685 // To negate an integer value.
687 def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
690 // Format: NOT rx, ry MIPS16e
692 // To complement an integer value
694 def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
697 // Format: OR rx, ry MIPS16e
699 // To do a bitwise logical OR.
701 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
704 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
705 // (All args are optional) MIPS16e
706 // Purpose: Restore Registers and Deallocate Stack Frame
707 // To deallocate a stack frame before exit from a subroutine,
708 // restoring return address and static registers, and adjusting
712 // fixed form for restoring RA and the frame
713 // for direct object emitter, encoding needs to be adjusted for the
716 let ra=1, s=0,s0=1,s1=1 in
718 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
719 "restore\t$$ra, $$s0, $$s1, $frame_size", [], IILoad >, MayLoad {
720 let isCodeGenOnly = 1;
721 let Defs = [S0, S1, RA, SP];
725 // Use Restore to increment SP since SP is not a Mip 16 register, this
726 // is an easy way to do that which does not require a register.
728 let ra=0, s=0,s0=0,s1=0 in
730 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
731 "restore\t$frame_size", [], IILoad >, MayLoad {
732 let isCodeGenOnly = 1;
738 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
740 // Purpose: Save Registers and Set Up Stack Frame
741 // To set up a stack frame on entry to a subroutine,
742 // saving return address and static registers, and adjusting stack
744 let ra=1, s=1,s0=1,s1=1 in
746 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
747 "save\t$$ra, $$s0, $$s1, $frame_size", [], IIStore >, MayStore {
748 let isCodeGenOnly = 1;
749 let Uses = [RA, SP, S0, S1];
754 // Use Save to decrement the SP by a constant since SP is not
755 // a Mips16 register.
757 let ra=0, s=0,s0=0,s1=0 in
759 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
760 "save\t$frame_size", [], IIStore >, MayStore {
761 let isCodeGenOnly = 1;
766 // Format: SB ry, offset(rx) MIPS16e
767 // Purpose: Store Byte (Extended)
768 // To store a byte to memory.
771 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
774 // The Sel(T) instructions are pseudos
775 // T means that they use T8 implicitly.
778 // Format: SelBeqZ rd, rs, rt
779 // Purpose: if rt==0, do nothing
782 def SelBeqZ: Sel<0b00100, "beqz", IIAlu>;
785 // Format: SelTBteqZCmp rd, rs, rl, rr
786 // Purpose: b = Cmp rl, rr.
787 // If b==0 then do nothing.
788 // if b!=0 then rd = rs
790 def SelTBteqZCmp: SelT<0b000, "bteqz", 0b01010, "cmp", IIAlu>;
793 // Format: SelTBteqZCmpi rd, rs, rl, rr
794 // Purpose: b = Cmpi rl, imm.
795 // If b==0 then do nothing.
796 // if b!=0 then rd = rs
798 def SelTBteqZCmpi: SeliT<0b000, "bteqz", 0b01110, "cmpi", IIAlu>;
801 // Format: SelTBteqZSlt rd, rs, rl, rr
802 // Purpose: b = Slt rl, rr.
803 // If b==0 then do nothing.
804 // if b!=0 then rd = rs
806 def SelTBteqZSlt: SelT<0b000, "bteqz", 0b00010, "slt", IIAlu>;
809 // Format: SelTBteqZSlti rd, rs, rl, rr
810 // Purpose: b = Slti rl, imm.
811 // If b==0 then do nothing.
812 // if b!=0 then rd = rs
814 def SelTBteqZSlti: SeliT<0b000, "bteqz", 0b01010, "slti", IIAlu>;
817 // Format: SelTBteqZSltu rd, rs, rl, rr
818 // Purpose: b = Sltu rl, rr.
819 // If b==0 then do nothing.
820 // if b!=0 then rd = rs
822 def SelTBteqZSltu: SelT<0b000, "bteqz", 0b00011, "sltu", IIAlu>;
825 // Format: SelTBteqZSltiu rd, rs, rl, rr
826 // Purpose: b = Sltiu rl, imm.
827 // If b==0 then do nothing.
828 // if b!=0 then rd = rs
830 def SelTBteqZSltiu: SeliT<0b000, "bteqz", 0b01011, "sltiu", IIAlu>;
833 // Format: SelBnez rd, rs, rt
834 // Purpose: if rt!=0, do nothing
837 def SelBneZ: Sel<0b00101, "bnez", IIAlu>;
840 // Format: SelTBtneZCmp rd, rs, rl, rr
841 // Purpose: b = Cmp rl, rr.
842 // If b!=0 then do nothing.
843 // if b0=0 then rd = rs
845 def SelTBtneZCmp: SelT<0b001, "btnez", 0b01010, "cmp", IIAlu>;
848 // Format: SelTBtnezCmpi rd, rs, rl, rr
849 // Purpose: b = Cmpi rl, imm.
850 // If b!=0 then do nothing.
851 // if b==0 then rd = rs
853 def SelTBtneZCmpi: SeliT<0b000, "btnez", 0b01110, "cmpi", IIAlu>;
856 // Format: SelTBtneZSlt rd, rs, rl, rr
857 // Purpose: b = Slt rl, rr.
858 // If b!=0 then do nothing.
859 // if b==0 then rd = rs
861 def SelTBtneZSlt: SelT<0b001, "btnez", 0b00010, "slt", IIAlu>;
864 // Format: SelTBtneZSlti rd, rs, rl, rr
865 // Purpose: b = Slti rl, imm.
866 // If b!=0 then do nothing.
867 // if b==0 then rd = rs
869 def SelTBtneZSlti: SeliT<0b001, "btnez", 0b01010, "slti", IIAlu>;
872 // Format: SelTBtneZSltu rd, rs, rl, rr
873 // Purpose: b = Sltu rl, rr.
874 // If b!=0 then do nothing.
875 // if b==0 then rd = rs
877 def SelTBtneZSltu: SelT<0b001, "btnez", 0b00011, "sltu", IIAlu>;
880 // Format: SelTBtneZSltiu rd, rs, rl, rr
881 // Purpose: b = Slti rl, imm.
882 // If b!=0 then do nothing.
883 // if b==0 then rd = rs
885 def SelTBtneZSltiu: SeliT<0b001, "btnez", 0b01011, "sltiu", IIAlu>;
888 // Format: SH ry, offset(rx) MIPS16e
889 // Purpose: Store Halfword (Extended)
890 // To store a halfword to memory.
893 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore;
896 // Format: SLL rx, ry, sa MIPS16e
897 // Purpose: Shift Word Left Logical (Extended)
898 // To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
900 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
903 // Format: SLLV ry, rx MIPS16e
904 // Purpose: Shift Word Left Logical Variable
905 // To execute a left-shift of a word by a variable number of bits.
907 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
910 // Format: SLTI rx, immediate MIPS16e
911 // Purpose: Set on Less Than Immediate (Extended)
912 // To record the result of a less-than comparison with a constant.
914 def SltiCCRxImmX16: FEXT_CCRXI16_ins<0b01010, "slti", IIAlu>;
917 // Format: SLTIU rx, immediate MIPS16e
918 // Purpose: Set on Less Than Immediate Unsigned (Extended)
919 // To record the result of a less-than comparison with a constant.
921 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<0b01011, "sltiu", IIAlu>;
924 // Format: SLT rx, ry MIPS16e
925 // Purpose: Set on Less Than
926 // To record the result of a less-than comparison.
928 def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>;
930 def SltCCRxRy16: FCCRR16_ins<0b00010, "slt", IIAlu>;
932 // Format: SLTU rx, ry MIPS16e
933 // Purpose: Set on Less Than Unsigned
934 // To record the result of an unsigned less-than comparison.
936 def SltuRxRyRz16: FRRTR16_ins<0b00011, "sltu", IIAlu> {
941 def SltuCCRxRy16: FCCRR16_ins<0b00011, "sltu", IIAlu>;
943 // Format: SRAV ry, rx MIPS16e
944 // Purpose: Shift Word Right Arithmetic Variable
945 // To execute an arithmetic right-shift of a word by a variable
948 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
952 // Format: SRA rx, ry, sa MIPS16e
953 // Purpose: Shift Word Right Arithmetic (Extended)
954 // To execute an arithmetic right-shift of a word by a fixed
955 // number of bits—1 to 8 bits.
957 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
961 // Format: SRLV ry, rx MIPS16e
962 // Purpose: Shift Word Right Logical Variable
963 // To execute a logical right-shift of a word by a variable
966 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
970 // Format: SRL rx, ry, sa MIPS16e
971 // Purpose: Shift Word Right Logical (Extended)
972 // To execute a logical right-shift of a word by a fixed
973 // number of bits—1 to 31 bits.
975 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
978 // Format: SUBU rz, rx, ry MIPS16e
979 // Purpose: Subtract Unsigned Word
980 // To subtract 32-bit integers
982 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
985 // Format: SW ry, offset(rx) MIPS16e
986 // Purpose: Store Word (Extended)
987 // To store a word to memory.
990 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore;
993 // Format: SW rx, offset(sp) MIPS16e
994 // Purpose: Store Word rx (SP-Relative)
995 // To store an SP-relative word to memory.
997 def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore;
1001 // Format: XOR rx, ry MIPS16e
1003 // To do a bitwise logical XOR.
1005 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
1007 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
1008 let Predicates = [InMips16Mode];
1011 // Unary Arith/Logic
1013 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1014 Mips16Pat<(OpNode CPU16Regs:$r),
1017 def: ArithLogicU_pat<not, NotRxRy16>;
1018 def: ArithLogicU_pat<ineg, NegRxRy16>;
1020 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1021 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1022 (I CPU16Regs:$l, CPU16Regs:$r)>;
1024 def: ArithLogic16_pat<add, AdduRxRyRz16>;
1025 def: ArithLogic16_pat<and, AndRxRxRy16>;
1026 def: ArithLogic16_pat<mul, MultRxRyRz16>;
1027 def: ArithLogic16_pat<or, OrRxRxRy16>;
1028 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
1029 def: ArithLogic16_pat<xor, XorRxRxRy16>;
1031 // Arithmetic and logical instructions with 2 register operands.
1033 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1034 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1035 (I CPU16Regs:$in, imm_type:$imm)>;
1037 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
1038 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
1039 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
1040 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
1042 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1043 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1044 (I CPU16Regs:$r, CPU16Regs:$ra)>;
1046 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
1047 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
1048 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
1050 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1051 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
1053 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
1054 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
1055 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
1056 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
1057 def: LoadM16_pat<load, LwRxRyOffMemX16>;
1059 class StoreM16_pat<PatFrag OpNode, Instruction I> :
1060 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr),
1061 (I CPU16Regs:$r, addr16:$addr)>;
1063 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
1064 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
1065 def: StoreM16_pat<store, SwRxRyOffMemX16>;
1067 // Unconditional branch
1068 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
1069 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1070 let Predicates = [RelocPIC, InMips16Mode];
1075 (brind CPU16Regs:$rs),
1076 (JrcRx16 CPU16Regs:$rs)>;
1079 // Jump and Link (Call)
1080 let isCall=1, hasDelaySlot=0 in
1082 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
1083 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
1086 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
1087 hasExtraSrcRegAllocReq = 1 in
1088 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
1093 class SetCC_R16<PatFrag cond_op, Instruction I>:
1094 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1095 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1097 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1098 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1099 (I CPU16Regs:$rx, imm_type:$imm16)>;
1102 def: Mips16Pat<(i32 addr16:$addr),
1103 (AddiuRxRyOffMemX16 addr16:$addr)>;
1106 // Large (>16 bit) immediate loads
1107 def : Mips16Pat<(i32 imm:$imm),
1108 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16),
1109 (LiRxImmX16 (LO16 imm:$imm)))>;
1111 // Carry MipsPatterns
1112 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
1113 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1114 def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
1115 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1116 def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
1117 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
1120 // Some branch conditional patterns are not generated by llvm at this time.
1121 // Some are for seemingly arbitrary reasons not used: i.e. with signed number
1122 // comparison they are used and for unsigned a different pattern is used.
1123 // I am pushing upstream from the full mips16 port and it seemed that I needed
1124 // these earlier and the mips32 port has these but now I cannot create test
1125 // cases that use these patterns. While I sort this all out I will leave these
1126 // extra patterns commented out and if I can be sure they are really not used,
1127 // I will delete the code. I don't want to check the code in uncommented without
1128 // a valid test case. In some cases, the compiler is generating patterns with
1129 // setcc instead and earlier I had implemented setcc first so may have masked
1130 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
1131 // figure out how to enable the brcond patterns or else possibly new
1132 // combinations of of brcond and setcc.
1138 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1139 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1144 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1145 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1149 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1150 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16)
1154 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1157 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1158 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1165 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1166 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1170 // never called because compiler transforms a >= k to a > (k-1)
1172 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1173 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1180 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1181 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1185 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1186 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1193 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1194 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1201 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1202 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1206 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1207 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1211 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1212 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1216 // This needs to be there but I forget which code will generate it
1219 <(brcond CPU16Regs:$rx, bb:$targ16),
1220 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1229 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1230 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1237 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1238 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1246 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1247 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1250 def: UncondBranch16_pat<br, BimmX16>;
1253 def: Mips16Pat<(i32 immSExt16:$in),
1254 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
1256 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
1262 <(MipsDivRem CPU16Regs:$rx, CPU16Regs:$ry),
1263 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1269 <(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry),
1270 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1275 // if !(a < b) x = y
1277 def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1278 CPU16Regs:$x, CPU16Regs:$y),
1279 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1280 CPU16Regs:$a, CPU16Regs:$b)>;
1287 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1288 CPU16Regs:$x, CPU16Regs:$y),
1289 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
1290 CPU16Regs:$b, CPU16Regs:$a)>;
1295 // if !(a < b) x = y;
1298 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
1299 CPU16Regs:$x, CPU16Regs:$y),
1300 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1301 CPU16Regs:$a, CPU16Regs:$b)>;
1308 def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
1309 CPU16Regs:$x, CPU16Regs:$y),
1310 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
1311 CPU16Regs:$b, CPU16Regs:$a)>;
1315 // due to an llvm optimization, i don't think that this will ever
1316 // be used. This is transformed into x = (a > k-1)?x:y
1321 // (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1322 // CPU16Regs:$T, CPU16Regs:$F),
1323 // (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
1324 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1327 // (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
1328 // CPU16Regs:$T, CPU16Regs:$F),
1329 // (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
1330 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1335 // if !(a < k) x = y;
1338 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1339 CPU16Regs:$x, CPU16Regs:$y),
1340 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
1341 CPU16Regs:$a, immSExt16:$b)>;
1347 // x = (a <= b)? x : y
1351 def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
1352 CPU16Regs:$x, CPU16Regs:$y),
1353 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1354 CPU16Regs:$b, CPU16Regs:$a)>;
1358 // x = (a <= b)? x : y
1362 def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
1363 CPU16Regs:$x, CPU16Regs:$y),
1364 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1365 CPU16Regs:$b, CPU16Regs:$a)>;
1369 // x = (a == b)? x : y
1371 // if (a != b) x = y
1373 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
1374 CPU16Regs:$x, CPU16Regs:$y),
1375 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
1376 CPU16Regs:$b, CPU16Regs:$a)>;
1380 // x = (a == 0)? x : y
1382 // if (a != 0) x = y
1384 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
1385 CPU16Regs:$x, CPU16Regs:$y),
1386 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
1392 // x = (a == k)? x : y
1394 // if (a != k) x = y
1396 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
1397 CPU16Regs:$x, CPU16Regs:$y),
1398 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
1399 CPU16Regs:$a, immZExt16:$k)>;
1404 // x = (a != b)? x : y
1406 // if (a == b) x = y
1409 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1410 CPU16Regs:$x, CPU16Regs:$y),
1411 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
1412 CPU16Regs:$b, CPU16Regs:$a)>;
1416 // x = (a != 0)? x : y
1418 // if (a == 0) x = y
1420 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1421 CPU16Regs:$x, CPU16Regs:$y),
1422 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1430 def : Mips16Pat<(select CPU16Regs:$a,
1431 CPU16Regs:$x, CPU16Regs:$y),
1432 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1438 // x = (a != k)? x : y
1440 // if (a == k) x = y
1442 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1443 CPU16Regs:$x, CPU16Regs:$y),
1444 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
1445 CPU16Regs:$a, immZExt16:$k)>;
1448 // When writing C code to test setxx these patterns,
1449 // some will be transformed into
1450 // other things. So we test using C code but using -O3 and -O0
1455 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
1456 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
1459 <(seteq CPU16Regs:$lhs, 0),
1460 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
1468 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1469 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1473 // For constants, llvm transforms this to:
1474 // x > (k -1) and then reverses the operands to use setlt. So this pattern
1475 // is not used now by the compiler. (Presumably checking that k-1 does not
1476 // overflow). The compiler never uses this at a the current time, due to
1477 // other optimizations.
1480 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
1481 // (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
1482 // (LiRxImmX16 1))>;
1484 // This catches the x >= -32768 case by transforming it to x > -32769
1487 <(setgt CPU16Regs:$lhs, -32769),
1488 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
1497 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
1498 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1504 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
1505 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1510 def: SetCC_R16<setlt, SltCCRxRy16>;
1512 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
1518 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
1519 (SltuCCRxRy16 (LiRxImmX16 0),
1520 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1527 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1528 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1531 // this pattern will never be used because the compiler will transform
1532 // x >= k to x > (k - 1) and then use SLT
1535 // <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1536 // (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1537 // (LiRxImmX16 1))>;
1543 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1544 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1550 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1551 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1556 def: SetCC_R16<setult, SltuCCRxRy16>;
1558 def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1560 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1561 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
1565 def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
1566 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
1569 class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1570 Mips16Pat<(MipsWrapper RC:$gp, node:$in),
1571 (ADDiuOp RC:$gp, node:$in)>;
1574 def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>;
1575 def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
1577 def : Mips16Pat<(i32 (extloadi8 addr16:$src)),
1578 (LbuRxRyOffMemX16 addr16:$src)>;
1579 def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
1580 (LhuRxRyOffMemX16 addr16:$src)>;