1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
18 ComplexPattern<iPTR, 3, "selectAddr16", [frameindex], [SDNPWantParent]>;
22 def mem16 : Operand<i32> {
23 let PrintMethod = "printMemOperand";
24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16RegsPlusSP);
25 let EncoderMethod = "getMemEncoding";
28 def mem16_ea : Operand<i32> {
29 let PrintMethod = "printMemOperandEA";
30 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
31 let EncoderMethod = "getMemEncoding";
36 // I8 instruction format
39 class FI816_ins_base<bits<3> _func, string asmstr,
40 string asmstr2, InstrItinClass itin>:
41 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
45 class FI816_SP_ins<bits<3> _func, string asmstr,
47 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
50 // RI instruction format
54 class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
56 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
57 !strconcat(asmstr, asmstr2), [], itin>;
59 class FRI16_ins<bits<5> op, string asmstr,
61 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
63 class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2,
65 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
66 !strconcat(asmstr, asmstr2), [], itin>;
68 class FRI16R_ins<bits<5> op, string asmstr,
70 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
72 class F2RI16_ins<bits<5> _op, string asmstr,
74 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
75 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
76 let Constraints = "$rx_ = $rx";
79 class FRI16_B_ins<bits<5> _op, string asmstr,
81 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
82 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>;
84 // Compare a register and immediate and place result in CC
87 // EXT-CCRR Instruction format
89 class FEXT_CCRXI16_ins<string asmstr>:
90 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
91 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
93 let usesCustomInserter = 1;
96 // JAL and JALX instruction format
98 class FJAL16_ins<bits<1> _X, string asmstr,
100 FJAL16<_X, (outs), (ins simm20:$imm),
101 !strconcat(asmstr, "\t$imm\n\tnop"),[],
106 // EXT-I instruction format
108 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
109 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
110 !strconcat(asmstr, "\t$imm16"),[], itin>;
113 // EXT-I8 instruction format
116 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
117 string asmstr2, InstrItinClass itin>:
118 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
121 class FEXT_I816_ins<bits<3> _func, string asmstr,
122 InstrItinClass itin>:
123 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
125 class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
126 InstrItinClass itin>:
127 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>;
130 // Assembler formats in alphabetical order.
131 // Natural and pseudos are mixed together.
133 // Compare two registers and place result in CC
134 // Implicit use of T8
136 // CC-RR Instruction format
138 class FCCRR16_ins<string asmstr> :
139 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
140 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
142 let usesCustomInserter = 1;
146 // EXT-RI instruction format
149 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
150 InstrItinClass itin>:
151 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
152 !strconcat(asmstr, asmstr2), [], itin>;
154 class FEXT_RI16_ins<bits<5> _op, string asmstr,
155 InstrItinClass itin>:
156 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
158 class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2,
159 InstrItinClass itin>:
160 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm),
161 !strconcat(asmstr, asmstr2), [], itin>;
163 class FEXT_RI16R_ins<bits<5> _op, string asmstr,
164 InstrItinClass itin>:
165 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
167 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
168 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
170 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
171 InstrItinClass itin>:
172 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
173 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
175 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
176 InstrItinClass itin>:
177 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
178 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
179 let Constraints = "$rx_ = $rx";
183 // this has an explicit sp argument that we ignore to work around a problem
185 class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
186 InstrItinClass itin>:
187 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
188 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
190 class FEXT_RI16_SP_Store_explicit_ins<bits<5> _op, string asmstr,
191 InstrItinClass itin>:
192 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm),
193 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
196 // EXT-RRI instruction format
199 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
200 InstrItinClass itin>:
201 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
202 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
204 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
205 InstrItinClass itin>:
206 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
207 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
211 // EXT-RRI-A instruction format
214 class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
215 InstrItinClass itin>:
216 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
217 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
220 // EXT-SHIFT instruction format
222 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
223 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa),
224 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
229 class FEXT_T8I816_ins<string asmstr, string asmstr2>:
231 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
232 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
233 !strconcat(asmstr, "\t$imm"))),[]> {
235 let usesCustomInserter = 1;
241 class FEXT_T8I8I16_ins<string asmstr, string asmstr2>:
243 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
244 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
245 !strconcat(asmstr, "\t$targ"))), []> {
247 let usesCustomInserter = 1;
253 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
255 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
256 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32),
257 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
260 // I8_MOV32R instruction format (used only by MOV32R instruction)
263 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
264 FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz),
265 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
268 // This are pseudo formats for multiply
269 // This first one can be changed to non pseudo now.
273 class FMULT16_ins<string asmstr, InstrItinClass itin> :
274 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
275 !strconcat(asmstr, "\t$rx, $ry"), []>;
280 class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
281 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
282 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
287 // RR-type instruction format
290 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
291 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
292 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
295 class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> :
296 FRRBreak16<(outs), (ins), asmstr, [], itin> {
300 class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> :
301 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
302 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
305 class FRRTR16_ins<string asmstr> :
306 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
307 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
310 // maybe refactor but need a $zero as a dummy first parameter
312 class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
313 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
314 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
316 class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
317 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
318 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
321 class FRR16_M_ins<bits<5> f, string asmstr,
322 InstrItinClass itin> :
323 FRR16<f, (outs CPU16Regs:$rx), (ins),
324 !strconcat(asmstr, "\t$rx"), [], itin>;
326 class FRxRxRy16_ins<bits<5> f, string asmstr,
327 InstrItinClass itin> :
328 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
329 !strconcat(asmstr, "\t$rz, $ry"),
331 let Constraints = "$rx = $rz";
335 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
336 string asmstr, InstrItinClass itin>:
337 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
341 class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
342 string asmstr, InstrItinClass itin>:
343 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
344 !strconcat(asmstr, "\t $rx"), [], itin> ;
347 <bits<5> _funct, bits<3> _subfunc,
348 string asmstr, InstrItinClass itin>:
349 FRR_SF16<_funct, _subfunc, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_),
350 !strconcat(asmstr, "\t $rx"),
352 let Constraints = "$rx_ = $rx";
355 // RRR-type instruction format
358 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
359 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
360 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
363 // These Sel patterns support the generation of conditional move
364 // pseudo instructions.
366 // The nomenclature uses the components making up the pseudo and may
367 // be a bit counter intuitive when compared with the end result we seek.
368 // For example using a bqez in the example directly below results in the
369 // conditional move being done if the tested register is not zero.
370 // I considered in easier to check by keeping the pseudo consistent with
371 // it's components but it could have been done differently.
373 // The simplest case is when can test and operand directly and do the
374 // conditional move based on a simple mips16 conditional
375 // branch instruction.
377 // if $op == beqz or bnez:
382 // if $op == beqz, then if $rt != 0, then the conditional assignment
383 // $rd = $rs is done.
385 // if $op == bnez, then if $rt == 0, then the conditional assignment
386 // $rd = $rs is done.
388 // So this pseudo class only has one operand, i.e. op
390 class Sel<string op>:
391 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
393 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> {
394 //let isCodeGenOnly=1;
395 let Constraints = "$rd = $rd_";
396 let usesCustomInserter = 1;
400 // The next two instruction classes allow for an operand which tests
401 // two operands and returns a value in register T8 and
402 //then does a conditional branch based on the value of T8
405 // op2 can be cmpi or slti/sltiu
406 // op1 can bteqz or btnez
407 // the operands for op2 are a register and a signed constant
409 // $op2 $t, $imm ;test register t and branch conditionally
410 // $op1 .+4 ;op1 is a conditional branch
414 class SeliT<string op1, string op2>:
415 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
416 CPU16Regs:$rl, simm16:$imm),
418 !strconcat("\t$rl, $imm\n\t",
419 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
421 let Constraints = "$rd = $rd_";
422 let usesCustomInserter = 1;
426 // op2 can be cmp or slt/sltu
427 // op1 can be bteqz or btnez
428 // the operands for op2 are two registers
429 // op1 is a conditional branch
432 // $op2 $rl, $rr ;test registers rl,rr
433 // $op1 .+4 ;op2 is a conditional branch
437 class SelT<string op1, string op2>:
438 MipsPseudo16<(outs CPU16Regs:$rd_),
439 (ins CPU16Regs:$rd, CPU16Regs:$rs,
440 CPU16Regs:$rl, CPU16Regs:$rr),
442 !strconcat("\t$rl, $rr\n\t",
443 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
445 let Constraints = "$rd = $rd_";
446 let usesCustomInserter = 1;
452 def imm32: Operand<i32>;
455 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
458 MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm),
459 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
463 // Some general instruction class info
467 class ArithLogic16Defs<bit isCom=0> {
469 bit isCommutable = isCom;
470 bit isReMaterializable = 1;
471 bit neverHasSideEffects = 1;
476 bit isTerminator = 1;
482 bit isTerminator = 1;
495 // Format: ADDIU rx, immediate MIPS16e
496 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
497 // To add a constant to a 32-bit integer.
499 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
501 def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>,
502 ArithLogic16Defs<0> {
503 let AddedComplexity = 5;
505 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
506 ArithLogic16Defs<0> {
507 let isCodeGenOnly = 1;
510 def AddiuRxRyOffMemX16:
511 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>;
515 // Format: ADDIU rx, pc, immediate MIPS16e
516 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
517 // To add a constant to the program counter.
519 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
522 // Format: ADDIU sp, immediate MIPS16e
523 // Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
524 // To add a constant to the stack pointer.
527 : FI816_SP_ins<0b011, "addiu", IIAlu> {
530 let AddedComplexity = 5;
534 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
540 // Format: ADDU rz, rx, ry MIPS16e
541 // Purpose: Add Unsigned Word (3-Operand)
542 // To add 32-bit integers.
545 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
548 // Format: AND rx, ry MIPS16e
550 // To do a bitwise logical AND.
552 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
556 // Format: BEQZ rx, offset MIPS16e
557 // Purpose: Branch on Equal to Zero
558 // To test a GPR then do a PC-relative conditional branch.
560 def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
564 // Format: BEQZ rx, offset MIPS16e
565 // Purpose: Branch on Equal to Zero (Extended)
566 // To test a GPR then do a PC-relative conditional branch.
568 def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
570 // Format: B offset MIPS16e
571 // Purpose: Unconditional Branch
572 // To do an unconditional PC-relative branch.
574 def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
577 // Format: BNEZ rx, offset MIPS16e
578 // Purpose: Branch on Not Equal to Zero
579 // To test a GPR then do a PC-relative conditional branch.
581 def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
584 // Format: BNEZ rx, offset MIPS16e
585 // Purpose: Branch on Not Equal to Zero (Extended)
586 // To test a GPR then do a PC-relative conditional branch.
588 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
592 //Format: BREAK immediate
593 // Purpose: Breakpoint
594 // To cause a Breakpoint exception.
596 def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>;
598 // Format: BTEQZ offset MIPS16e
599 // Purpose: Branch on T Equal to Zero (Extended)
600 // To test special register T then do a PC-relative conditional branch.
602 def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
606 def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16;
608 def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">,
611 def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16;
613 def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;
615 def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16;
617 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
621 // Format: BTNEZ offset MIPS16e
622 // Purpose: Branch on T Not Equal to Zero (Extended)
623 // To test special register T then do a PC-relative conditional branch.
625 def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 {
629 def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16;
631 def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16;
633 def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16;
635 def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;
637 def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16;
639 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
643 // Format: CMP rx, ry MIPS16e
645 // To compare the contents of two GPRs.
647 def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> {
652 // Format: CMPI rx, immediate MIPS16e
653 // Purpose: Compare Immediate
654 // To compare a constant with the contents of a GPR.
656 def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> {
661 // Format: CMPI rx, immediate MIPS16e
662 // Purpose: Compare Immediate (Extended)
663 // To compare a constant with the contents of a GPR.
665 def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> {
671 // Format: DIV rx, ry MIPS16e
672 // Purpose: Divide Word
673 // To divide 32-bit signed integers.
675 def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
676 let Defs = [HI0, LO0];
680 // Format: DIVU rx, ry MIPS16e
681 // Purpose: Divide Unsigned Word
682 // To divide 32-bit unsigned integers.
684 def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
685 let Defs = [HI0, LO0];
688 // Format: JAL target MIPS16e
689 // Purpose: Jump and Link
690 // To execute a procedure call within the current 256 MB-aligned
691 // region and preserve the current ISA.
694 def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
695 let hasDelaySlot = 0; // not true, but we add the nop for now
700 // Format: JR ra MIPS16e
701 // Purpose: Jump Register Through Register ra
702 // To execute a branch to the instruction address in the return
706 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
708 let isIndirectBranch = 1;
709 let hasDelaySlot = 1;
714 def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> {
716 let isIndirectBranch = 1;
721 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
723 let isIndirectBranch = 1;
728 // Format: LB ry, offset(rx) MIPS16e
729 // Purpose: Load Byte (Extended)
730 // To load a byte from memory as a signed value.
732 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{
733 let isCodeGenOnly = 1;
737 // Format: LBU ry, offset(rx) MIPS16e
738 // Purpose: Load Byte Unsigned (Extended)
739 // To load a byte from memory as a unsigned value.
741 def LbuRxRyOffMemX16:
742 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad {
743 let isCodeGenOnly = 1;
747 // Format: LH ry, offset(rx) MIPS16e
748 // Purpose: Load Halfword signed (Extended)
749 // To load a halfword from memory as a signed value.
751 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{
752 let isCodeGenOnly = 1;
756 // Format: LHU ry, offset(rx) MIPS16e
757 // Purpose: Load Halfword unsigned (Extended)
758 // To load a halfword from memory as an unsigned value.
760 def LhuRxRyOffMemX16:
761 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad {
762 let isCodeGenOnly = 1;
766 // Format: LI rx, immediate MIPS16e
767 // Purpose: Load Immediate
768 // To load a constant into a GPR.
770 def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>;
773 // Format: LI rx, immediate MIPS16e
774 // Purpose: Load Immediate (Extended)
775 // To load a constant into a GPR.
777 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
779 def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIAlu> {
780 let isCodeGenOnly = 1;
784 // Format: LW ry, offset(rx) MIPS16e
785 // Purpose: Load Word (Extended)
786 // To load a word from memory as a signed value.
788 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{
789 let isCodeGenOnly = 1;
792 // Format: LW rx, offset(sp) MIPS16e
793 // Purpose: Load Word (SP-Relative, Extended)
794 // To load an SP-relative word from memory as a signed value.
796 def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{
801 // Format: MOVE r32, rz MIPS16e
803 // To move the contents of a GPR to a GPR.
805 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
808 // Format: MOVE ry, r32 MIPS16e
810 // To move the contents of a GPR to a GPR.
812 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
815 // Format: MFHI rx MIPS16e
816 // Purpose: Move From HI Register
817 // To copy the special purpose HI register to a GPR.
819 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
821 let neverHasSideEffects = 1;
825 // Format: MFLO rx MIPS16e
826 // Purpose: Move From LO Register
827 // To copy the special purpose LO register to a GPR.
829 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
831 let neverHasSideEffects = 1;
835 // Pseudo Instruction for mult
837 def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
838 let isCommutable = 1;
839 let neverHasSideEffects = 1;
840 let Defs = [HI0, LO0];
843 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
844 let isCommutable = 1;
845 let neverHasSideEffects = 1;
846 let Defs = [HI0, LO0];
850 // Format: MULT rx, ry MIPS16e
851 // Purpose: Multiply Word
852 // To multiply 32-bit signed integers.
854 def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
855 let isCommutable = 1;
856 let neverHasSideEffects = 1;
857 let Defs = [HI0, LO0];
861 // Format: MULTU rx, ry MIPS16e
862 // Purpose: Multiply Unsigned Word
863 // To multiply 32-bit unsigned integers.
865 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
866 let isCommutable = 1;
867 let neverHasSideEffects = 1;
868 let Defs = [HI0, LO0];
872 // Format: NEG rx, ry MIPS16e
874 // To negate an integer value.
876 def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
879 // Format: NOT rx, ry MIPS16e
881 // To complement an integer value
883 def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
886 // Format: OR rx, ry MIPS16e
888 // To do a bitwise logical OR.
890 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
893 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
894 // (All args are optional) MIPS16e
895 // Purpose: Restore Registers and Deallocate Stack Frame
896 // To deallocate a stack frame before exit from a subroutine,
897 // restoring return address and static registers, and adjusting
901 // fixed form for restoring RA and the frame
902 // for direct object emitter, encoding needs to be adjusted for the
905 let ra=1, s=0,s0=1,s1=1 in
907 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
908 "restore\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IILoad >, MayLoad {
909 let isCodeGenOnly = 1;
910 let Defs = [S0, S1, S2, RA, SP];
914 // Use Restore to increment SP since SP is not a Mip 16 register, this
915 // is an easy way to do that which does not require a register.
917 let ra=0, s=0,s0=0,s1=0 in
919 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
920 "restore\t$frame_size", [], IILoad >, MayLoad {
921 let isCodeGenOnly = 1;
927 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
929 // Purpose: Save Registers and Set Up Stack Frame
930 // To set up a stack frame on entry to a subroutine,
931 // saving return address and static registers, and adjusting stack
933 let ra=1, s=1,s0=1,s1=1 in
935 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
936 "save\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IIStore >, MayStore {
937 let isCodeGenOnly = 1;
938 let Uses = [RA, SP, S0, S1, S2];
943 // Use Save to decrement the SP by a constant since SP is not
944 // a Mips16 register.
946 let ra=0, s=0,s0=0,s1=0 in
948 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
949 "save\t$frame_size", [], IIStore >, MayStore {
950 let isCodeGenOnly = 1;
955 // Format: SB ry, offset(rx) MIPS16e
956 // Purpose: Store Byte (Extended)
957 // To store a byte to memory.
960 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
963 // Format: SEB rx MIPS16e
964 // Purpose: Sign-Extend Byte
965 // Sign-extend least significant byte in register rx.
968 : FRR_SF16_ins<0b10001, 0b100, "seb", IIAlu>;
971 // Format: SEH rx MIPS16e
972 // Purpose: Sign-Extend Halfword
973 // Sign-extend least significant word in register rx.
976 : FRR_SF16_ins<0b10001, 0b101, "seh", IIAlu>;
979 // The Sel(T) instructions are pseudos
980 // T means that they use T8 implicitly.
983 // Format: SelBeqZ rd, rs, rt
984 // Purpose: if rt==0, do nothing
987 def SelBeqZ: Sel<"beqz">;
990 // Format: SelTBteqZCmp rd, rs, rl, rr
991 // Purpose: b = Cmp rl, rr.
992 // If b==0 then do nothing.
993 // if b!=0 then rd = rs
995 def SelTBteqZCmp: SelT<"bteqz", "cmp">;
998 // Format: SelTBteqZCmpi rd, rs, rl, rr
999 // Purpose: b = Cmpi rl, imm.
1000 // If b==0 then do nothing.
1001 // if b!=0 then rd = rs
1003 def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">;
1006 // Format: SelTBteqZSlt rd, rs, rl, rr
1007 // Purpose: b = Slt rl, rr.
1008 // If b==0 then do nothing.
1009 // if b!=0 then rd = rs
1011 def SelTBteqZSlt: SelT<"bteqz", "slt">;
1014 // Format: SelTBteqZSlti rd, rs, rl, rr
1015 // Purpose: b = Slti rl, imm.
1016 // If b==0 then do nothing.
1017 // if b!=0 then rd = rs
1019 def SelTBteqZSlti: SeliT<"bteqz", "slti">;
1022 // Format: SelTBteqZSltu rd, rs, rl, rr
1023 // Purpose: b = Sltu rl, rr.
1024 // If b==0 then do nothing.
1025 // if b!=0 then rd = rs
1027 def SelTBteqZSltu: SelT<"bteqz", "sltu">;
1030 // Format: SelTBteqZSltiu rd, rs, rl, rr
1031 // Purpose: b = Sltiu rl, imm.
1032 // If b==0 then do nothing.
1033 // if b!=0 then rd = rs
1035 def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">;
1038 // Format: SelBnez rd, rs, rt
1039 // Purpose: if rt!=0, do nothing
1042 def SelBneZ: Sel<"bnez">;
1045 // Format: SelTBtneZCmp rd, rs, rl, rr
1046 // Purpose: b = Cmp rl, rr.
1047 // If b!=0 then do nothing.
1048 // if b0=0 then rd = rs
1050 def SelTBtneZCmp: SelT<"btnez", "cmp">;
1053 // Format: SelTBtnezCmpi rd, rs, rl, rr
1054 // Purpose: b = Cmpi rl, imm.
1055 // If b!=0 then do nothing.
1056 // if b==0 then rd = rs
1058 def SelTBtneZCmpi: SeliT<"btnez", "cmpi">;
1061 // Format: SelTBtneZSlt rd, rs, rl, rr
1062 // Purpose: b = Slt rl, rr.
1063 // If b!=0 then do nothing.
1064 // if b==0 then rd = rs
1066 def SelTBtneZSlt: SelT<"btnez", "slt">;
1069 // Format: SelTBtneZSlti rd, rs, rl, rr
1070 // Purpose: b = Slti rl, imm.
1071 // If b!=0 then do nothing.
1072 // if b==0 then rd = rs
1074 def SelTBtneZSlti: SeliT<"btnez", "slti">;
1077 // Format: SelTBtneZSltu rd, rs, rl, rr
1078 // Purpose: b = Sltu rl, rr.
1079 // If b!=0 then do nothing.
1080 // if b==0 then rd = rs
1082 def SelTBtneZSltu: SelT<"btnez", "sltu">;
1085 // Format: SelTBtneZSltiu rd, rs, rl, rr
1086 // Purpose: b = Slti rl, imm.
1087 // If b!=0 then do nothing.
1088 // if b==0 then rd = rs
1090 def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
1093 // Format: SH ry, offset(rx) MIPS16e
1094 // Purpose: Store Halfword (Extended)
1095 // To store a halfword to memory.
1097 def ShRxRyOffMemX16:
1098 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore;
1101 // Format: SLL rx, ry, sa MIPS16e
1102 // Purpose: Shift Word Left Logical (Extended)
1103 // To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
1105 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
1108 // Format: SLLV ry, rx MIPS16e
1109 // Purpose: Shift Word Left Logical Variable
1110 // To execute a left-shift of a word by a variable number of bits.
1112 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
1114 // Format: SLTI rx, immediate MIPS16e
1115 // Purpose: Set on Less Than Immediate
1116 // To record the result of a less-than comparison with a constant.
1119 def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> {
1124 // Format: SLTI rx, immediate MIPS16e
1125 // Purpose: Set on Less Than Immediate (Extended)
1126 // To record the result of a less-than comparison with a constant.
1129 def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> {
1133 def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
1135 // Format: SLTIU rx, immediate MIPS16e
1136 // Purpose: Set on Less Than Immediate Unsigned
1137 // To record the result of a less-than comparison with a constant.
1140 def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> {
1145 // Format: SLTI rx, immediate MIPS16e
1146 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1147 // To record the result of a less-than comparison with a constant.
1150 def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> {
1154 // Format: SLTIU rx, immediate MIPS16e
1155 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1156 // To record the result of a less-than comparison with a constant.
1158 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
1161 // Format: SLT rx, ry MIPS16e
1162 // Purpose: Set on Less Than
1163 // To record the result of a less-than comparison.
1165 def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{
1169 def SltCCRxRy16: FCCRR16_ins<"slt">;
1171 // Format: SLTU rx, ry MIPS16e
1172 // Purpose: Set on Less Than Unsigned
1173 // To record the result of an unsigned less-than comparison.
1175 def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{
1179 def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
1180 let isCodeGenOnly=1;
1185 def SltuCCRxRy16: FCCRR16_ins<"sltu">;
1187 // Format: SRAV ry, rx MIPS16e
1188 // Purpose: Shift Word Right Arithmetic Variable
1189 // To execute an arithmetic right-shift of a word by a variable
1192 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
1196 // Format: SRA rx, ry, sa MIPS16e
1197 // Purpose: Shift Word Right Arithmetic (Extended)
1198 // To execute an arithmetic right-shift of a word by a fixed
1199 // number of bits—1 to 8 bits.
1201 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
1205 // Format: SRLV ry, rx MIPS16e
1206 // Purpose: Shift Word Right Logical Variable
1207 // To execute a logical right-shift of a word by a variable
1210 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
1214 // Format: SRL rx, ry, sa MIPS16e
1215 // Purpose: Shift Word Right Logical (Extended)
1216 // To execute a logical right-shift of a word by a fixed
1217 // number of bits—1 to 31 bits.
1219 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
1222 // Format: SUBU rz, rx, ry MIPS16e
1223 // Purpose: Subtract Unsigned Word
1224 // To subtract 32-bit integers
1226 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
1229 // Format: SW ry, offset(rx) MIPS16e
1230 // Purpose: Store Word (Extended)
1231 // To store a word to memory.
1233 def SwRxRyOffMemX16:
1234 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore;
1237 // Format: SW rx, offset(sp) MIPS16e
1238 // Purpose: Store Word rx (SP-Relative)
1239 // To store an SP-relative word to memory.
1241 def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins
1242 <0b11010, "sw", IIStore>, MayStore;
1246 // Format: XOR rx, ry MIPS16e
1248 // To do a bitwise logical XOR.
1250 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
1252 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
1253 let Predicates = [InMips16Mode];
1256 // Unary Arith/Logic
1258 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1259 Mips16Pat<(OpNode CPU16Regs:$r),
1262 def: ArithLogicU_pat<not, NotRxRy16>;
1263 def: ArithLogicU_pat<ineg, NegRxRy16>;
1265 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1266 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1267 (I CPU16Regs:$l, CPU16Regs:$r)>;
1269 def: ArithLogic16_pat<add, AdduRxRyRz16>;
1270 def: ArithLogic16_pat<and, AndRxRxRy16>;
1271 def: ArithLogic16_pat<mul, MultRxRyRz16>;
1272 def: ArithLogic16_pat<or, OrRxRxRy16>;
1273 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
1274 def: ArithLogic16_pat<xor, XorRxRxRy16>;
1276 // Arithmetic and logical instructions with 2 register operands.
1278 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1279 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1280 (I CPU16Regs:$in, imm_type:$imm)>;
1282 def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>;
1283 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
1284 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
1285 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
1286 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
1288 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1289 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1290 (I CPU16Regs:$r, CPU16Regs:$ra)>;
1292 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
1293 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
1294 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
1296 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1297 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
1299 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
1300 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
1301 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
1302 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
1303 def: LoadM16_pat<load, LwRxRyOffMemX16>;
1305 class StoreM16_pat<PatFrag OpNode, Instruction I> :
1306 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr),
1307 (I CPU16Regs:$r, addr16:$addr)>;
1309 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
1310 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
1311 def: StoreM16_pat<store, SwRxRyOffMemX16>;
1313 // Unconditional branch
1314 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
1315 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1316 let Predicates = [InMips16Mode];
1319 def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1320 (Jal16 tglobaladdr:$dst)>;
1322 def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)),
1323 (Jal16 texternalsym:$dst)>;
1327 (brind CPU16Regs:$rs),
1328 (JrcRx16 CPU16Regs:$rs)>;
1330 // Jump and Link (Call)
1331 let isCall=1, hasDelaySlot=0 in
1333 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
1334 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
1337 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
1338 hasExtraSrcRegAllocReq = 1 in
1339 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
1344 class SetCC_R16<PatFrag cond_op, Instruction I>:
1345 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1346 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1348 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1349 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1350 (I CPU16Regs:$rx, imm_type:$imm16)>;
1353 def: Mips16Pat<(i32 addr16:$addr),
1354 (AddiuRxRyOffMemX16 addr16:$addr)>;
1357 // Large (>16 bit) immediate loads
1358 def : Mips16Pat<(i32 imm:$imm),
1359 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16),
1360 (LiRxImmX16 (LO16 imm:$imm)))>;
1362 // Carry MipsPatterns
1363 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
1364 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1365 def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
1366 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1367 def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
1368 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
1371 // Some branch conditional patterns are not generated by llvm at this time.
1372 // Some are for seemingly arbitrary reasons not used: i.e. with signed number
1373 // comparison they are used and for unsigned a different pattern is used.
1374 // I am pushing upstream from the full mips16 port and it seemed that I needed
1375 // these earlier and the mips32 port has these but now I cannot create test
1376 // cases that use these patterns. While I sort this all out I will leave these
1377 // extra patterns commented out and if I can be sure they are really not used,
1378 // I will delete the code. I don't want to check the code in uncommented without
1379 // a valid test case. In some cases, the compiler is generating patterns with
1380 // setcc instead and earlier I had implemented setcc first so may have masked
1381 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
1382 // figure out how to enable the brcond patterns or else possibly new
1383 // combinations of of brcond and setcc.
1389 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1390 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1395 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1396 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1400 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1401 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16)
1405 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1408 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1409 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1416 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1417 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1421 // never called because compiler transforms a >= k to a > (k-1)
1423 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1424 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1431 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1432 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1436 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1437 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1444 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1445 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1452 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1453 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1457 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1458 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1462 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1463 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1467 // This needs to be there but I forget which code will generate it
1470 <(brcond CPU16Regs:$rx, bb:$targ16),
1471 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1480 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1481 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1488 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1489 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1497 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1498 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1501 def: UncondBranch16_pat<br, BimmX16>;
1504 def: Mips16Pat<(i32 immSExt16:$in),
1505 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
1507 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
1513 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry),
1514 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1520 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry),
1521 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1526 // if !(a < b) x = y
1528 def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1529 CPU16Regs:$x, CPU16Regs:$y),
1530 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1531 CPU16Regs:$a, CPU16Regs:$b)>;
1538 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1539 CPU16Regs:$x, CPU16Regs:$y),
1540 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
1541 CPU16Regs:$b, CPU16Regs:$a)>;
1546 // if !(a < b) x = y;
1549 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
1550 CPU16Regs:$x, CPU16Regs:$y),
1551 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1552 CPU16Regs:$a, CPU16Regs:$b)>;
1559 def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
1560 CPU16Regs:$x, CPU16Regs:$y),
1561 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
1562 CPU16Regs:$b, CPU16Regs:$a)>;
1566 // due to an llvm optimization, i don't think that this will ever
1567 // be used. This is transformed into x = (a > k-1)?x:y
1572 // (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1573 // CPU16Regs:$T, CPU16Regs:$F),
1574 // (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
1575 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1578 // (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
1579 // CPU16Regs:$T, CPU16Regs:$F),
1580 // (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
1581 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1586 // if !(a < k) x = y;
1589 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1590 CPU16Regs:$x, CPU16Regs:$y),
1591 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
1592 CPU16Regs:$a, immSExt16:$b)>;
1598 // x = (a <= b)? x : y
1602 def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
1603 CPU16Regs:$x, CPU16Regs:$y),
1604 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1605 CPU16Regs:$b, CPU16Regs:$a)>;
1609 // x = (a <= b)? x : y
1613 def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
1614 CPU16Regs:$x, CPU16Regs:$y),
1615 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1616 CPU16Regs:$b, CPU16Regs:$a)>;
1620 // x = (a == b)? x : y
1622 // if (a != b) x = y
1624 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
1625 CPU16Regs:$x, CPU16Regs:$y),
1626 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
1627 CPU16Regs:$b, CPU16Regs:$a)>;
1631 // x = (a == 0)? x : y
1633 // if (a != 0) x = y
1635 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
1636 CPU16Regs:$x, CPU16Regs:$y),
1637 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
1643 // x = (a == k)? x : y
1645 // if (a != k) x = y
1647 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
1648 CPU16Regs:$x, CPU16Regs:$y),
1649 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
1650 CPU16Regs:$a, immZExt16:$k)>;
1655 // x = (a != b)? x : y
1657 // if (a == b) x = y
1660 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1661 CPU16Regs:$x, CPU16Regs:$y),
1662 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
1663 CPU16Regs:$b, CPU16Regs:$a)>;
1667 // x = (a != 0)? x : y
1669 // if (a == 0) x = y
1671 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1672 CPU16Regs:$x, CPU16Regs:$y),
1673 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1681 def : Mips16Pat<(select CPU16Regs:$a,
1682 CPU16Regs:$x, CPU16Regs:$y),
1683 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1689 // x = (a != k)? x : y
1691 // if (a == k) x = y
1693 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1694 CPU16Regs:$x, CPU16Regs:$y),
1695 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
1696 CPU16Regs:$a, immZExt16:$k)>;
1699 // When writing C code to test setxx these patterns,
1700 // some will be transformed into
1701 // other things. So we test using C code but using -O3 and -O0
1706 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
1707 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
1710 <(seteq CPU16Regs:$lhs, 0),
1711 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
1719 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1720 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1724 // For constants, llvm transforms this to:
1725 // x > (k -1) and then reverses the operands to use setlt. So this pattern
1726 // is not used now by the compiler. (Presumably checking that k-1 does not
1727 // overflow). The compiler never uses this at a the current time, due to
1728 // other optimizations.
1731 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
1732 // (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
1733 // (LiRxImmX16 1))>;
1735 // This catches the x >= -32768 case by transforming it to x > -32769
1738 <(setgt CPU16Regs:$lhs, -32769),
1739 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
1748 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
1749 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1755 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
1756 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>;
1761 def: SetCC_R16<setlt, SltCCRxRy16>;
1763 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
1769 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
1770 (SltuCCRxRy16 (LiRxImmX16 0),
1771 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1778 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1779 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1782 // this pattern will never be used because the compiler will transform
1783 // x >= k to x > (k - 1) and then use SLT
1786 // <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1787 // (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1788 // (LiRxImmX16 1))>;
1794 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1795 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1801 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1802 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1807 def: SetCC_R16<setult, SltuCCRxRy16>;
1809 def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1811 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1812 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
1815 def : Mips16Pat<(MipsHi tblockaddress:$in),
1816 (SllX16 (LiRxImmX16 tblockaddress:$in), 16)>;
1817 def : Mips16Pat<(MipsHi tglobaladdr:$in),
1818 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>;
1819 def : Mips16Pat<(MipsHi tjumptable:$in),
1820 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>;
1821 def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
1822 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
1824 def : Mips16Pat<(MipsLo tblockaddress:$in), (LiRxImmX16 tblockaddress:$in)>;
1827 class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1828 Mips16Pat<(MipsWrapper RC:$gp, node:$in),
1829 (ADDiuOp RC:$gp, node:$in)>;
1832 def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>;
1833 def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
1835 def : Mips16Pat<(i32 (extloadi8 addr16:$src)),
1836 (LbuRxRyOffMemX16 addr16:$src)>;
1837 def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
1838 (LhuRxRyOffMemX16 addr16:$src)>;
1840 def: Mips16Pat<(trap), (Break16)>;
1842 def : Mips16Pat<(sext_inreg CPU16Regs:$val, i8),
1843 (SebRx16 CPU16Regs:$val)>;
1845 def : Mips16Pat<(sext_inreg CPU16Regs:$val, i16),
1846 (SehRx16 CPU16Regs:$val)>;
1850 (outs CPU16Regs:$rh, CPU16Regs:$rl),
1851 (ins simm16:$immHi, simm16:$immLo),
1852 ".align 2\n\tli\t$rh, $immHi\n\taddiu\t$rl, $$pc, $immLo\n ",[]> ;