1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
18 ComplexPattern<iPTR, 3, "selectAddr16", [frameindex], [SDNPWantParent]>;
22 def mem16 : Operand<i32> {
23 let PrintMethod = "printMemOperand";
24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16RegsPlusSP);
25 let EncoderMethod = "getMemEncoding";
28 def mem16_ea : Operand<i32> {
29 let PrintMethod = "printMemOperandEA";
30 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
31 let EncoderMethod = "getMemEncoding";
35 // I-type instruction format
37 // this is only used by bimm. the actual assembly value is a 12 bit signed
40 class FI16_ins<bits<5> op, string asmstr, InstrItinClass itin>:
41 FI16<op, (outs), (ins brtarget:$imm16),
42 !strconcat(asmstr, "\t$imm16 # 16 bit inst"), [], itin>;
46 // I8 instruction format
49 class FI816_ins_base<bits<3> _func, string asmstr,
50 string asmstr2, InstrItinClass itin>:
51 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
54 class FI816_ins<bits<3> _func, string asmstr,
56 FI816_ins_base<_func, asmstr, "\t$imm # 16 bit inst", itin>;
58 class FI816_SP_ins<bits<3> _func, string asmstr,
60 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
63 // RI instruction format
67 class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
69 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
70 !strconcat(asmstr, asmstr2), [], itin>;
72 class FRI16_ins<bits<5> op, string asmstr,
74 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
76 class FRI16_TCP_ins<bits<5> _op, string asmstr,
78 FRI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size),
79 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin>;
81 class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2,
83 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
84 !strconcat(asmstr, asmstr2), [], itin>;
86 class FRI16R_ins<bits<5> op, string asmstr,
88 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
90 class F2RI16_ins<bits<5> _op, string asmstr,
92 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
93 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
94 let Constraints = "$rx_ = $rx";
97 class FRI16_B_ins<bits<5> _op, string asmstr,
99 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
100 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>;
102 // Compare a register and immediate and place result in CC
103 // Implicit use of T8
105 // EXT-CCRR Instruction format
107 class FEXT_CCRXI16_ins<string asmstr>:
108 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
109 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
111 let usesCustomInserter = 1;
114 // JAL and JALX instruction format
116 class FJAL16_ins<bits<1> _X, string asmstr,
117 InstrItinClass itin>:
118 FJAL16<_X, (outs), (ins simm20:$imm),
119 !strconcat(asmstr, "\t$imm\n\tnop"),[],
124 class FJALB16_ins<bits<1> _X, string asmstr,
125 InstrItinClass itin>:
126 FJAL16<_X, (outs), (ins simm20:$imm),
127 !strconcat(asmstr, "\t$imm\t# branch\n\tnop"),[],
133 // EXT-I instruction format
135 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
136 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
137 !strconcat(asmstr, "\t$imm16"),[], itin>;
140 // EXT-I8 instruction format
143 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
144 string asmstr2, InstrItinClass itin>:
145 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
148 class FEXT_I816_ins<bits<3> _func, string asmstr,
149 InstrItinClass itin>:
150 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
152 class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
153 InstrItinClass itin>:
154 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>;
157 // Assembler formats in alphabetical order.
158 // Natural and pseudos are mixed together.
160 // Compare two registers and place result in CC
161 // Implicit use of T8
163 // CC-RR Instruction format
165 class FCCRR16_ins<string asmstr> :
166 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
167 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
169 let usesCustomInserter = 1;
173 // EXT-RI instruction format
176 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
177 InstrItinClass itin>:
178 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
179 !strconcat(asmstr, asmstr2), [], itin>;
181 class FEXT_RI16_ins<bits<5> _op, string asmstr,
182 InstrItinClass itin>:
183 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
185 class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2,
186 InstrItinClass itin>:
187 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm),
188 !strconcat(asmstr, asmstr2), [], itin>;
190 class FEXT_RI16R_ins<bits<5> _op, string asmstr,
191 InstrItinClass itin>:
192 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
194 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
195 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
197 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
198 InstrItinClass itin>:
199 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
200 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
202 class FEXT_RI16_TCP_ins<bits<5> _op, string asmstr,
203 InstrItinClass itin>:
204 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size),
205 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
207 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
208 InstrItinClass itin>:
209 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
210 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
211 let Constraints = "$rx_ = $rx";
215 // this has an explicit sp argument that we ignore to work around a problem
217 class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
218 InstrItinClass itin>:
219 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
220 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
222 class FEXT_RI16_SP_Store_explicit_ins<bits<5> _op, string asmstr,
223 InstrItinClass itin>:
224 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm),
225 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
228 // EXT-RRI instruction format
231 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
232 InstrItinClass itin>:
233 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
234 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
236 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
237 InstrItinClass itin>:
238 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
239 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
243 // EXT-RRI-A instruction format
246 class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
247 InstrItinClass itin>:
248 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
249 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
252 // EXT-SHIFT instruction format
254 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
255 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa),
256 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
261 class FEXT_T8I816_ins<string asmstr, string asmstr2>:
263 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
264 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
265 !strconcat(asmstr, "\t$imm"))),[]> {
267 let usesCustomInserter = 1;
273 class FEXT_T8I8I16_ins<string asmstr, string asmstr2>:
275 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
276 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
277 !strconcat(asmstr, "\t$targ"))), []> {
279 let usesCustomInserter = 1;
285 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
287 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
288 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32),
289 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
292 // I8_MOV32R instruction format (used only by MOV32R instruction)
295 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
296 FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz),
297 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
300 // This are pseudo formats for multiply
301 // This first one can be changed to non-pseudo now.
305 class FMULT16_ins<string asmstr, InstrItinClass itin> :
306 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
307 !strconcat(asmstr, "\t$rx, $ry"), []>;
312 class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
313 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
314 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
319 // RR-type instruction format
322 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
323 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
324 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
327 class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> :
328 FRRBreak16<(outs), (ins), asmstr, [], itin> {
332 class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> :
333 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
334 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
337 class FRRTR16_ins<string asmstr> :
338 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
339 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
342 // maybe refactor but need a $zero as a dummy first parameter
344 class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
345 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
346 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
348 class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
349 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
350 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
353 class FRR16_M_ins<bits<5> f, string asmstr,
354 InstrItinClass itin> :
355 FRR16<f, (outs CPU16Regs:$rx), (ins),
356 !strconcat(asmstr, "\t$rx"), [], itin>;
358 class FRxRxRy16_ins<bits<5> f, string asmstr,
359 InstrItinClass itin> :
360 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
361 !strconcat(asmstr, "\t$rz, $ry"),
363 let Constraints = "$rx = $rz";
367 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
368 string asmstr, InstrItinClass itin>:
369 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
373 class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
374 string asmstr, InstrItinClass itin>:
375 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
376 !strconcat(asmstr, "\t $rx"), [], itin> ;
379 <bits<5> _funct, bits<3> _subfunc,
380 string asmstr, InstrItinClass itin>:
381 FRR_SF16<_funct, _subfunc, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_),
382 !strconcat(asmstr, "\t $rx"),
384 let Constraints = "$rx_ = $rx";
387 // RRR-type instruction format
390 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
391 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
392 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
395 // These Sel patterns support the generation of conditional move
396 // pseudo instructions.
398 // The nomenclature uses the components making up the pseudo and may
399 // be a bit counter intuitive when compared with the end result we seek.
400 // For example using a bqez in the example directly below results in the
401 // conditional move being done if the tested register is not zero.
402 // I considered in easier to check by keeping the pseudo consistent with
403 // it's components but it could have been done differently.
405 // The simplest case is when can test and operand directly and do the
406 // conditional move based on a simple mips16 conditional
407 // branch instruction.
409 // if $op == beqz or bnez:
414 // if $op == beqz, then if $rt != 0, then the conditional assignment
415 // $rd = $rs is done.
417 // if $op == bnez, then if $rt == 0, then the conditional assignment
418 // $rd = $rs is done.
420 // So this pseudo class only has one operand, i.e. op
422 class Sel<string op>:
423 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
425 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> {
426 //let isCodeGenOnly=1;
427 let Constraints = "$rd = $rd_";
428 let usesCustomInserter = 1;
432 // The next two instruction classes allow for an operand which tests
433 // two operands and returns a value in register T8 and
434 //then does a conditional branch based on the value of T8
437 // op2 can be cmpi or slti/sltiu
438 // op1 can bteqz or btnez
439 // the operands for op2 are a register and a signed constant
441 // $op2 $t, $imm ;test register t and branch conditionally
442 // $op1 .+4 ;op1 is a conditional branch
446 class SeliT<string op1, string op2>:
447 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
448 CPU16Regs:$rl, simm16:$imm),
450 !strconcat("\t$rl, $imm\n\t",
451 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
453 let Constraints = "$rd = $rd_";
454 let usesCustomInserter = 1;
458 // op2 can be cmp or slt/sltu
459 // op1 can be bteqz or btnez
460 // the operands for op2 are two registers
461 // op1 is a conditional branch
464 // $op2 $rl, $rr ;test registers rl,rr
465 // $op1 .+4 ;op2 is a conditional branch
469 class SelT<string op1, string op2>:
470 MipsPseudo16<(outs CPU16Regs:$rd_),
471 (ins CPU16Regs:$rd, CPU16Regs:$rs,
472 CPU16Regs:$rl, CPU16Regs:$rr),
474 !strconcat("\t$rl, $rr\n\t",
475 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
477 let Constraints = "$rd = $rd_";
478 let usesCustomInserter = 1;
484 def imm32: Operand<i32>;
487 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
490 MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm, imm32:$constid),
491 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
495 // Some general instruction class info
499 class ArithLogic16Defs<bit isCom=0> {
501 bit isCommutable = isCom;
502 bit isReMaterializable = 1;
503 bit neverHasSideEffects = 1;
508 bit isTerminator = 1;
514 bit isTerminator = 1;
527 // Format: ADDIU rx, immediate MIPS16e
528 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
529 // To add a constant to a 32-bit integer.
531 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
533 def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>,
534 ArithLogic16Defs<0> {
535 let AddedComplexity = 5;
537 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
538 ArithLogic16Defs<0> {
539 let isCodeGenOnly = 1;
542 def AddiuRxRyOffMemX16:
543 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>;
547 // Format: ADDIU rx, pc, immediate MIPS16e
548 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
549 // To add a constant to the program counter.
551 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
554 // Format: ADDIU sp, immediate MIPS16e
555 // Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
556 // To add a constant to the stack pointer.
559 : FI816_SP_ins<0b011, "addiu", IIAlu> {
562 let AddedComplexity = 5;
566 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
572 // Format: ADDU rz, rx, ry MIPS16e
573 // Purpose: Add Unsigned Word (3-Operand)
574 // To add 32-bit integers.
577 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
580 // Format: AND rx, ry MIPS16e
582 // To do a bitwise logical AND.
584 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
588 // Format: BEQZ rx, offset MIPS16e
589 // Purpose: Branch on Equal to Zero
590 // To test a GPR then do a PC-relative conditional branch.
592 def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
596 // Format: BEQZ rx, offset MIPS16e
597 // Purpose: Branch on Equal to Zero (Extended)
598 // To test a GPR then do a PC-relative conditional branch.
600 def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
603 // Format: B offset MIPS16e
604 // Purpose: Unconditional Branch (Extended)
605 // To do an unconditional PC-relative branch.
608 def Bimm16: FI16_ins<0b00010, "b", IIAlu>, branch16;
610 // Format: B offset MIPS16e
611 // Purpose: Unconditional Branch
612 // To do an unconditional PC-relative branch.
614 def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
617 // Format: BNEZ rx, offset MIPS16e
618 // Purpose: Branch on Not Equal to Zero
619 // To test a GPR then do a PC-relative conditional branch.
621 def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
624 // Format: BNEZ rx, offset MIPS16e
625 // Purpose: Branch on Not Equal to Zero (Extended)
626 // To test a GPR then do a PC-relative conditional branch.
628 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
632 //Format: BREAK immediate
633 // Purpose: Breakpoint
634 // To cause a Breakpoint exception.
636 def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>;
638 // Format: BTEQZ offset MIPS16e
639 // Purpose: Branch on T Equal to Zero (Extended)
640 // To test special register T then do a PC-relative conditional branch.
642 def Bteqz16: FI816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
646 def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
650 def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16;
652 def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">,
655 def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16;
657 def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;
659 def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16;
661 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
665 // Format: BTNEZ offset MIPS16e
666 // Purpose: Branch on T Not Equal to Zero (Extended)
667 // To test special register T then do a PC-relative conditional branch.
670 def Btnez16: FI816_ins<0b001, "btnez", IIAlu>, cbranch16 {
674 def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 {
678 def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16;
680 def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16;
682 def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16;
684 def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;
686 def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16;
688 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
692 // Format: CMP rx, ry MIPS16e
694 // To compare the contents of two GPRs.
696 def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> {
701 // Format: CMPI rx, immediate MIPS16e
702 // Purpose: Compare Immediate
703 // To compare a constant with the contents of a GPR.
705 def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> {
710 // Format: CMPI rx, immediate MIPS16e
711 // Purpose: Compare Immediate (Extended)
712 // To compare a constant with the contents of a GPR.
714 def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> {
720 // Format: DIV rx, ry MIPS16e
721 // Purpose: Divide Word
722 // To divide 32-bit signed integers.
724 def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
725 let Defs = [HI0, LO0];
729 // Format: DIVU rx, ry MIPS16e
730 // Purpose: Divide Unsigned Word
731 // To divide 32-bit unsigned integers.
733 def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
734 let Defs = [HI0, LO0];
737 // Format: JAL target MIPS16e
738 // Purpose: Jump and Link
739 // To execute a procedure call within the current 256 MB-aligned
740 // region and preserve the current ISA.
743 def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
744 let hasDelaySlot = 0; // not true, but we add the nop for now
749 def JalB16 : FJALB16_ins<0b0, "jal", IIAlu>, branch16 {
750 let hasDelaySlot = 0; // not true, but we add the nop for now
756 // Format: JR ra MIPS16e
757 // Purpose: Jump Register Through Register ra
758 // To execute a branch to the instruction address in the return
762 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
764 let isIndirectBranch = 1;
765 let hasDelaySlot = 1;
770 def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> {
772 let isIndirectBranch = 1;
777 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
779 let isIndirectBranch = 1;
784 // Format: LB ry, offset(rx) MIPS16e
785 // Purpose: Load Byte (Extended)
786 // To load a byte from memory as a signed value.
788 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{
789 let isCodeGenOnly = 1;
793 // Format: LBU ry, offset(rx) MIPS16e
794 // Purpose: Load Byte Unsigned (Extended)
795 // To load a byte from memory as a unsigned value.
797 def LbuRxRyOffMemX16:
798 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad {
799 let isCodeGenOnly = 1;
803 // Format: LH ry, offset(rx) MIPS16e
804 // Purpose: Load Halfword signed (Extended)
805 // To load a halfword from memory as a signed value.
807 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{
808 let isCodeGenOnly = 1;
812 // Format: LHU ry, offset(rx) MIPS16e
813 // Purpose: Load Halfword unsigned (Extended)
814 // To load a halfword from memory as an unsigned value.
816 def LhuRxRyOffMemX16:
817 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad {
818 let isCodeGenOnly = 1;
822 // Format: LI rx, immediate MIPS16e
823 // Purpose: Load Immediate
824 // To load a constant into a GPR.
826 def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>;
829 // Format: LI rx, immediate MIPS16e
830 // Purpose: Load Immediate (Extended)
831 // To load a constant into a GPR.
833 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
835 def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIAlu> {
836 let isCodeGenOnly = 1;
840 // Format: LW ry, offset(rx) MIPS16e
841 // Purpose: Load Word (Extended)
842 // To load a word from memory as a signed value.
844 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{
845 let isCodeGenOnly = 1;
848 // Format: LW rx, offset(sp) MIPS16e
849 // Purpose: Load Word (SP-Relative, Extended)
850 // To load an SP-relative word from memory as a signed value.
852 def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10010, "lw", IILoad>, MayLoad{
856 def LwRxPcTcp16: FRI16_TCP_ins<0b10110, "lw", IILoad>, MayLoad;
858 def LwRxPcTcpX16: FEXT_RI16_TCP_ins<0b10110, "lw", IILoad>, MayLoad;
860 // Format: MOVE r32, rz MIPS16e
862 // To move the contents of a GPR to a GPR.
864 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
867 // Format: MOVE ry, r32 MIPS16e
869 // To move the contents of a GPR to a GPR.
871 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
874 // Format: MFHI rx MIPS16e
875 // Purpose: Move From HI Register
876 // To copy the special purpose HI register to a GPR.
878 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
880 let neverHasSideEffects = 1;
884 // Format: MFLO rx MIPS16e
885 // Purpose: Move From LO Register
886 // To copy the special purpose LO register to a GPR.
888 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
890 let neverHasSideEffects = 1;
894 // Pseudo Instruction for mult
896 def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
897 let isCommutable = 1;
898 let neverHasSideEffects = 1;
899 let Defs = [HI0, LO0];
902 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
903 let isCommutable = 1;
904 let neverHasSideEffects = 1;
905 let Defs = [HI0, LO0];
909 // Format: MULT rx, ry MIPS16e
910 // Purpose: Multiply Word
911 // To multiply 32-bit signed integers.
913 def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
914 let isCommutable = 1;
915 let neverHasSideEffects = 1;
916 let Defs = [HI0, LO0];
920 // Format: MULTU rx, ry MIPS16e
921 // Purpose: Multiply Unsigned Word
922 // To multiply 32-bit unsigned integers.
924 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
925 let isCommutable = 1;
926 let neverHasSideEffects = 1;
927 let Defs = [HI0, LO0];
931 // Format: NEG rx, ry MIPS16e
933 // To negate an integer value.
935 def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
938 // Format: NOT rx, ry MIPS16e
940 // To complement an integer value
942 def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
945 // Format: OR rx, ry MIPS16e
947 // To do a bitwise logical OR.
949 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
952 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
953 // (All args are optional) MIPS16e
954 // Purpose: Restore Registers and Deallocate Stack Frame
955 // To deallocate a stack frame before exit from a subroutine,
956 // restoring return address and static registers, and adjusting
961 FI8_SVRS16<0b1, (outs), (ins variable_ops),
962 "", [], IILoad >, MayLoad {
963 let isCodeGenOnly = 1;
970 FI8_SVRS16<0b1, (outs), (ins variable_ops),
971 "", [], IILoad >, MayLoad {
972 let isCodeGenOnly = 1;
978 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
980 // Purpose: Save Registers and Set Up Stack Frame
981 // To set up a stack frame on entry to a subroutine,
982 // saving return address and static registers, and adjusting stack
985 FI8_SVRS16<0b1, (outs), (ins variable_ops),
986 "", [], IIStore >, MayStore {
987 let isCodeGenOnly = 1;
993 FI8_SVRS16<0b1, (outs), (ins variable_ops),
994 "", [], IIStore >, MayStore {
995 let isCodeGenOnly = 1;
1000 // Format: SB ry, offset(rx) MIPS16e
1001 // Purpose: Store Byte (Extended)
1002 // To store a byte to memory.
1004 def SbRxRyOffMemX16:
1005 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
1008 // Format: SEB rx MIPS16e
1009 // Purpose: Sign-Extend Byte
1010 // Sign-extend least significant byte in register rx.
1013 : FRR_SF16_ins<0b10001, 0b100, "seb", IIAlu>;
1016 // Format: SEH rx MIPS16e
1017 // Purpose: Sign-Extend Halfword
1018 // Sign-extend least significant word in register rx.
1021 : FRR_SF16_ins<0b10001, 0b101, "seh", IIAlu>;
1024 // The Sel(T) instructions are pseudos
1025 // T means that they use T8 implicitly.
1028 // Format: SelBeqZ rd, rs, rt
1029 // Purpose: if rt==0, do nothing
1032 def SelBeqZ: Sel<"beqz">;
1035 // Format: SelTBteqZCmp rd, rs, rl, rr
1036 // Purpose: b = Cmp rl, rr.
1037 // If b==0 then do nothing.
1038 // if b!=0 then rd = rs
1040 def SelTBteqZCmp: SelT<"bteqz", "cmp">;
1043 // Format: SelTBteqZCmpi rd, rs, rl, rr
1044 // Purpose: b = Cmpi rl, imm.
1045 // If b==0 then do nothing.
1046 // if b!=0 then rd = rs
1048 def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">;
1051 // Format: SelTBteqZSlt rd, rs, rl, rr
1052 // Purpose: b = Slt rl, rr.
1053 // If b==0 then do nothing.
1054 // if b!=0 then rd = rs
1056 def SelTBteqZSlt: SelT<"bteqz", "slt">;
1059 // Format: SelTBteqZSlti rd, rs, rl, rr
1060 // Purpose: b = Slti rl, imm.
1061 // If b==0 then do nothing.
1062 // if b!=0 then rd = rs
1064 def SelTBteqZSlti: SeliT<"bteqz", "slti">;
1067 // Format: SelTBteqZSltu rd, rs, rl, rr
1068 // Purpose: b = Sltu rl, rr.
1069 // If b==0 then do nothing.
1070 // if b!=0 then rd = rs
1072 def SelTBteqZSltu: SelT<"bteqz", "sltu">;
1075 // Format: SelTBteqZSltiu rd, rs, rl, rr
1076 // Purpose: b = Sltiu rl, imm.
1077 // If b==0 then do nothing.
1078 // if b!=0 then rd = rs
1080 def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">;
1083 // Format: SelBnez rd, rs, rt
1084 // Purpose: if rt!=0, do nothing
1087 def SelBneZ: Sel<"bnez">;
1090 // Format: SelTBtneZCmp rd, rs, rl, rr
1091 // Purpose: b = Cmp rl, rr.
1092 // If b!=0 then do nothing.
1093 // if b0=0 then rd = rs
1095 def SelTBtneZCmp: SelT<"btnez", "cmp">;
1098 // Format: SelTBtnezCmpi rd, rs, rl, rr
1099 // Purpose: b = Cmpi rl, imm.
1100 // If b!=0 then do nothing.
1101 // if b==0 then rd = rs
1103 def SelTBtneZCmpi: SeliT<"btnez", "cmpi">;
1106 // Format: SelTBtneZSlt rd, rs, rl, rr
1107 // Purpose: b = Slt rl, rr.
1108 // If b!=0 then do nothing.
1109 // if b==0 then rd = rs
1111 def SelTBtneZSlt: SelT<"btnez", "slt">;
1114 // Format: SelTBtneZSlti rd, rs, rl, rr
1115 // Purpose: b = Slti rl, imm.
1116 // If b!=0 then do nothing.
1117 // if b==0 then rd = rs
1119 def SelTBtneZSlti: SeliT<"btnez", "slti">;
1122 // Format: SelTBtneZSltu rd, rs, rl, rr
1123 // Purpose: b = Sltu rl, rr.
1124 // If b!=0 then do nothing.
1125 // if b==0 then rd = rs
1127 def SelTBtneZSltu: SelT<"btnez", "sltu">;
1130 // Format: SelTBtneZSltiu rd, rs, rl, rr
1131 // Purpose: b = Slti rl, imm.
1132 // If b!=0 then do nothing.
1133 // if b==0 then rd = rs
1135 def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
1138 // Format: SH ry, offset(rx) MIPS16e
1139 // Purpose: Store Halfword (Extended)
1140 // To store a halfword to memory.
1142 def ShRxRyOffMemX16:
1143 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore;
1146 // Format: SLL rx, ry, sa MIPS16e
1147 // Purpose: Shift Word Left Logical (Extended)
1148 // To execute a left-shift of a word by a fixed number of bits-0 to 31 bits.
1150 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
1153 // Format: SLLV ry, rx MIPS16e
1154 // Purpose: Shift Word Left Logical Variable
1155 // To execute a left-shift of a word by a variable number of bits.
1157 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
1159 // Format: SLTI rx, immediate MIPS16e
1160 // Purpose: Set on Less Than Immediate
1161 // To record the result of a less-than comparison with a constant.
1164 def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> {
1169 // Format: SLTI rx, immediate MIPS16e
1170 // Purpose: Set on Less Than Immediate (Extended)
1171 // To record the result of a less-than comparison with a constant.
1174 def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> {
1178 def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
1180 // Format: SLTIU rx, immediate MIPS16e
1181 // Purpose: Set on Less Than Immediate Unsigned
1182 // To record the result of a less-than comparison with a constant.
1185 def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> {
1190 // Format: SLTI rx, immediate MIPS16e
1191 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1192 // To record the result of a less-than comparison with a constant.
1195 def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> {
1199 // Format: SLTIU rx, immediate MIPS16e
1200 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1201 // To record the result of a less-than comparison with a constant.
1203 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
1206 // Format: SLT rx, ry MIPS16e
1207 // Purpose: Set on Less Than
1208 // To record the result of a less-than comparison.
1210 def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{
1214 def SltCCRxRy16: FCCRR16_ins<"slt">;
1216 // Format: SLTU rx, ry MIPS16e
1217 // Purpose: Set on Less Than Unsigned
1218 // To record the result of an unsigned less-than comparison.
1220 def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{
1224 def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
1225 let isCodeGenOnly=1;
1230 def SltuCCRxRy16: FCCRR16_ins<"sltu">;
1232 // Format: SRAV ry, rx MIPS16e
1233 // Purpose: Shift Word Right Arithmetic Variable
1234 // To execute an arithmetic right-shift of a word by a variable
1237 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
1241 // Format: SRA rx, ry, sa MIPS16e
1242 // Purpose: Shift Word Right Arithmetic (Extended)
1243 // To execute an arithmetic right-shift of a word by a fixed
1244 // number of bits-1 to 8 bits.
1246 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
1250 // Format: SRLV ry, rx MIPS16e
1251 // Purpose: Shift Word Right Logical Variable
1252 // To execute a logical right-shift of a word by a variable
1255 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
1259 // Format: SRL rx, ry, sa MIPS16e
1260 // Purpose: Shift Word Right Logical (Extended)
1261 // To execute a logical right-shift of a word by a fixed
1262 // number of bits-1 to 31 bits.
1264 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
1267 // Format: SUBU rz, rx, ry MIPS16e
1268 // Purpose: Subtract Unsigned Word
1269 // To subtract 32-bit integers
1271 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
1274 // Format: SW ry, offset(rx) MIPS16e
1275 // Purpose: Store Word (Extended)
1276 // To store a word to memory.
1278 def SwRxRyOffMemX16:
1279 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore;
1282 // Format: SW rx, offset(sp) MIPS16e
1283 // Purpose: Store Word rx (SP-Relative)
1284 // To store an SP-relative word to memory.
1286 def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins
1287 <0b11010, "sw", IIStore>, MayStore;
1291 // Format: XOR rx, ry MIPS16e
1293 // To do a bitwise logical XOR.
1295 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
1297 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
1298 let Predicates = [InMips16Mode];
1301 // Unary Arith/Logic
1303 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1304 Mips16Pat<(OpNode CPU16Regs:$r),
1307 def: ArithLogicU_pat<not, NotRxRy16>;
1308 def: ArithLogicU_pat<ineg, NegRxRy16>;
1310 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1311 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1312 (I CPU16Regs:$l, CPU16Regs:$r)>;
1314 def: ArithLogic16_pat<add, AdduRxRyRz16>;
1315 def: ArithLogic16_pat<and, AndRxRxRy16>;
1316 def: ArithLogic16_pat<mul, MultRxRyRz16>;
1317 def: ArithLogic16_pat<or, OrRxRxRy16>;
1318 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
1319 def: ArithLogic16_pat<xor, XorRxRxRy16>;
1321 // Arithmetic and logical instructions with 2 register operands.
1323 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1324 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1325 (I CPU16Regs:$in, imm_type:$imm)>;
1327 def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>;
1328 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
1329 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
1330 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
1331 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
1333 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1334 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1335 (I CPU16Regs:$r, CPU16Regs:$ra)>;
1337 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
1338 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
1339 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
1341 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1342 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
1344 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
1345 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
1346 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
1347 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
1348 def: LoadM16_pat<load, LwRxRyOffMemX16>;
1350 class StoreM16_pat<PatFrag OpNode, Instruction I> :
1351 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr),
1352 (I CPU16Regs:$r, addr16:$addr)>;
1354 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
1355 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
1356 def: StoreM16_pat<store, SwRxRyOffMemX16>;
1358 // Unconditional branch
1359 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
1360 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1361 let Predicates = [InMips16Mode];
1364 def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1365 (Jal16 tglobaladdr:$dst)>;
1367 def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)),
1368 (Jal16 texternalsym:$dst)>;
1372 (brind CPU16Regs:$rs),
1373 (JrcRx16 CPU16Regs:$rs)>;
1375 // Jump and Link (Call)
1376 let isCall=1, hasDelaySlot=0 in
1378 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
1379 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch> {
1384 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
1385 hasExtraSrcRegAllocReq = 1 in
1386 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
1391 class SetCC_R16<PatFrag cond_op, Instruction I>:
1392 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1393 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1395 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1396 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1397 (I CPU16Regs:$rx, imm_type:$imm16)>;
1400 def: Mips16Pat<(i32 addr16:$addr),
1401 (AddiuRxRyOffMemX16 addr16:$addr)>;
1404 // Large (>16 bit) immediate loads
1405 def : Mips16Pat<(i32 imm:$imm), (LwConstant32 imm:$imm, -1)>;
1407 // Carry MipsPatterns
1408 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
1409 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1410 def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
1411 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1412 def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
1413 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
1416 // Some branch conditional patterns are not generated by llvm at this time.
1417 // Some are for seemingly arbitrary reasons not used: i.e. with signed number
1418 // comparison they are used and for unsigned a different pattern is used.
1419 // I am pushing upstream from the full mips16 port and it seemed that I needed
1420 // these earlier and the mips32 port has these but now I cannot create test
1421 // cases that use these patterns. While I sort this all out I will leave these
1422 // extra patterns commented out and if I can be sure they are really not used,
1423 // I will delete the code. I don't want to check the code in uncommented without
1424 // a valid test case. In some cases, the compiler is generating patterns with
1425 // setcc instead and earlier I had implemented setcc first so may have masked
1426 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
1427 // figure out how to enable the brcond patterns or else possibly new
1428 // combinations of of brcond and setcc.
1434 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1435 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1440 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1441 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1445 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1446 (BeqzRxImm16 CPU16Regs:$rx, bb:$targ16)
1450 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1453 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1454 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1461 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1462 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1466 // never called because compiler transforms a >= k to a > (k-1)
1468 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1469 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1476 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1477 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1481 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1482 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1489 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1490 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1497 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1498 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1502 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1503 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1507 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1508 (BnezRxImm16 CPU16Regs:$rx, bb:$targ16)
1512 // This needs to be there but I forget which code will generate it
1515 <(brcond CPU16Regs:$rx, bb:$targ16),
1516 (BnezRxImm16 CPU16Regs:$rx, bb:$targ16)
1525 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1526 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1533 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1534 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1542 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1543 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1546 def: UncondBranch16_pat<br, Bimm16>;
1549 def: Mips16Pat<(i32 immSExt16:$in),
1550 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
1552 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
1558 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry),
1559 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1565 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry),
1566 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1571 // if !(a < b) x = y
1573 def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1574 CPU16Regs:$x, CPU16Regs:$y),
1575 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1576 CPU16Regs:$a, CPU16Regs:$b)>;
1583 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1584 CPU16Regs:$x, CPU16Regs:$y),
1585 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
1586 CPU16Regs:$b, CPU16Regs:$a)>;
1591 // if !(a < b) x = y;
1594 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
1595 CPU16Regs:$x, CPU16Regs:$y),
1596 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1597 CPU16Regs:$a, CPU16Regs:$b)>;
1604 def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
1605 CPU16Regs:$x, CPU16Regs:$y),
1606 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
1607 CPU16Regs:$b, CPU16Regs:$a)>;
1611 // due to an llvm optimization, i don't think that this will ever
1612 // be used. This is transformed into x = (a > k-1)?x:y
1617 // (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1618 // CPU16Regs:$T, CPU16Regs:$F),
1619 // (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
1620 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1623 // (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
1624 // CPU16Regs:$T, CPU16Regs:$F),
1625 // (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
1626 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1631 // if !(a < k) x = y;
1634 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1635 CPU16Regs:$x, CPU16Regs:$y),
1636 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
1637 CPU16Regs:$a, immSExt16:$b)>;
1643 // x = (a <= b)? x : y
1647 def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
1648 CPU16Regs:$x, CPU16Regs:$y),
1649 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1650 CPU16Regs:$b, CPU16Regs:$a)>;
1654 // x = (a <= b)? x : y
1658 def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
1659 CPU16Regs:$x, CPU16Regs:$y),
1660 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1661 CPU16Regs:$b, CPU16Regs:$a)>;
1665 // x = (a == b)? x : y
1667 // if (a != b) x = y
1669 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
1670 CPU16Regs:$x, CPU16Regs:$y),
1671 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
1672 CPU16Regs:$b, CPU16Regs:$a)>;
1676 // x = (a == 0)? x : y
1678 // if (a != 0) x = y
1680 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
1681 CPU16Regs:$x, CPU16Regs:$y),
1682 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
1688 // x = (a == k)? x : y
1690 // if (a != k) x = y
1692 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
1693 CPU16Regs:$x, CPU16Regs:$y),
1694 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
1695 CPU16Regs:$a, immZExt16:$k)>;
1700 // x = (a != b)? x : y
1702 // if (a == b) x = y
1705 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1706 CPU16Regs:$x, CPU16Regs:$y),
1707 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
1708 CPU16Regs:$b, CPU16Regs:$a)>;
1712 // x = (a != 0)? x : y
1714 // if (a == 0) x = y
1716 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1717 CPU16Regs:$x, CPU16Regs:$y),
1718 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1726 def : Mips16Pat<(select CPU16Regs:$a,
1727 CPU16Regs:$x, CPU16Regs:$y),
1728 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1734 // x = (a != k)? x : y
1736 // if (a == k) x = y
1738 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1739 CPU16Regs:$x, CPU16Regs:$y),
1740 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
1741 CPU16Regs:$a, immZExt16:$k)>;
1744 // When writing C code to test setxx these patterns,
1745 // some will be transformed into
1746 // other things. So we test using C code but using -O3 and -O0
1751 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
1752 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
1755 <(seteq CPU16Regs:$lhs, 0),
1756 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
1764 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1765 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1769 // For constants, llvm transforms this to:
1770 // x > (k -1) and then reverses the operands to use setlt. So this pattern
1771 // is not used now by the compiler. (Presumably checking that k-1 does not
1772 // overflow). The compiler never uses this at a the current time, due to
1773 // other optimizations.
1776 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
1777 // (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
1778 // (LiRxImmX16 1))>;
1780 // This catches the x >= -32768 case by transforming it to x > -32769
1783 <(setgt CPU16Regs:$lhs, -32769),
1784 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
1793 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
1794 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1800 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
1801 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>;
1806 def: SetCC_R16<setlt, SltCCRxRy16>;
1808 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
1814 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
1815 (SltuCCRxRy16 (LiRxImmX16 0),
1816 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1823 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1824 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1827 // this pattern will never be used because the compiler will transform
1828 // x >= k to x > (k - 1) and then use SLT
1831 // <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1832 // (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1833 // (LiRxImmX16 1))>;
1839 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1840 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1846 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1847 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1852 def: SetCC_R16<setult, SltuCCRxRy16>;
1854 def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1856 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1857 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
1860 def : Mips16Pat<(MipsHi tblockaddress:$in),
1861 (SllX16 (LiRxImmX16 tblockaddress:$in), 16)>;
1862 def : Mips16Pat<(MipsHi tglobaladdr:$in),
1863 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>;
1864 def : Mips16Pat<(MipsHi tjumptable:$in),
1865 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>;
1866 def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
1867 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
1869 def : Mips16Pat<(MipsLo tblockaddress:$in), (LiRxImmX16 tblockaddress:$in)>;
1872 class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1873 Mips16Pat<(MipsWrapper RC:$gp, node:$in),
1874 (ADDiuOp RC:$gp, node:$in)>;
1877 def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>;
1878 def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
1880 def : Mips16Pat<(i32 (extloadi8 addr16:$src)),
1881 (LbuRxRyOffMemX16 addr16:$src)>;
1882 def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
1883 (LhuRxRyOffMemX16 addr16:$src)>;
1885 def: Mips16Pat<(trap), (Break16)>;
1887 def : Mips16Pat<(sext_inreg CPU16Regs:$val, i8),
1888 (SebRx16 CPU16Regs:$val)>;
1890 def : Mips16Pat<(sext_inreg CPU16Regs:$val, i16),
1891 (SehRx16 CPU16Regs:$val)>;
1895 (outs CPU16Regs:$rh, CPU16Regs:$rl),
1896 (ins simm16:$immHi, simm16:$immLo),
1897 "\tli\t$rh, $immHi\n\taddiu\t$rl, $$pc, $immLo\n ",[]> ;
1899 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
1900 def cpinst_operand : Operand<i32> {
1901 // let PrintMethod = "printCPInstOperand";
1904 // CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1905 // the function. The first operand is the ID# for this instruction, the second
1906 // is the index into the MachineConstantPool that this is, the third is the
1907 // size in bytes of this constant pool entry.
1909 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1910 def CONSTPOOL_ENTRY :
1911 MipsPseudo16<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1912 i32imm:$size), "foo", []>;