1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
18 ComplexPattern<iPTR, 3, "SelectAddr16", [frameindex], [SDNPWantParent]>;
22 def mem16 : Operand<i32> {
23 let PrintMethod = "printMemOperand";
24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16Regs);
25 let EncoderMethod = "getMemEncoding";
28 def mem16_ea : Operand<i32> {
29 let PrintMethod = "printMemOperandEA";
30 let MIOperandInfo = (ops CPU16Regs, simm16);
31 let EncoderMethod = "getMemEncoding";
36 // I8 instruction format
39 class FI816_ins_base<bits<3> _func, string asmstr,
40 string asmstr2, InstrItinClass itin>:
41 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
45 class FI816_SP_ins<bits<3> _func, string asmstr,
47 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
50 // RI instruction format
54 class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
56 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
57 !strconcat(asmstr, asmstr2), [], itin>;
59 class FRI16_ins<bits<5> op, string asmstr,
61 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
63 class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2,
65 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
66 !strconcat(asmstr, asmstr2), [], itin>;
68 class FRI16R_ins<bits<5> op, string asmstr,
70 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
72 class F2RI16_ins<bits<5> _op, string asmstr,
74 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
75 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
76 let Constraints = "$rx_ = $rx";
79 class FRI16_B_ins<bits<5> _op, string asmstr,
81 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
82 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>;
84 // Compare a register and immediate and place result in CC
87 // EXT-CCRR Instruction format
89 class FEXT_CCRXI16_ins<string asmstr>:
90 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
91 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
95 // JAL and JALX instruction format
97 class FJAL16_ins<bits<1> _X, string asmstr,
99 FJAL16<_X, (outs), (ins simm20:$imm),
100 !strconcat(asmstr, "\t$imm\n\tnop"),[],
105 // EXT-I instruction format
107 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
108 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
109 !strconcat(asmstr, "\t$imm16"),[], itin>;
112 // EXT-I8 instruction format
115 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
116 string asmstr2, InstrItinClass itin>:
117 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
120 class FEXT_I816_ins<bits<3> _func, string asmstr,
121 InstrItinClass itin>:
122 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
124 class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
125 InstrItinClass itin>:
126 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>;
129 // Assembler formats in alphabetical order.
130 // Natural and pseudos are mixed together.
132 // Compare two registers and place result in CC
133 // Implicit use of T8
135 // CC-RR Instruction format
137 class FCCRR16_ins<string asmstr> :
138 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
139 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
144 // EXT-RI instruction format
147 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
148 InstrItinClass itin>:
149 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
150 !strconcat(asmstr, asmstr2), [], itin>;
152 class FEXT_RI16_ins<bits<5> _op, string asmstr,
153 InstrItinClass itin>:
154 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
156 class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2,
157 InstrItinClass itin>:
158 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm),
159 !strconcat(asmstr, asmstr2), [], itin>;
161 class FEXT_RI16R_ins<bits<5> _op, string asmstr,
162 InstrItinClass itin>:
163 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
165 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
166 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
168 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
169 InstrItinClass itin>:
170 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
171 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
173 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
174 InstrItinClass itin>:
175 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
176 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
177 let Constraints = "$rx_ = $rx";
181 // this has an explicit sp argument that we ignore to work around a problem
183 class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
184 InstrItinClass itin>:
185 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
186 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
189 // EXT-RRI instruction format
192 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
193 InstrItinClass itin>:
194 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
195 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
197 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
198 InstrItinClass itin>:
199 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
200 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
204 // EXT-RRI-A instruction format
207 class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
208 InstrItinClass itin>:
209 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
210 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
213 // EXT-SHIFT instruction format
215 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
216 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
217 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
222 class FEXT_T8I816_ins<string asmstr, string asmstr2>:
224 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
225 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
226 !strconcat(asmstr, "\t$imm"))),[]> {
228 let usesCustomInserter = 1;
234 class FEXT_T8I8I16_ins<string asmstr, string asmstr2>:
236 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
237 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
238 !strconcat(asmstr, "\t$targ"))), []> {
245 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
247 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
248 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32),
249 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
252 // I8_MOV32R instruction format (used only by MOV32R instruction)
255 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
256 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
257 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
260 // This are pseudo formats for multiply
261 // This first one can be changed to non pseudo now.
265 class FMULT16_ins<string asmstr, InstrItinClass itin> :
266 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
267 !strconcat(asmstr, "\t$rx, $ry"), []>;
272 class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
273 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
274 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
279 // RR-type instruction format
282 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
283 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
284 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
287 class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> :
288 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
289 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
292 class FRRTR16_ins<string asmstr> :
293 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
294 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
297 // maybe refactor but need a $zero as a dummy first parameter
299 class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
300 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
301 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
303 class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
304 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
305 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
308 class FRR16_M_ins<bits<5> f, string asmstr,
309 InstrItinClass itin> :
310 FRR16<f, (outs CPU16Regs:$rx), (ins),
311 !strconcat(asmstr, "\t$rx"), [], itin>;
313 class FRxRxRy16_ins<bits<5> f, string asmstr,
314 InstrItinClass itin> :
315 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
316 !strconcat(asmstr, "\t$rz, $ry"),
318 let Constraints = "$rx = $rz";
322 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
323 string asmstr, InstrItinClass itin>:
324 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
328 class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
329 string asmstr, InstrItinClass itin>:
330 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
331 !strconcat(asmstr, "\t $rx"), [], itin> ;
334 // RRR-type instruction format
337 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
338 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
339 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
342 // These Sel patterns support the generation of conditional move
343 // pseudo instructions.
345 // The nomenclature uses the components making up the pseudo and may
346 // be a bit counter intuitive when compared with the end result we seek.
347 // For example using a bqez in the example directly below results in the
348 // conditional move being done if the tested register is not zero.
349 // I considered in easier to check by keeping the pseudo consistent with
350 // it's components but it could have been done differently.
352 // The simplest case is when can test and operand directly and do the
353 // conditional move based on a simple mips16 conditional
354 // branch instruction.
356 // if $op == beqz or bnez:
361 // if $op == beqz, then if $rt != 0, then the conditional assignment
362 // $rd = $rs is done.
364 // if $op == bnez, then if $rt == 0, then the conditional assignment
365 // $rd = $rs is done.
367 // So this pseudo class only has one operand, i.e. op
369 class Sel<string op>:
370 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
372 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> {
373 //let isCodeGenOnly=1;
374 let Constraints = "$rd = $rd_";
375 let usesCustomInserter = 1;
379 // The next two instruction classes allow for an operand which tests
380 // two operands and returns a value in register T8 and
381 //then does a conditional branch based on the value of T8
384 // op2 can be cmpi or slti/sltiu
385 // op1 can bteqz or btnez
386 // the operands for op2 are a register and a signed constant
388 // $op2 $t, $imm ;test register t and branch conditionally
389 // $op1 .+4 ;op1 is a conditional branch
393 class SeliT<string op1, string op2>:
394 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
395 CPU16Regs:$rl, simm16:$imm),
397 !strconcat("\t$rl, $imm\n\t",
398 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
400 let Constraints = "$rd = $rd_";
401 let usesCustomInserter = 1;
405 // op2 can be cmp or slt/sltu
406 // op1 can be bteqz or btnez
407 // the operands for op2 are two registers
408 // op1 is a conditional branch
411 // $op2 $rl, $rr ;test registers rl,rr
412 // $op1 .+4 ;op2 is a conditional branch
416 class SelT<string op1, string op2>:
417 MipsPseudo16<(outs CPU16Regs:$rd_),
418 (ins CPU16Regs:$rd, CPU16Regs:$rs,
419 CPU16Regs:$rl, CPU16Regs:$rr),
421 !strconcat("\t$rl, $rr\n\t",
422 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
424 let Constraints = "$rd = $rd_";
425 let usesCustomInserter = 1;
431 def imm32: Operand<i32>;
434 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
437 MipsPseudo16<(outs), (ins CPU16Regs:$rx, imm32:$imm),
438 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
442 // Some general instruction class info
446 class ArithLogic16Defs<bit isCom=0> {
448 bit isCommutable = isCom;
449 bit isReMaterializable = 1;
450 bit neverHasSideEffects = 1;
455 bit isTerminator = 1;
461 bit isTerminator = 1;
474 // Format: ADDIU rx, immediate MIPS16e
475 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
476 // To add a constant to a 32-bit integer.
478 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
480 def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>,
481 ArithLogic16Defs<0> {
482 let AddedComplexity = 5;
484 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
485 ArithLogic16Defs<0> {
486 let isCodeGenOnly = 1;
489 def AddiuRxRyOffMemX16:
490 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>;
494 // Format: ADDIU rx, pc, immediate MIPS16e
495 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
496 // To add a constant to the program counter.
498 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
501 // Format: ADDIU sp, immediate MIPS16e
502 // Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
503 // To add a constant to the stack pointer.
506 : FI816_SP_ins<0b011, "addiu", IIAlu> {
509 let AddedComplexity = 5;
513 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
519 // Format: ADDU rz, rx, ry MIPS16e
520 // Purpose: Add Unsigned Word (3-Operand)
521 // To add 32-bit integers.
524 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
527 // Format: AND rx, ry MIPS16e
529 // To do a bitwise logical AND.
531 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
535 // Format: BEQZ rx, offset MIPS16e
536 // Purpose: Branch on Equal to Zero
537 // To test a GPR then do a PC-relative conditional branch.
539 def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
543 // Format: BEQZ rx, offset MIPS16e
544 // Purpose: Branch on Equal to Zero (Extended)
545 // To test a GPR then do a PC-relative conditional branch.
547 def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
549 // Format: B offset MIPS16e
550 // Purpose: Unconditional Branch
551 // To do an unconditional PC-relative branch.
553 def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
556 // Format: BNEZ rx, offset MIPS16e
557 // Purpose: Branch on Not Equal to Zero
558 // To test a GPR then do a PC-relative conditional branch.
560 def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
563 // Format: BNEZ rx, offset MIPS16e
564 // Purpose: Branch on Not Equal to Zero (Extended)
565 // To test a GPR then do a PC-relative conditional branch.
567 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
570 // Format: BTEQZ offset MIPS16e
571 // Purpose: Branch on T Equal to Zero (Extended)
572 // To test special register T then do a PC-relative conditional branch.
574 def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
578 def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16;
580 def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">,
583 def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16;
585 def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;
587 def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16;
589 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
593 // Format: BTNEZ offset MIPS16e
594 // Purpose: Branch on T Not Equal to Zero (Extended)
595 // To test special register T then do a PC-relative conditional branch.
597 def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 {
601 def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16;
603 def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16;
605 def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16;
607 def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;
609 def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16;
611 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
615 // Format: CMP rx, ry MIPS16e
617 // To compare the contents of two GPRs.
619 def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> {
624 // Format: CMPI rx, immediate MIPS16e
625 // Purpose: Compare Immediate
626 // To compare a constant with the contents of a GPR.
628 def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> {
633 // Format: CMPI rx, immediate MIPS16e
634 // Purpose: Compare Immediate (Extended)
635 // To compare a constant with the contents of a GPR.
637 def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> {
643 // Format: DIV rx, ry MIPS16e
644 // Purpose: Divide Word
645 // To divide 32-bit signed integers.
647 def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
652 // Format: DIVU rx, ry MIPS16e
653 // Purpose: Divide Unsigned Word
654 // To divide 32-bit unsigned integers.
656 def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
660 // Format: JAL target MIPS16e
661 // Purpose: Jump and Link
662 // To execute a procedure call within the current 256 MB-aligned
663 // region and preserve the current ISA.
666 def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
668 let hasDelaySlot = 0; // not true, but we add the nop for now
674 // Format: JR ra MIPS16e
675 // Purpose: Jump Register Through Register ra
676 // To execute a branch to the instruction address in the return
680 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
682 let isIndirectBranch = 1;
683 let hasDelaySlot = 1;
688 def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> {
690 let isIndirectBranch = 1;
695 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
697 let isIndirectBranch = 1;
702 // Format: LB ry, offset(rx) MIPS16e
703 // Purpose: Load Byte (Extended)
704 // To load a byte from memory as a signed value.
706 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{
707 let isCodeGenOnly = 1;
711 // Format: LBU ry, offset(rx) MIPS16e
712 // Purpose: Load Byte Unsigned (Extended)
713 // To load a byte from memory as a unsigned value.
715 def LbuRxRyOffMemX16:
716 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad {
717 let isCodeGenOnly = 1;
721 // Format: LH ry, offset(rx) MIPS16e
722 // Purpose: Load Halfword signed (Extended)
723 // To load a halfword from memory as a signed value.
725 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{
726 let isCodeGenOnly = 1;
730 // Format: LHU ry, offset(rx) MIPS16e
731 // Purpose: Load Halfword unsigned (Extended)
732 // To load a halfword from memory as an unsigned value.
734 def LhuRxRyOffMemX16:
735 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad {
736 let isCodeGenOnly = 1;
740 // Format: LI rx, immediate MIPS16e
741 // Purpose: Load Immediate
742 // To load a constant into a GPR.
744 def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>;
747 // Format: LI rx, immediate MIPS16e
748 // Purpose: Load Immediate (Extended)
749 // To load a constant into a GPR.
751 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
754 // Format: LW ry, offset(rx) MIPS16e
755 // Purpose: Load Word (Extended)
756 // To load a word from memory as a signed value.
758 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{
759 let isCodeGenOnly = 1;
762 // Format: LW rx, offset(sp) MIPS16e
763 // Purpose: Load Word (SP-Relative, Extended)
764 // To load an SP-relative word from memory as a signed value.
766 def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{
771 // Format: MOVE r32, rz MIPS16e
773 // To move the contents of a GPR to a GPR.
775 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
778 // Format: MOVE ry, r32 MIPS16e
780 // To move the contents of a GPR to a GPR.
782 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
785 // Format: MFHI rx MIPS16e
786 // Purpose: Move From HI Register
787 // To copy the special purpose HI register to a GPR.
789 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
791 let neverHasSideEffects = 1;
795 // Format: MFLO rx MIPS16e
796 // Purpose: Move From LO Register
797 // To copy the special purpose LO register to a GPR.
799 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
801 let neverHasSideEffects = 1;
805 // Pseudo Instruction for mult
807 def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
808 let isCommutable = 1;
809 let neverHasSideEffects = 1;
813 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
814 let isCommutable = 1;
815 let neverHasSideEffects = 1;
820 // Format: MULT rx, ry MIPS16e
821 // Purpose: Multiply Word
822 // To multiply 32-bit signed integers.
824 def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
825 let isCommutable = 1;
826 let neverHasSideEffects = 1;
831 // Format: MULTU rx, ry MIPS16e
832 // Purpose: Multiply Unsigned Word
833 // To multiply 32-bit unsigned integers.
835 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
836 let isCommutable = 1;
837 let neverHasSideEffects = 1;
842 // Format: NEG rx, ry MIPS16e
844 // To negate an integer value.
846 def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
849 // Format: NOT rx, ry MIPS16e
851 // To complement an integer value
853 def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
856 // Format: OR rx, ry MIPS16e
858 // To do a bitwise logical OR.
860 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
863 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
864 // (All args are optional) MIPS16e
865 // Purpose: Restore Registers and Deallocate Stack Frame
866 // To deallocate a stack frame before exit from a subroutine,
867 // restoring return address and static registers, and adjusting
871 // fixed form for restoring RA and the frame
872 // for direct object emitter, encoding needs to be adjusted for the
875 let ra=1, s=0,s0=1,s1=1 in
877 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
878 "restore\t$$ra, $$s0, $$s1, $frame_size", [], IILoad >, MayLoad {
879 let isCodeGenOnly = 1;
880 let Defs = [S0, S1, RA, SP];
884 // Use Restore to increment SP since SP is not a Mip 16 register, this
885 // is an easy way to do that which does not require a register.
887 let ra=0, s=0,s0=0,s1=0 in
889 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
890 "restore\t$frame_size", [], IILoad >, MayLoad {
891 let isCodeGenOnly = 1;
897 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
899 // Purpose: Save Registers and Set Up Stack Frame
900 // To set up a stack frame on entry to a subroutine,
901 // saving return address and static registers, and adjusting stack
903 let ra=1, s=1,s0=1,s1=1 in
905 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
906 "save\t$$ra, $$s0, $$s1, $frame_size", [], IIStore >, MayStore {
907 let isCodeGenOnly = 1;
908 let Uses = [RA, SP, S0, S1];
913 // Use Save to decrement the SP by a constant since SP is not
914 // a Mips16 register.
916 let ra=0, s=0,s0=0,s1=0 in
918 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
919 "save\t$frame_size", [], IIStore >, MayStore {
920 let isCodeGenOnly = 1;
925 // Format: SB ry, offset(rx) MIPS16e
926 // Purpose: Store Byte (Extended)
927 // To store a byte to memory.
930 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
933 // The Sel(T) instructions are pseudos
934 // T means that they use T8 implicitly.
937 // Format: SelBeqZ rd, rs, rt
938 // Purpose: if rt==0, do nothing
941 def SelBeqZ: Sel<"beqz">;
944 // Format: SelTBteqZCmp rd, rs, rl, rr
945 // Purpose: b = Cmp rl, rr.
946 // If b==0 then do nothing.
947 // if b!=0 then rd = rs
949 def SelTBteqZCmp: SelT<"bteqz", "cmp">;
952 // Format: SelTBteqZCmpi rd, rs, rl, rr
953 // Purpose: b = Cmpi rl, imm.
954 // If b==0 then do nothing.
955 // if b!=0 then rd = rs
957 def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">;
960 // Format: SelTBteqZSlt rd, rs, rl, rr
961 // Purpose: b = Slt rl, rr.
962 // If b==0 then do nothing.
963 // if b!=0 then rd = rs
965 def SelTBteqZSlt: SelT<"bteqz", "slt">;
968 // Format: SelTBteqZSlti rd, rs, rl, rr
969 // Purpose: b = Slti rl, imm.
970 // If b==0 then do nothing.
971 // if b!=0 then rd = rs
973 def SelTBteqZSlti: SeliT<"bteqz", "slti">;
976 // Format: SelTBteqZSltu rd, rs, rl, rr
977 // Purpose: b = Sltu rl, rr.
978 // If b==0 then do nothing.
979 // if b!=0 then rd = rs
981 def SelTBteqZSltu: SelT<"bteqz", "sltu">;
984 // Format: SelTBteqZSltiu rd, rs, rl, rr
985 // Purpose: b = Sltiu rl, imm.
986 // If b==0 then do nothing.
987 // if b!=0 then rd = rs
989 def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">;
992 // Format: SelBnez rd, rs, rt
993 // Purpose: if rt!=0, do nothing
996 def SelBneZ: Sel<"bnez">;
999 // Format: SelTBtneZCmp rd, rs, rl, rr
1000 // Purpose: b = Cmp rl, rr.
1001 // If b!=0 then do nothing.
1002 // if b0=0 then rd = rs
1004 def SelTBtneZCmp: SelT<"btnez", "cmp">;
1007 // Format: SelTBtnezCmpi rd, rs, rl, rr
1008 // Purpose: b = Cmpi rl, imm.
1009 // If b!=0 then do nothing.
1010 // if b==0 then rd = rs
1012 def SelTBtneZCmpi: SeliT<"btnez", "cmpi">;
1015 // Format: SelTBtneZSlt rd, rs, rl, rr
1016 // Purpose: b = Slt rl, rr.
1017 // If b!=0 then do nothing.
1018 // if b==0 then rd = rs
1020 def SelTBtneZSlt: SelT<"btnez", "slt">;
1023 // Format: SelTBtneZSlti rd, rs, rl, rr
1024 // Purpose: b = Slti rl, imm.
1025 // If b!=0 then do nothing.
1026 // if b==0 then rd = rs
1028 def SelTBtneZSlti: SeliT<"btnez", "slti">;
1031 // Format: SelTBtneZSltu rd, rs, rl, rr
1032 // Purpose: b = Sltu rl, rr.
1033 // If b!=0 then do nothing.
1034 // if b==0 then rd = rs
1036 def SelTBtneZSltu: SelT<"btnez", "sltu">;
1039 // Format: SelTBtneZSltiu rd, rs, rl, rr
1040 // Purpose: b = Slti rl, imm.
1041 // If b!=0 then do nothing.
1042 // if b==0 then rd = rs
1044 def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
1047 // Format: SH ry, offset(rx) MIPS16e
1048 // Purpose: Store Halfword (Extended)
1049 // To store a halfword to memory.
1051 def ShRxRyOffMemX16:
1052 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore;
1055 // Format: SLL rx, ry, sa MIPS16e
1056 // Purpose: Shift Word Left Logical (Extended)
1057 // To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
1059 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
1062 // Format: SLLV ry, rx MIPS16e
1063 // Purpose: Shift Word Left Logical Variable
1064 // To execute a left-shift of a word by a variable number of bits.
1066 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
1068 // Format: SLTI rx, immediate MIPS16e
1069 // Purpose: Set on Less Than Immediate
1070 // To record the result of a less-than comparison with a constant.
1073 def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> {
1078 // Format: SLTI rx, immediate MIPS16e
1079 // Purpose: Set on Less Than Immediate (Extended)
1080 // To record the result of a less-than comparison with a constant.
1083 def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> {
1087 def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
1089 // Format: SLTIU rx, immediate MIPS16e
1090 // Purpose: Set on Less Than Immediate Unsigned
1091 // To record the result of a less-than comparison with a constant.
1094 def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> {
1099 // Format: SLTI rx, immediate MIPS16e
1100 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1101 // To record the result of a less-than comparison with a constant.
1104 def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> {
1108 // Format: SLTIU rx, immediate MIPS16e
1109 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1110 // To record the result of a less-than comparison with a constant.
1112 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
1115 // Format: SLT rx, ry MIPS16e
1116 // Purpose: Set on Less Than
1117 // To record the result of a less-than comparison.
1119 def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{
1123 def SltCCRxRy16: FCCRR16_ins<"slt">;
1125 // Format: SLTU rx, ry MIPS16e
1126 // Purpose: Set on Less Than Unsigned
1127 // To record the result of an unsigned less-than comparison.
1129 def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{
1133 def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
1134 let isCodeGenOnly=1;
1139 def SltuCCRxRy16: FCCRR16_ins<"sltu">;
1141 // Format: SRAV ry, rx MIPS16e
1142 // Purpose: Shift Word Right Arithmetic Variable
1143 // To execute an arithmetic right-shift of a word by a variable
1146 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
1150 // Format: SRA rx, ry, sa MIPS16e
1151 // Purpose: Shift Word Right Arithmetic (Extended)
1152 // To execute an arithmetic right-shift of a word by a fixed
1153 // number of bits—1 to 8 bits.
1155 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
1159 // Format: SRLV ry, rx MIPS16e
1160 // Purpose: Shift Word Right Logical Variable
1161 // To execute a logical right-shift of a word by a variable
1164 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
1168 // Format: SRL rx, ry, sa MIPS16e
1169 // Purpose: Shift Word Right Logical (Extended)
1170 // To execute a logical right-shift of a word by a fixed
1171 // number of bits—1 to 31 bits.
1173 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
1176 // Format: SUBU rz, rx, ry MIPS16e
1177 // Purpose: Subtract Unsigned Word
1178 // To subtract 32-bit integers
1180 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
1183 // Format: SW ry, offset(rx) MIPS16e
1184 // Purpose: Store Word (Extended)
1185 // To store a word to memory.
1187 def SwRxRyOffMemX16:
1188 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore;
1191 // Format: SW rx, offset(sp) MIPS16e
1192 // Purpose: Store Word rx (SP-Relative)
1193 // To store an SP-relative word to memory.
1195 def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore;
1199 // Format: XOR rx, ry MIPS16e
1201 // To do a bitwise logical XOR.
1203 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
1205 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
1206 let Predicates = [InMips16Mode];
1209 // Unary Arith/Logic
1211 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1212 Mips16Pat<(OpNode CPU16Regs:$r),
1215 def: ArithLogicU_pat<not, NotRxRy16>;
1216 def: ArithLogicU_pat<ineg, NegRxRy16>;
1218 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1219 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1220 (I CPU16Regs:$l, CPU16Regs:$r)>;
1222 def: ArithLogic16_pat<add, AdduRxRyRz16>;
1223 def: ArithLogic16_pat<and, AndRxRxRy16>;
1224 def: ArithLogic16_pat<mul, MultRxRyRz16>;
1225 def: ArithLogic16_pat<or, OrRxRxRy16>;
1226 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
1227 def: ArithLogic16_pat<xor, XorRxRxRy16>;
1229 // Arithmetic and logical instructions with 2 register operands.
1231 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1232 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1233 (I CPU16Regs:$in, imm_type:$imm)>;
1235 def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>;
1236 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
1237 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
1238 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
1239 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
1241 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1242 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1243 (I CPU16Regs:$r, CPU16Regs:$ra)>;
1245 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
1246 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
1247 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
1249 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1250 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
1252 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
1253 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
1254 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
1255 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
1256 def: LoadM16_pat<load, LwRxRyOffMemX16>;
1258 class StoreM16_pat<PatFrag OpNode, Instruction I> :
1259 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr),
1260 (I CPU16Regs:$r, addr16:$addr)>;
1262 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
1263 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
1264 def: StoreM16_pat<store, SwRxRyOffMemX16>;
1266 // Unconditional branch
1267 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
1268 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1269 let Predicates = [InMips16Mode];
1272 def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1273 (Jal16 tglobaladdr:$dst)>;
1275 def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)),
1276 (Jal16 texternalsym:$dst)>;
1280 (brind CPU16Regs:$rs),
1281 (JrcRx16 CPU16Regs:$rs)>;
1283 // Jump and Link (Call)
1284 let isCall=1, hasDelaySlot=0 in
1286 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
1287 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
1290 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
1291 hasExtraSrcRegAllocReq = 1 in
1292 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
1297 class SetCC_R16<PatFrag cond_op, Instruction I>:
1298 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1299 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1301 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1302 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1303 (I CPU16Regs:$rx, imm_type:$imm16)>;
1306 def: Mips16Pat<(i32 addr16:$addr),
1307 (AddiuRxRyOffMemX16 addr16:$addr)>;
1310 // Large (>16 bit) immediate loads
1311 def : Mips16Pat<(i32 imm:$imm),
1312 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16),
1313 (LiRxImmX16 (LO16 imm:$imm)))>;
1315 // Carry MipsPatterns
1316 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
1317 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1318 def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
1319 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1320 def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
1321 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
1324 // Some branch conditional patterns are not generated by llvm at this time.
1325 // Some are for seemingly arbitrary reasons not used: i.e. with signed number
1326 // comparison they are used and for unsigned a different pattern is used.
1327 // I am pushing upstream from the full mips16 port and it seemed that I needed
1328 // these earlier and the mips32 port has these but now I cannot create test
1329 // cases that use these patterns. While I sort this all out I will leave these
1330 // extra patterns commented out and if I can be sure they are really not used,
1331 // I will delete the code. I don't want to check the code in uncommented without
1332 // a valid test case. In some cases, the compiler is generating patterns with
1333 // setcc instead and earlier I had implemented setcc first so may have masked
1334 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
1335 // figure out how to enable the brcond patterns or else possibly new
1336 // combinations of of brcond and setcc.
1342 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1343 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1348 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1349 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1353 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1354 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16)
1358 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1361 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1362 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1369 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1370 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1374 // never called because compiler transforms a >= k to a > (k-1)
1376 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1377 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1384 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1385 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1389 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1390 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1397 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1398 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1405 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1406 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1410 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1411 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1415 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1416 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1420 // This needs to be there but I forget which code will generate it
1423 <(brcond CPU16Regs:$rx, bb:$targ16),
1424 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1433 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1434 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1441 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1442 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1450 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1451 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1454 def: UncondBranch16_pat<br, BimmX16>;
1457 def: Mips16Pat<(i32 immSExt16:$in),
1458 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
1460 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
1466 <(MipsDivRem CPU16Regs:$rx, CPU16Regs:$ry),
1467 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1473 <(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry),
1474 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1479 // if !(a < b) x = y
1481 def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1482 CPU16Regs:$x, CPU16Regs:$y),
1483 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1484 CPU16Regs:$a, CPU16Regs:$b)>;
1491 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1492 CPU16Regs:$x, CPU16Regs:$y),
1493 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
1494 CPU16Regs:$b, CPU16Regs:$a)>;
1499 // if !(a < b) x = y;
1502 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
1503 CPU16Regs:$x, CPU16Regs:$y),
1504 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1505 CPU16Regs:$a, CPU16Regs:$b)>;
1512 def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
1513 CPU16Regs:$x, CPU16Regs:$y),
1514 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
1515 CPU16Regs:$b, CPU16Regs:$a)>;
1519 // due to an llvm optimization, i don't think that this will ever
1520 // be used. This is transformed into x = (a > k-1)?x:y
1525 // (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1526 // CPU16Regs:$T, CPU16Regs:$F),
1527 // (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
1528 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1531 // (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
1532 // CPU16Regs:$T, CPU16Regs:$F),
1533 // (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
1534 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1539 // if !(a < k) x = y;
1542 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1543 CPU16Regs:$x, CPU16Regs:$y),
1544 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
1545 CPU16Regs:$a, immSExt16:$b)>;
1551 // x = (a <= b)? x : y
1555 def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
1556 CPU16Regs:$x, CPU16Regs:$y),
1557 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1558 CPU16Regs:$b, CPU16Regs:$a)>;
1562 // x = (a <= b)? x : y
1566 def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
1567 CPU16Regs:$x, CPU16Regs:$y),
1568 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1569 CPU16Regs:$b, CPU16Regs:$a)>;
1573 // x = (a == b)? x : y
1575 // if (a != b) x = y
1577 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
1578 CPU16Regs:$x, CPU16Regs:$y),
1579 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
1580 CPU16Regs:$b, CPU16Regs:$a)>;
1584 // x = (a == 0)? x : y
1586 // if (a != 0) x = y
1588 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
1589 CPU16Regs:$x, CPU16Regs:$y),
1590 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
1596 // x = (a == k)? x : y
1598 // if (a != k) x = y
1600 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
1601 CPU16Regs:$x, CPU16Regs:$y),
1602 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
1603 CPU16Regs:$a, immZExt16:$k)>;
1608 // x = (a != b)? x : y
1610 // if (a == b) x = y
1613 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1614 CPU16Regs:$x, CPU16Regs:$y),
1615 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
1616 CPU16Regs:$b, CPU16Regs:$a)>;
1620 // x = (a != 0)? x : y
1622 // if (a == 0) x = y
1624 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1625 CPU16Regs:$x, CPU16Regs:$y),
1626 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1634 def : Mips16Pat<(select CPU16Regs:$a,
1635 CPU16Regs:$x, CPU16Regs:$y),
1636 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1642 // x = (a != k)? x : y
1644 // if (a == k) x = y
1646 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1647 CPU16Regs:$x, CPU16Regs:$y),
1648 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
1649 CPU16Regs:$a, immZExt16:$k)>;
1652 // When writing C code to test setxx these patterns,
1653 // some will be transformed into
1654 // other things. So we test using C code but using -O3 and -O0
1659 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
1660 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
1663 <(seteq CPU16Regs:$lhs, 0),
1664 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
1672 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1673 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1677 // For constants, llvm transforms this to:
1678 // x > (k -1) and then reverses the operands to use setlt. So this pattern
1679 // is not used now by the compiler. (Presumably checking that k-1 does not
1680 // overflow). The compiler never uses this at a the current time, due to
1681 // other optimizations.
1684 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
1685 // (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
1686 // (LiRxImmX16 1))>;
1688 // This catches the x >= -32768 case by transforming it to x > -32769
1691 <(setgt CPU16Regs:$lhs, -32769),
1692 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
1701 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
1702 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1708 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
1709 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>;
1714 def: SetCC_R16<setlt, SltCCRxRy16>;
1716 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
1722 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
1723 (SltuCCRxRy16 (LiRxImmX16 0),
1724 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1731 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1732 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1735 // this pattern will never be used because the compiler will transform
1736 // x >= k to x > (k - 1) and then use SLT
1739 // <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1740 // (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1741 // (LiRxImmX16 1))>;
1747 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1748 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1754 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1755 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1760 def: SetCC_R16<setult, SltuCCRxRy16>;
1762 def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1764 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1765 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
1769 def : Mips16Pat<(MipsHi tglobaladdr:$in),
1770 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>;
1771 def : Mips16Pat<(MipsHi tjumptable:$in),
1772 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>;
1773 def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
1774 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
1777 class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1778 Mips16Pat<(MipsWrapper RC:$gp, node:$in),
1779 (ADDiuOp RC:$gp, node:$in)>;
1782 def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>;
1783 def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
1785 def : Mips16Pat<(i32 (extloadi8 addr16:$src)),
1786 (LbuRxRyOffMemX16 addr16:$src)>;
1787 def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
1788 (LhuRxRyOffMemX16 addr16:$src)>;