1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
18 ComplexPattern<iPTR, 3, "selectAddr16", [frameindex], [SDNPWantParent]>;
22 def mem16 : Operand<i32> {
23 let PrintMethod = "printMemOperand";
24 let MIOperandInfo = (ops CPU16Regs, simm16, CPU16RegsPlusSP);
25 let EncoderMethod = "getMemEncoding";
28 def mem16_ea : Operand<i32> {
29 let PrintMethod = "printMemOperandEA";
30 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
31 let EncoderMethod = "getMemEncoding";
36 // I8 instruction format
39 class FI816_ins_base<bits<3> _func, string asmstr,
40 string asmstr2, InstrItinClass itin>:
41 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
45 class FI816_SP_ins<bits<3> _func, string asmstr,
47 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
50 // RI instruction format
54 class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
56 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
57 !strconcat(asmstr, asmstr2), [], itin>;
59 class FRI16_ins<bits<5> op, string asmstr,
61 FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
63 class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2,
65 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
66 !strconcat(asmstr, asmstr2), [], itin>;
68 class FRI16R_ins<bits<5> op, string asmstr,
70 FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
72 class F2RI16_ins<bits<5> _op, string asmstr,
74 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
75 !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
76 let Constraints = "$rx_ = $rx";
79 class FRI16_B_ins<bits<5> _op, string asmstr,
81 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
82 !strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>;
84 // Compare a register and immediate and place result in CC
87 // EXT-CCRR Instruction format
89 class FEXT_CCRXI16_ins<string asmstr>:
90 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
91 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
93 let usesCustomInserter = 1;
96 // JAL and JALX instruction format
98 class FJAL16_ins<bits<1> _X, string asmstr,
100 FJAL16<_X, (outs), (ins simm20:$imm),
101 !strconcat(asmstr, "\t$imm\n\tnop"),[],
106 // EXT-I instruction format
108 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
109 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
110 !strconcat(asmstr, "\t$imm16"),[], itin>;
113 // EXT-I8 instruction format
116 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
117 string asmstr2, InstrItinClass itin>:
118 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
121 class FEXT_I816_ins<bits<3> _func, string asmstr,
122 InstrItinClass itin>:
123 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
125 class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
126 InstrItinClass itin>:
127 FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>;
130 // Assembler formats in alphabetical order.
131 // Natural and pseudos are mixed together.
133 // Compare two registers and place result in CC
134 // Implicit use of T8
136 // CC-RR Instruction format
138 class FCCRR16_ins<string asmstr> :
139 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
140 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
142 let usesCustomInserter = 1;
146 // EXT-RI instruction format
149 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
150 InstrItinClass itin>:
151 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
152 !strconcat(asmstr, asmstr2), [], itin>;
154 class FEXT_RI16_ins<bits<5> _op, string asmstr,
155 InstrItinClass itin>:
156 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
158 class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2,
159 InstrItinClass itin>:
160 FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm),
161 !strconcat(asmstr, asmstr2), [], itin>;
163 class FEXT_RI16R_ins<bits<5> _op, string asmstr,
164 InstrItinClass itin>:
165 FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
167 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
168 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
170 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
171 InstrItinClass itin>:
172 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
173 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
175 class FEXT_RI16_TCP_ins<bits<5> _op, string asmstr,
176 InstrItinClass itin>:
177 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm),
178 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
180 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
181 InstrItinClass itin>:
182 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
183 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
184 let Constraints = "$rx_ = $rx";
188 // this has an explicit sp argument that we ignore to work around a problem
190 class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
191 InstrItinClass itin>:
192 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
193 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
195 class FEXT_RI16_SP_Store_explicit_ins<bits<5> _op, string asmstr,
196 InstrItinClass itin>:
197 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm),
198 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
201 // EXT-RRI instruction format
204 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
205 InstrItinClass itin>:
206 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
207 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
209 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
210 InstrItinClass itin>:
211 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
212 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
216 // EXT-RRI-A instruction format
219 class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
220 InstrItinClass itin>:
221 FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
222 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
225 // EXT-SHIFT instruction format
227 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
228 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa),
229 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
234 class FEXT_T8I816_ins<string asmstr, string asmstr2>:
236 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
237 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
238 !strconcat(asmstr, "\t$imm"))),[]> {
240 let usesCustomInserter = 1;
246 class FEXT_T8I8I16_ins<string asmstr, string asmstr2>:
248 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
249 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
250 !strconcat(asmstr, "\t$targ"))), []> {
252 let usesCustomInserter = 1;
258 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
260 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
261 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32),
262 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
265 // I8_MOV32R instruction format (used only by MOV32R instruction)
268 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
269 FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz),
270 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
273 // This are pseudo formats for multiply
274 // This first one can be changed to non pseudo now.
278 class FMULT16_ins<string asmstr, InstrItinClass itin> :
279 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
280 !strconcat(asmstr, "\t$rx, $ry"), []>;
285 class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
286 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
287 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
292 // RR-type instruction format
295 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
296 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
297 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
300 class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> :
301 FRRBreak16<(outs), (ins), asmstr, [], itin> {
305 class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> :
306 FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
307 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
310 class FRRTR16_ins<string asmstr> :
311 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
312 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
315 // maybe refactor but need a $zero as a dummy first parameter
317 class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
318 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
319 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
321 class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
322 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
323 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
326 class FRR16_M_ins<bits<5> f, string asmstr,
327 InstrItinClass itin> :
328 FRR16<f, (outs CPU16Regs:$rx), (ins),
329 !strconcat(asmstr, "\t$rx"), [], itin>;
331 class FRxRxRy16_ins<bits<5> f, string asmstr,
332 InstrItinClass itin> :
333 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
334 !strconcat(asmstr, "\t$rz, $ry"),
336 let Constraints = "$rx = $rz";
340 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
341 string asmstr, InstrItinClass itin>:
342 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
346 class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
347 string asmstr, InstrItinClass itin>:
348 FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
349 !strconcat(asmstr, "\t $rx"), [], itin> ;
352 <bits<5> _funct, bits<3> _subfunc,
353 string asmstr, InstrItinClass itin>:
354 FRR_SF16<_funct, _subfunc, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_),
355 !strconcat(asmstr, "\t $rx"),
357 let Constraints = "$rx_ = $rx";
360 // RRR-type instruction format
363 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
364 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
365 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
368 // These Sel patterns support the generation of conditional move
369 // pseudo instructions.
371 // The nomenclature uses the components making up the pseudo and may
372 // be a bit counter intuitive when compared with the end result we seek.
373 // For example using a bqez in the example directly below results in the
374 // conditional move being done if the tested register is not zero.
375 // I considered in easier to check by keeping the pseudo consistent with
376 // it's components but it could have been done differently.
378 // The simplest case is when can test and operand directly and do the
379 // conditional move based on a simple mips16 conditional
380 // branch instruction.
382 // if $op == beqz or bnez:
387 // if $op == beqz, then if $rt != 0, then the conditional assignment
388 // $rd = $rs is done.
390 // if $op == bnez, then if $rt == 0, then the conditional assignment
391 // $rd = $rs is done.
393 // So this pseudo class only has one operand, i.e. op
395 class Sel<string op>:
396 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
398 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> {
399 //let isCodeGenOnly=1;
400 let Constraints = "$rd = $rd_";
401 let usesCustomInserter = 1;
405 // The next two instruction classes allow for an operand which tests
406 // two operands and returns a value in register T8 and
407 //then does a conditional branch based on the value of T8
410 // op2 can be cmpi or slti/sltiu
411 // op1 can bteqz or btnez
412 // the operands for op2 are a register and a signed constant
414 // $op2 $t, $imm ;test register t and branch conditionally
415 // $op1 .+4 ;op1 is a conditional branch
419 class SeliT<string op1, string op2>:
420 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
421 CPU16Regs:$rl, simm16:$imm),
423 !strconcat("\t$rl, $imm\n\t",
424 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
426 let Constraints = "$rd = $rd_";
427 let usesCustomInserter = 1;
431 // op2 can be cmp or slt/sltu
432 // op1 can be bteqz or btnez
433 // the operands for op2 are two registers
434 // op1 is a conditional branch
437 // $op2 $rl, $rr ;test registers rl,rr
438 // $op1 .+4 ;op2 is a conditional branch
442 class SelT<string op1, string op2>:
443 MipsPseudo16<(outs CPU16Regs:$rd_),
444 (ins CPU16Regs:$rd, CPU16Regs:$rs,
445 CPU16Regs:$rl, CPU16Regs:$rr),
447 !strconcat("\t$rl, $rr\n\t",
448 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
450 let Constraints = "$rd = $rd_";
451 let usesCustomInserter = 1;
457 def imm32: Operand<i32>;
460 MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
463 MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm, imm32:$constid),
464 "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
468 // Some general instruction class info
472 class ArithLogic16Defs<bit isCom=0> {
474 bit isCommutable = isCom;
475 bit isReMaterializable = 1;
476 bit neverHasSideEffects = 1;
481 bit isTerminator = 1;
487 bit isTerminator = 1;
500 // Format: ADDIU rx, immediate MIPS16e
501 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
502 // To add a constant to a 32-bit integer.
504 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
506 def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>,
507 ArithLogic16Defs<0> {
508 let AddedComplexity = 5;
510 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
511 ArithLogic16Defs<0> {
512 let isCodeGenOnly = 1;
515 def AddiuRxRyOffMemX16:
516 FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>;
520 // Format: ADDIU rx, pc, immediate MIPS16e
521 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
522 // To add a constant to the program counter.
524 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
527 // Format: ADDIU sp, immediate MIPS16e
528 // Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
529 // To add a constant to the stack pointer.
532 : FI816_SP_ins<0b011, "addiu", IIAlu> {
535 let AddedComplexity = 5;
539 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
545 // Format: ADDU rz, rx, ry MIPS16e
546 // Purpose: Add Unsigned Word (3-Operand)
547 // To add 32-bit integers.
550 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
553 // Format: AND rx, ry MIPS16e
555 // To do a bitwise logical AND.
557 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
561 // Format: BEQZ rx, offset MIPS16e
562 // Purpose: Branch on Equal to Zero
563 // To test a GPR then do a PC-relative conditional branch.
565 def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
569 // Format: BEQZ rx, offset MIPS16e
570 // Purpose: Branch on Equal to Zero (Extended)
571 // To test a GPR then do a PC-relative conditional branch.
573 def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
575 // Format: B offset MIPS16e
576 // Purpose: Unconditional Branch
577 // To do an unconditional PC-relative branch.
579 def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
582 // Format: BNEZ rx, offset MIPS16e
583 // Purpose: Branch on Not Equal to Zero
584 // To test a GPR then do a PC-relative conditional branch.
586 def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
589 // Format: BNEZ rx, offset MIPS16e
590 // Purpose: Branch on Not Equal to Zero (Extended)
591 // To test a GPR then do a PC-relative conditional branch.
593 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
597 //Format: BREAK immediate
598 // Purpose: Breakpoint
599 // To cause a Breakpoint exception.
601 def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>;
603 // Format: BTEQZ offset MIPS16e
604 // Purpose: Branch on T Equal to Zero (Extended)
605 // To test special register T then do a PC-relative conditional branch.
607 def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
611 def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16;
613 def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">,
616 def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16;
618 def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;
620 def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16;
622 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
626 // Format: BTNEZ offset MIPS16e
627 // Purpose: Branch on T Not Equal to Zero (Extended)
628 // To test special register T then do a PC-relative conditional branch.
630 def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 {
634 def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16;
636 def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16;
638 def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16;
640 def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;
642 def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16;
644 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
648 // Format: CMP rx, ry MIPS16e
650 // To compare the contents of two GPRs.
652 def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> {
657 // Format: CMPI rx, immediate MIPS16e
658 // Purpose: Compare Immediate
659 // To compare a constant with the contents of a GPR.
661 def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> {
666 // Format: CMPI rx, immediate MIPS16e
667 // Purpose: Compare Immediate (Extended)
668 // To compare a constant with the contents of a GPR.
670 def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> {
676 // Format: DIV rx, ry MIPS16e
677 // Purpose: Divide Word
678 // To divide 32-bit signed integers.
680 def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
681 let Defs = [HI0, LO0];
685 // Format: DIVU rx, ry MIPS16e
686 // Purpose: Divide Unsigned Word
687 // To divide 32-bit unsigned integers.
689 def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
690 let Defs = [HI0, LO0];
693 // Format: JAL target MIPS16e
694 // Purpose: Jump and Link
695 // To execute a procedure call within the current 256 MB-aligned
696 // region and preserve the current ISA.
699 def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
700 let hasDelaySlot = 0; // not true, but we add the nop for now
705 // Format: JR ra MIPS16e
706 // Purpose: Jump Register Through Register ra
707 // To execute a branch to the instruction address in the return
711 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
713 let isIndirectBranch = 1;
714 let hasDelaySlot = 1;
719 def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> {
721 let isIndirectBranch = 1;
726 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
728 let isIndirectBranch = 1;
733 // Format: LB ry, offset(rx) MIPS16e
734 // Purpose: Load Byte (Extended)
735 // To load a byte from memory as a signed value.
737 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{
738 let isCodeGenOnly = 1;
742 // Format: LBU ry, offset(rx) MIPS16e
743 // Purpose: Load Byte Unsigned (Extended)
744 // To load a byte from memory as a unsigned value.
746 def LbuRxRyOffMemX16:
747 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad {
748 let isCodeGenOnly = 1;
752 // Format: LH ry, offset(rx) MIPS16e
753 // Purpose: Load Halfword signed (Extended)
754 // To load a halfword from memory as a signed value.
756 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{
757 let isCodeGenOnly = 1;
761 // Format: LHU ry, offset(rx) MIPS16e
762 // Purpose: Load Halfword unsigned (Extended)
763 // To load a halfword from memory as an unsigned value.
765 def LhuRxRyOffMemX16:
766 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad {
767 let isCodeGenOnly = 1;
771 // Format: LI rx, immediate MIPS16e
772 // Purpose: Load Immediate
773 // To load a constant into a GPR.
775 def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>;
778 // Format: LI rx, immediate MIPS16e
779 // Purpose: Load Immediate (Extended)
780 // To load a constant into a GPR.
782 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
784 def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIAlu> {
785 let isCodeGenOnly = 1;
789 // Format: LW ry, offset(rx) MIPS16e
790 // Purpose: Load Word (Extended)
791 // To load a word from memory as a signed value.
793 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{
794 let isCodeGenOnly = 1;
797 // Format: LW rx, offset(sp) MIPS16e
798 // Purpose: Load Word (SP-Relative, Extended)
799 // To load an SP-relative word from memory as a signed value.
801 def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10010, "lw", IILoad>, MayLoad{
805 def LwRxPcTcpX16: FEXT_RI16_TCP_ins<0b10110, "lw", IILoad>, MayLoad;
807 // Format: MOVE r32, rz MIPS16e
809 // To move the contents of a GPR to a GPR.
811 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
814 // Format: MOVE ry, r32 MIPS16e
816 // To move the contents of a GPR to a GPR.
818 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
821 // Format: MFHI rx MIPS16e
822 // Purpose: Move From HI Register
823 // To copy the special purpose HI register to a GPR.
825 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
827 let neverHasSideEffects = 1;
831 // Format: MFLO rx MIPS16e
832 // Purpose: Move From LO Register
833 // To copy the special purpose LO register to a GPR.
835 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
837 let neverHasSideEffects = 1;
841 // Pseudo Instruction for mult
843 def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
844 let isCommutable = 1;
845 let neverHasSideEffects = 1;
846 let Defs = [HI0, LO0];
849 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
850 let isCommutable = 1;
851 let neverHasSideEffects = 1;
852 let Defs = [HI0, LO0];
856 // Format: MULT rx, ry MIPS16e
857 // Purpose: Multiply Word
858 // To multiply 32-bit signed integers.
860 def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
861 let isCommutable = 1;
862 let neverHasSideEffects = 1;
863 let Defs = [HI0, LO0];
867 // Format: MULTU rx, ry MIPS16e
868 // Purpose: Multiply Unsigned Word
869 // To multiply 32-bit unsigned integers.
871 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
872 let isCommutable = 1;
873 let neverHasSideEffects = 1;
874 let Defs = [HI0, LO0];
878 // Format: NEG rx, ry MIPS16e
880 // To negate an integer value.
882 def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
885 // Format: NOT rx, ry MIPS16e
887 // To complement an integer value
889 def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
892 // Format: OR rx, ry MIPS16e
894 // To do a bitwise logical OR.
896 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
899 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
900 // (All args are optional) MIPS16e
901 // Purpose: Restore Registers and Deallocate Stack Frame
902 // To deallocate a stack frame before exit from a subroutine,
903 // restoring return address and static registers, and adjusting
907 // fixed form for restoring RA and the frame
908 // for direct object emitter, encoding needs to be adjusted for the
911 let ra=1, s=0,s0=1,s1=1 in
913 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
914 "restore\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IILoad >, MayLoad {
915 let isCodeGenOnly = 1;
916 let Defs = [S0, S1, S2, RA, SP];
920 // Use Restore to increment SP since SP is not a Mip 16 register, this
921 // is an easy way to do that which does not require a register.
923 let ra=0, s=0,s0=0,s1=0 in
925 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
926 "restore\t$frame_size", [], IILoad >, MayLoad {
927 let isCodeGenOnly = 1;
933 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
935 // Purpose: Save Registers and Set Up Stack Frame
936 // To set up a stack frame on entry to a subroutine,
937 // saving return address and static registers, and adjusting stack
939 let ra=1, s=1,s0=1,s1=1 in
941 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
942 "save\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IIStore >, MayStore {
943 let isCodeGenOnly = 1;
944 let Uses = [RA, SP, S0, S1, S2];
949 // Use Save to decrement the SP by a constant since SP is not
950 // a Mips16 register.
952 let ra=0, s=0,s0=0,s1=0 in
954 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
955 "save\t$frame_size", [], IIStore >, MayStore {
956 let isCodeGenOnly = 1;
961 // Format: SB ry, offset(rx) MIPS16e
962 // Purpose: Store Byte (Extended)
963 // To store a byte to memory.
966 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
969 // Format: SEB rx MIPS16e
970 // Purpose: Sign-Extend Byte
971 // Sign-extend least significant byte in register rx.
974 : FRR_SF16_ins<0b10001, 0b100, "seb", IIAlu>;
977 // Format: SEH rx MIPS16e
978 // Purpose: Sign-Extend Halfword
979 // Sign-extend least significant word in register rx.
982 : FRR_SF16_ins<0b10001, 0b101, "seh", IIAlu>;
985 // The Sel(T) instructions are pseudos
986 // T means that they use T8 implicitly.
989 // Format: SelBeqZ rd, rs, rt
990 // Purpose: if rt==0, do nothing
993 def SelBeqZ: Sel<"beqz">;
996 // Format: SelTBteqZCmp rd, rs, rl, rr
997 // Purpose: b = Cmp rl, rr.
998 // If b==0 then do nothing.
999 // if b!=0 then rd = rs
1001 def SelTBteqZCmp: SelT<"bteqz", "cmp">;
1004 // Format: SelTBteqZCmpi rd, rs, rl, rr
1005 // Purpose: b = Cmpi rl, imm.
1006 // If b==0 then do nothing.
1007 // if b!=0 then rd = rs
1009 def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">;
1012 // Format: SelTBteqZSlt rd, rs, rl, rr
1013 // Purpose: b = Slt rl, rr.
1014 // If b==0 then do nothing.
1015 // if b!=0 then rd = rs
1017 def SelTBteqZSlt: SelT<"bteqz", "slt">;
1020 // Format: SelTBteqZSlti rd, rs, rl, rr
1021 // Purpose: b = Slti rl, imm.
1022 // If b==0 then do nothing.
1023 // if b!=0 then rd = rs
1025 def SelTBteqZSlti: SeliT<"bteqz", "slti">;
1028 // Format: SelTBteqZSltu rd, rs, rl, rr
1029 // Purpose: b = Sltu rl, rr.
1030 // If b==0 then do nothing.
1031 // if b!=0 then rd = rs
1033 def SelTBteqZSltu: SelT<"bteqz", "sltu">;
1036 // Format: SelTBteqZSltiu rd, rs, rl, rr
1037 // Purpose: b = Sltiu rl, imm.
1038 // If b==0 then do nothing.
1039 // if b!=0 then rd = rs
1041 def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">;
1044 // Format: SelBnez rd, rs, rt
1045 // Purpose: if rt!=0, do nothing
1048 def SelBneZ: Sel<"bnez">;
1051 // Format: SelTBtneZCmp rd, rs, rl, rr
1052 // Purpose: b = Cmp rl, rr.
1053 // If b!=0 then do nothing.
1054 // if b0=0 then rd = rs
1056 def SelTBtneZCmp: SelT<"btnez", "cmp">;
1059 // Format: SelTBtnezCmpi rd, rs, rl, rr
1060 // Purpose: b = Cmpi rl, imm.
1061 // If b!=0 then do nothing.
1062 // if b==0 then rd = rs
1064 def SelTBtneZCmpi: SeliT<"btnez", "cmpi">;
1067 // Format: SelTBtneZSlt rd, rs, rl, rr
1068 // Purpose: b = Slt rl, rr.
1069 // If b!=0 then do nothing.
1070 // if b==0 then rd = rs
1072 def SelTBtneZSlt: SelT<"btnez", "slt">;
1075 // Format: SelTBtneZSlti rd, rs, rl, rr
1076 // Purpose: b = Slti rl, imm.
1077 // If b!=0 then do nothing.
1078 // if b==0 then rd = rs
1080 def SelTBtneZSlti: SeliT<"btnez", "slti">;
1083 // Format: SelTBtneZSltu rd, rs, rl, rr
1084 // Purpose: b = Sltu rl, rr.
1085 // If b!=0 then do nothing.
1086 // if b==0 then rd = rs
1088 def SelTBtneZSltu: SelT<"btnez", "sltu">;
1091 // Format: SelTBtneZSltiu rd, rs, rl, rr
1092 // Purpose: b = Slti rl, imm.
1093 // If b!=0 then do nothing.
1094 // if b==0 then rd = rs
1096 def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
1099 // Format: SH ry, offset(rx) MIPS16e
1100 // Purpose: Store Halfword (Extended)
1101 // To store a halfword to memory.
1103 def ShRxRyOffMemX16:
1104 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore;
1107 // Format: SLL rx, ry, sa MIPS16e
1108 // Purpose: Shift Word Left Logical (Extended)
1109 // To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
1111 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
1114 // Format: SLLV ry, rx MIPS16e
1115 // Purpose: Shift Word Left Logical Variable
1116 // To execute a left-shift of a word by a variable number of bits.
1118 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
1120 // Format: SLTI rx, immediate MIPS16e
1121 // Purpose: Set on Less Than Immediate
1122 // To record the result of a less-than comparison with a constant.
1125 def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> {
1130 // Format: SLTI rx, immediate MIPS16e
1131 // Purpose: Set on Less Than Immediate (Extended)
1132 // To record the result of a less-than comparison with a constant.
1135 def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> {
1139 def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
1141 // Format: SLTIU rx, immediate MIPS16e
1142 // Purpose: Set on Less Than Immediate Unsigned
1143 // To record the result of a less-than comparison with a constant.
1146 def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> {
1151 // Format: SLTI rx, immediate MIPS16e
1152 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1153 // To record the result of a less-than comparison with a constant.
1156 def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> {
1160 // Format: SLTIU rx, immediate MIPS16e
1161 // Purpose: Set on Less Than Immediate Unsigned (Extended)
1162 // To record the result of a less-than comparison with a constant.
1164 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
1167 // Format: SLT rx, ry MIPS16e
1168 // Purpose: Set on Less Than
1169 // To record the result of a less-than comparison.
1171 def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{
1175 def SltCCRxRy16: FCCRR16_ins<"slt">;
1177 // Format: SLTU rx, ry MIPS16e
1178 // Purpose: Set on Less Than Unsigned
1179 // To record the result of an unsigned less-than comparison.
1181 def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{
1185 def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
1186 let isCodeGenOnly=1;
1191 def SltuCCRxRy16: FCCRR16_ins<"sltu">;
1193 // Format: SRAV ry, rx MIPS16e
1194 // Purpose: Shift Word Right Arithmetic Variable
1195 // To execute an arithmetic right-shift of a word by a variable
1198 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
1202 // Format: SRA rx, ry, sa MIPS16e
1203 // Purpose: Shift Word Right Arithmetic (Extended)
1204 // To execute an arithmetic right-shift of a word by a fixed
1205 // number of bits—1 to 8 bits.
1207 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
1211 // Format: SRLV ry, rx MIPS16e
1212 // Purpose: Shift Word Right Logical Variable
1213 // To execute a logical right-shift of a word by a variable
1216 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
1220 // Format: SRL rx, ry, sa MIPS16e
1221 // Purpose: Shift Word Right Logical (Extended)
1222 // To execute a logical right-shift of a word by a fixed
1223 // number of bits—1 to 31 bits.
1225 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
1228 // Format: SUBU rz, rx, ry MIPS16e
1229 // Purpose: Subtract Unsigned Word
1230 // To subtract 32-bit integers
1232 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
1235 // Format: SW ry, offset(rx) MIPS16e
1236 // Purpose: Store Word (Extended)
1237 // To store a word to memory.
1239 def SwRxRyOffMemX16:
1240 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore;
1243 // Format: SW rx, offset(sp) MIPS16e
1244 // Purpose: Store Word rx (SP-Relative)
1245 // To store an SP-relative word to memory.
1247 def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins
1248 <0b11010, "sw", IIStore>, MayStore;
1252 // Format: XOR rx, ry MIPS16e
1254 // To do a bitwise logical XOR.
1256 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
1258 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
1259 let Predicates = [InMips16Mode];
1262 // Unary Arith/Logic
1264 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1265 Mips16Pat<(OpNode CPU16Regs:$r),
1268 def: ArithLogicU_pat<not, NotRxRy16>;
1269 def: ArithLogicU_pat<ineg, NegRxRy16>;
1271 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1272 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1273 (I CPU16Regs:$l, CPU16Regs:$r)>;
1275 def: ArithLogic16_pat<add, AdduRxRyRz16>;
1276 def: ArithLogic16_pat<and, AndRxRxRy16>;
1277 def: ArithLogic16_pat<mul, MultRxRyRz16>;
1278 def: ArithLogic16_pat<or, OrRxRxRy16>;
1279 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
1280 def: ArithLogic16_pat<xor, XorRxRxRy16>;
1282 // Arithmetic and logical instructions with 2 register operands.
1284 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
1285 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1286 (I CPU16Regs:$in, imm_type:$imm)>;
1288 def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>;
1289 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
1290 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
1291 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
1292 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
1294 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1295 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1296 (I CPU16Regs:$r, CPU16Regs:$ra)>;
1298 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
1299 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
1300 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
1302 class LoadM16_pat<PatFrag OpNode, Instruction I> :
1303 Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
1305 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
1306 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
1307 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
1308 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
1309 def: LoadM16_pat<load, LwRxRyOffMemX16>;
1311 class StoreM16_pat<PatFrag OpNode, Instruction I> :
1312 Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr),
1313 (I CPU16Regs:$r, addr16:$addr)>;
1315 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
1316 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
1317 def: StoreM16_pat<store, SwRxRyOffMemX16>;
1319 // Unconditional branch
1320 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
1321 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
1322 let Predicates = [InMips16Mode];
1325 def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1326 (Jal16 tglobaladdr:$dst)>;
1328 def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)),
1329 (Jal16 texternalsym:$dst)>;
1333 (brind CPU16Regs:$rs),
1334 (JrcRx16 CPU16Regs:$rs)>;
1336 // Jump and Link (Call)
1337 let isCall=1, hasDelaySlot=0 in
1339 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
1340 "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
1343 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
1344 hasExtraSrcRegAllocReq = 1 in
1345 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
1350 class SetCC_R16<PatFrag cond_op, Instruction I>:
1351 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
1352 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
1354 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
1355 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
1356 (I CPU16Regs:$rx, imm_type:$imm16)>;
1359 def: Mips16Pat<(i32 addr16:$addr),
1360 (AddiuRxRyOffMemX16 addr16:$addr)>;
1363 // Large (>16 bit) immediate loads
1364 def : Mips16Pat<(i32 imm:$imm), (LwConstant32 imm:$imm, -1)>;
1366 // Carry MipsPatterns
1367 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
1368 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1369 def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
1370 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
1371 def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
1372 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
1375 // Some branch conditional patterns are not generated by llvm at this time.
1376 // Some are for seemingly arbitrary reasons not used: i.e. with signed number
1377 // comparison they are used and for unsigned a different pattern is used.
1378 // I am pushing upstream from the full mips16 port and it seemed that I needed
1379 // these earlier and the mips32 port has these but now I cannot create test
1380 // cases that use these patterns. While I sort this all out I will leave these
1381 // extra patterns commented out and if I can be sure they are really not used,
1382 // I will delete the code. I don't want to check the code in uncommented without
1383 // a valid test case. In some cases, the compiler is generating patterns with
1384 // setcc instead and earlier I had implemented setcc first so may have masked
1385 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
1386 // figure out how to enable the brcond patterns or else possibly new
1387 // combinations of of brcond and setcc.
1393 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1394 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1399 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1400 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1404 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1405 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16)
1409 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1412 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1413 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1420 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1421 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1425 // never called because compiler transforms a >= k to a > (k-1)
1427 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1428 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1435 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1436 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1440 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1441 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1448 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1449 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1456 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1457 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1461 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1462 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1466 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1467 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1471 // This needs to be there but I forget which code will generate it
1474 <(brcond CPU16Regs:$rx, bb:$targ16),
1475 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1484 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1485 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1492 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1493 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1501 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1502 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1505 def: UncondBranch16_pat<br, BimmX16>;
1508 def: Mips16Pat<(i32 immSExt16:$in),
1509 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
1511 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
1517 <(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry),
1518 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1524 <(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry),
1525 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1530 // if !(a < b) x = y
1532 def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1533 CPU16Regs:$x, CPU16Regs:$y),
1534 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1535 CPU16Regs:$a, CPU16Regs:$b)>;
1542 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1543 CPU16Regs:$x, CPU16Regs:$y),
1544 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
1545 CPU16Regs:$b, CPU16Regs:$a)>;
1550 // if !(a < b) x = y;
1553 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
1554 CPU16Regs:$x, CPU16Regs:$y),
1555 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1556 CPU16Regs:$a, CPU16Regs:$b)>;
1563 def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
1564 CPU16Regs:$x, CPU16Regs:$y),
1565 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
1566 CPU16Regs:$b, CPU16Regs:$a)>;
1570 // due to an llvm optimization, i don't think that this will ever
1571 // be used. This is transformed into x = (a > k-1)?x:y
1576 // (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1577 // CPU16Regs:$T, CPU16Regs:$F),
1578 // (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
1579 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1582 // (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
1583 // CPU16Regs:$T, CPU16Regs:$F),
1584 // (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
1585 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1590 // if !(a < k) x = y;
1593 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1594 CPU16Regs:$x, CPU16Regs:$y),
1595 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
1596 CPU16Regs:$a, immSExt16:$b)>;
1602 // x = (a <= b)? x : y
1606 def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
1607 CPU16Regs:$x, CPU16Regs:$y),
1608 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1609 CPU16Regs:$b, CPU16Regs:$a)>;
1613 // x = (a <= b)? x : y
1617 def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
1618 CPU16Regs:$x, CPU16Regs:$y),
1619 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1620 CPU16Regs:$b, CPU16Regs:$a)>;
1624 // x = (a == b)? x : y
1626 // if (a != b) x = y
1628 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
1629 CPU16Regs:$x, CPU16Regs:$y),
1630 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
1631 CPU16Regs:$b, CPU16Regs:$a)>;
1635 // x = (a == 0)? x : y
1637 // if (a != 0) x = y
1639 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
1640 CPU16Regs:$x, CPU16Regs:$y),
1641 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
1647 // x = (a == k)? x : y
1649 // if (a != k) x = y
1651 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
1652 CPU16Regs:$x, CPU16Regs:$y),
1653 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
1654 CPU16Regs:$a, immZExt16:$k)>;
1659 // x = (a != b)? x : y
1661 // if (a == b) x = y
1664 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1665 CPU16Regs:$x, CPU16Regs:$y),
1666 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
1667 CPU16Regs:$b, CPU16Regs:$a)>;
1671 // x = (a != 0)? x : y
1673 // if (a == 0) x = y
1675 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1676 CPU16Regs:$x, CPU16Regs:$y),
1677 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1685 def : Mips16Pat<(select CPU16Regs:$a,
1686 CPU16Regs:$x, CPU16Regs:$y),
1687 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1693 // x = (a != k)? x : y
1695 // if (a == k) x = y
1697 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1698 CPU16Regs:$x, CPU16Regs:$y),
1699 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
1700 CPU16Regs:$a, immZExt16:$k)>;
1703 // When writing C code to test setxx these patterns,
1704 // some will be transformed into
1705 // other things. So we test using C code but using -O3 and -O0
1710 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
1711 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
1714 <(seteq CPU16Regs:$lhs, 0),
1715 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
1723 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1724 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1728 // For constants, llvm transforms this to:
1729 // x > (k -1) and then reverses the operands to use setlt. So this pattern
1730 // is not used now by the compiler. (Presumably checking that k-1 does not
1731 // overflow). The compiler never uses this at a the current time, due to
1732 // other optimizations.
1735 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
1736 // (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
1737 // (LiRxImmX16 1))>;
1739 // This catches the x >= -32768 case by transforming it to x > -32769
1742 <(setgt CPU16Regs:$lhs, -32769),
1743 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
1752 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
1753 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1759 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
1760 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>;
1765 def: SetCC_R16<setlt, SltCCRxRy16>;
1767 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
1773 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
1774 (SltuCCRxRy16 (LiRxImmX16 0),
1775 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1782 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1783 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1786 // this pattern will never be used because the compiler will transform
1787 // x >= k to x > (k - 1) and then use SLT
1790 // <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1791 // (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1792 // (LiRxImmX16 1))>;
1798 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1799 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1805 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1806 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1811 def: SetCC_R16<setult, SltuCCRxRy16>;
1813 def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1815 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1816 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
1819 def : Mips16Pat<(MipsHi tblockaddress:$in),
1820 (SllX16 (LiRxImmX16 tblockaddress:$in), 16)>;
1821 def : Mips16Pat<(MipsHi tglobaladdr:$in),
1822 (SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>;
1823 def : Mips16Pat<(MipsHi tjumptable:$in),
1824 (SllX16 (LiRxImmX16 tjumptable:$in), 16)>;
1825 def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
1826 (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
1828 def : Mips16Pat<(MipsLo tblockaddress:$in), (LiRxImmX16 tblockaddress:$in)>;
1831 class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1832 Mips16Pat<(MipsWrapper RC:$gp, node:$in),
1833 (ADDiuOp RC:$gp, node:$in)>;
1836 def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>;
1837 def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
1839 def : Mips16Pat<(i32 (extloadi8 addr16:$src)),
1840 (LbuRxRyOffMemX16 addr16:$src)>;
1841 def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
1842 (LhuRxRyOffMemX16 addr16:$src)>;
1844 def: Mips16Pat<(trap), (Break16)>;
1846 def : Mips16Pat<(sext_inreg CPU16Regs:$val, i8),
1847 (SebRx16 CPU16Regs:$val)>;
1849 def : Mips16Pat<(sext_inreg CPU16Regs:$val, i16),
1850 (SehRx16 CPU16Regs:$val)>;
1854 (outs CPU16Regs:$rh, CPU16Regs:$rl),
1855 (ins simm16:$immHi, simm16:$immLo),
1856 ".align 2\n\tli\t$rh, $immHi\n\taddiu\t$rl, $$pc, $immLo\n ",[]> ;
1858 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
1859 def cpinst_operand : Operand<i32> {
1860 // let PrintMethod = "printCPInstOperand";
1863 // CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1864 // the function. The first operand is the ID# for this instruction, the second
1865 // is the index into the MachineConstantPool that this is, the third is the
1866 // size in bytes of this constant pool entry.
1868 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1869 def CONSTPOOL_ENTRY :
1870 MipsPseudo16<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1871 i32imm:$size), "foo", []>;