1 //===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips16 instructions.
12 //===----------------------------------------------------------------------===//
17 def mem16 : Operand<i32> {
18 let PrintMethod = "printMemOperand";
19 let MIOperandInfo = (ops CPU16Regs, simm16);
20 let EncoderMethod = "getMemEncoding";
24 // Compare a register and immediate and place result in CC
27 // EXT-CCRR Instruction format
29 class FEXT_CCRXI16_ins<bits<5> _op, string asmstr,
31 FEXT_RI16<_op, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
32 !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), [], itin> {
37 // EXT-I instruction format
39 class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
40 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
41 !strconcat(asmstr, "\t$imm16"),[], itin>;
44 // EXT-I8 instruction format
47 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
48 string asmstr2, InstrItinClass itin>:
49 FEXT_I816<_func, (outs), (ins uimm16:$imm), !strconcat(asmstr, asmstr2),
52 class FEXT_I816_ins<bits<3> _func, string asmstr,
54 FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
57 // Assembler formats in alphabetical order.
58 // Natural and pseudos are mixed together.
60 // Compare two registers and place result in CC
63 // CC-RR Instruction format
65 class FCCRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
66 FRR16<f, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
67 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), [], itin> {
72 // EXT-RI instruction format
75 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
77 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
78 !strconcat(asmstr, asmstr2), [], itin>;
80 class FEXT_RI16_ins<bits<5> _op, string asmstr,
82 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
84 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
85 FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
87 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
89 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
90 !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
92 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
94 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
95 !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
96 let Constraints = "$rx_ = $rx";
100 // this has an explicit sp argument that we ignore to work around a problem
102 class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
103 InstrItinClass itin>:
104 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
105 !strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
108 // EXT-RRI instruction format
111 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
112 InstrItinClass itin>:
113 FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
114 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
116 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
117 InstrItinClass itin>:
118 FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
119 !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
122 // EXT-SHIFT instruction format
124 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
125 FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
126 !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
131 class FEXT_T8I816_ins<bits<3> _func, string asmstr, string asmstr2,
132 InstrItinClass itin>:
133 FEXT_I816<_func, (outs),
134 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
135 !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
136 !strconcat(asmstr, "\t$imm"))),[], itin> {
143 class FEXT_T8I8I16_ins<bits<3> _func, string asmstr, string asmstr2,
144 InstrItinClass itin>:
145 FEXT_I816<_func, (outs),
146 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
147 !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
148 !strconcat(asmstr, "\t$targ"))), [], itin> {
155 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
157 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
158 FI8_MOVR3216<(outs CPU16Regs:$rz), (ins CPURegs:$r32),
159 !strconcat(asmstr, "\t$rz, $r32"), [], itin>;
162 // I8_MOV32R instruction format (used only by MOV32R instruction)
165 class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
166 FI8_MOV32R16<(outs CPURegs:$r32), (ins CPU16Regs:$rz),
167 !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
170 // This are pseudo formats for multiply
171 // This first one can be changed to non pseudo now.
175 class FMULT16_ins<string asmstr, InstrItinClass itin> :
176 MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
177 !strconcat(asmstr, "\t$rx, $ry"), []>;
182 class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
183 MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
184 !strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
189 // RR-type instruction format
192 class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
193 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
194 !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
197 class FRRTR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
198 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
199 !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), [], itin> ;
202 // maybe refactor but need a $zero as a dummy first parameter
204 class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
205 FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
206 !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
208 class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
209 FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
210 !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
213 class FRR16_M_ins<bits<5> f, string asmstr,
214 InstrItinClass itin> :
215 FRR16<f, (outs CPU16Regs:$rx), (ins),
216 !strconcat(asmstr, "\t$rx"), [], itin>;
218 class FRxRxRy16_ins<bits<5> f, string asmstr,
219 InstrItinClass itin> :
220 FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
221 !strconcat(asmstr, "\t$rz, $ry"),
223 let Constraints = "$rx = $rz";
227 class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
228 string asmstr, InstrItinClass itin>:
229 FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
233 // RRR-type instruction format
236 class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
237 FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
238 !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
241 // These Sel patterns support the generation of conditional move
242 // pseudo instructions.
244 // The nomenclature uses the components making up the pseudo and may
245 // be a bit counter intuitive when compared with the end result we seek.
246 // For example using a bqez in the example directly below results in the
247 // conditional move being done if the tested register is not zero.
248 // I considered in easier to check by keeping the pseudo consistent with
249 // it's components but it could have been done differently.
251 // The simplest case is when can test and operand directly and do the
252 // conditional move based on a simple mips16 conditional
253 // branch instruction.
255 // if $op == beqz or bnez:
260 // if $op == beqz, then if $rt != 0, then the conditional assignment
261 // $rd = $rs is done.
263 // if $op == bnez, then if $rt == 0, then the conditional assignment
264 // $rd = $rs is done.
266 // So this pseudo class only has one operand, i.e. op
268 class Sel<bits<5> f1, string op, InstrItinClass itin>:
269 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
271 !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), [], itin,
274 let Constraints = "$rd = $rd_";
278 // The next two instruction classes allow for an operand which tests
279 // two operands and returns a value in register T8 and
280 //then does a conditional branch based on the value of T8
283 // op2 can be cmpi or slti/sltiu
284 // op1 can bteqz or btnez
285 // the operands for op2 are a register and a signed constant
287 // $op2 $t, $imm ;test register t and branch conditionally
288 // $op1 .+4 ;op1 is a conditional branch
292 class SeliT<bits<5> f1, string op1, bits<5> f2, string op2,
293 InstrItinClass itin>:
294 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
295 CPU16Regs:$rl, simm16:$imm),
297 !strconcat("\t$rl, $imm\n\t",
298 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin,
301 let Constraints = "$rd = $rd_";
305 // op2 can be cmp or slt/sltu
306 // op1 can be bteqz or btnez
307 // the operands for op2 are two registers
308 // op1 is a conditional branch
311 // $op2 $rl, $rr ;test registers rl,rr
312 // $op1 .+4 ;op2 is a conditional branch
316 class SelT<bits<5> f1, string op1, bits<5> f2, string op2,
317 InstrItinClass itin>:
318 MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
319 CPU16Regs:$rl, CPU16Regs:$rr),
321 !strconcat("\t$rl, $rr\n\t",
322 !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin,
325 let Constraints = "$rd = $rd_";
330 // Some general instruction class info
334 class ArithLogic16Defs<bit isCom=0> {
336 bit isCommutable = isCom;
337 bit isReMaterializable = 1;
338 bit neverHasSideEffects = 1;
343 bit isTerminator = 1;
349 bit isTerminator = 1;
361 // Format: ADDIU rx, immediate MIPS16e
362 // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
363 // To add a constant to a 32-bit integer.
365 def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
367 def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
372 // Format: ADDIU rx, pc, immediate MIPS16e
373 // Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
374 // To add a constant to the program counter.
376 def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
378 // Format: ADDU rz, rx, ry MIPS16e
379 // Purpose: Add Unsigned Word (3-Operand)
380 // To add 32-bit integers.
383 def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
386 // Format: AND rx, ry MIPS16e
388 // To do a bitwise logical AND.
390 def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
394 // Format: BEQZ rx, offset MIPS16e
395 // Purpose: Branch on Equal to Zero (Extended)
396 // To test a GPR then do a PC-relative conditional branch.
398 def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
400 // Format: B offset MIPS16e
401 // Purpose: Unconditional Branch
402 // To do an unconditional PC-relative branch.
404 def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
407 // Format: BNEZ rx, offset MIPS16e
408 // Purpose: Branch on Not Equal to Zero (Extended)
409 // To test a GPR then do a PC-relative conditional branch.
411 def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
414 // Format: BTEQZ offset MIPS16e
415 // Purpose: Branch on T Equal to Zero (Extended)
416 // To test special register T then do a PC-relative conditional branch.
418 def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16;
420 def BteqzT8CmpX16: FEXT_T8I816_ins<0b000, "bteqz", "cmp", IIAlu>, cbranch16;
422 def BteqzT8CmpiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "cmpi", IIAlu>,
425 def BteqzT8SltX16: FEXT_T8I816_ins<0b000, "bteqz", "slt", IIAlu>, cbranch16;
427 def BteqzT8SltuX16: FEXT_T8I816_ins<0b000, "bteqz", "sltu", IIAlu>, cbranch16;
429 def BteqzT8SltiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "slti", IIAlu>, cbranch16;
431 def BteqzT8SltiuX16: FEXT_T8I8I16_ins<0b000, "bteqz", "sltiu", IIAlu>,
435 // Format: BTNEZ offset MIPS16e
436 // Purpose: Branch on T Not Equal to Zero (Extended)
437 // To test special register T then do a PC-relative conditional branch.
439 def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16;
441 def BtnezT8CmpX16: FEXT_T8I816_ins<0b000, "btnez", "cmp", IIAlu>, cbranch16;
443 def BtnezT8CmpiX16: FEXT_T8I8I16_ins<0b000, "btnez", "cmpi", IIAlu>, cbranch16;
445 def BtnezT8SltX16: FEXT_T8I816_ins<0b000, "btnez", "slt", IIAlu>, cbranch16;
447 def BtnezT8SltuX16: FEXT_T8I816_ins<0b000, "btnez", "sltu", IIAlu>, cbranch16;
449 def BtnezT8SltiX16: FEXT_T8I8I16_ins<0b000, "btnez", "slti", IIAlu>, cbranch16;
451 def BtnezT8SltiuX16: FEXT_T8I8I16_ins<0b000, "btnez", "sltiu", IIAlu>,
455 // Format: DIV rx, ry MIPS16e
456 // Purpose: Divide Word
457 // To divide 32-bit signed integers.
459 def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
464 // Format: DIVU rx, ry MIPS16e
465 // Purpose: Divide Unsigned Word
466 // To divide 32-bit unsigned integers.
468 def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
474 // Format: JR ra MIPS16e
475 // Purpose: Jump Register Through Register ra
476 // To execute a branch to the instruction address in the return
480 def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu>;
483 // Format: LB ry, offset(rx) MIPS16e
484 // Purpose: Load Byte (Extended)
485 // To load a byte from memory as a signed value.
487 def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad;
490 // Format: LBU ry, offset(rx) MIPS16e
491 // Purpose: Load Byte Unsigned (Extended)
492 // To load a byte from memory as a unsigned value.
494 def LbuRxRyOffMemX16:
495 FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad;
498 // Format: LH ry, offset(rx) MIPS16e
499 // Purpose: Load Halfword signed (Extended)
500 // To load a halfword from memory as a signed value.
502 def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad;
505 // Format: LHU ry, offset(rx) MIPS16e
506 // Purpose: Load Halfword unsigned (Extended)
507 // To load a halfword from memory as an unsigned value.
509 def LhuRxRyOffMemX16:
510 FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad;
513 // Format: LI rx, immediate MIPS16e
514 // Purpose: Load Immediate (Extended)
515 // To load a constant into a GPR.
517 def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
520 // Format: LW ry, offset(rx) MIPS16e
521 // Purpose: Load Word (Extended)
522 // To load a word from memory as a signed value.
524 def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad;
526 // Format: LW rx, offset(sp) MIPS16e
527 // Purpose: Load Word (SP-Relative, Extended)
528 // To load an SP-relative word from memory as a signed value.
530 def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad;
533 // Format: MOVE r32, rz MIPS16e
535 // To move the contents of a GPR to a GPR.
537 def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
540 // Format: MOVE ry, r32 MIPS16e
542 // To move the contents of a GPR to a GPR.
544 def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
547 // Format: MFHI rx MIPS16e
548 // Purpose: Move From HI Register
549 // To copy the special purpose HI register to a GPR.
551 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
553 let neverHasSideEffects = 1;
557 // Format: MFLO rx MIPS16e
558 // Purpose: Move From LO Register
559 // To copy the special purpose LO register to a GPR.
561 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
563 let neverHasSideEffects = 1;
567 // Pseudo Instruction for mult
569 def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
570 let isCommutable = 1;
571 let neverHasSideEffects = 1;
575 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
576 let isCommutable = 1;
577 let neverHasSideEffects = 1;
582 // Format: MULT rx, ry MIPS16e
583 // Purpose: Multiply Word
584 // To multiply 32-bit signed integers.
586 def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
587 let isCommutable = 1;
588 let neverHasSideEffects = 1;
593 // Format: MULTU rx, ry MIPS16e
594 // Purpose: Multiply Unsigned Word
595 // To multiply 32-bit unsigned integers.
597 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
598 let isCommutable = 1;
599 let neverHasSideEffects = 1;
604 // Format: NEG rx, ry MIPS16e
606 // To negate an integer value.
608 def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
611 // Format: NOT rx, ry MIPS16e
613 // To complement an integer value
615 def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
618 // Format: OR rx, ry MIPS16e
620 // To do a bitwise logical OR.
622 def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
625 // Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
626 // (All args are optional) MIPS16e
627 // Purpose: Restore Registers and Deallocate Stack Frame
628 // To deallocate a stack frame before exit from a subroutine,
629 // restoring return address and static registers, and adjusting
633 // fixed form for restoring RA and the frame
634 // for direct object emitter, encoding needs to be adjusted for the
637 let ra=1, s=0,s0=1,s1=1 in
639 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
640 "restore \t$$ra, $$s0, $$s1, $frame_size", [], IILoad >, MayLoad {
641 let isCodeGenOnly = 1;
645 // Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
647 // Purpose: Save Registers and Set Up Stack Frame
648 // To set up a stack frame on entry to a subroutine,
649 // saving return address and static registers, and adjusting stack
651 let ra=1, s=1,s0=1,s1=1 in
653 FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
654 "save \t$$ra, $$s0, $$s1, $frame_size", [], IIStore >, MayStore {
655 let isCodeGenOnly = 1;
658 // Format: SB ry, offset(rx) MIPS16e
659 // Purpose: Store Byte (Extended)
660 // To store a byte to memory.
663 FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
666 // The Sel(T) instructions are pseudos
667 // T means that they use T8 implicitly.
670 // Format: SelBeqZ rd, rs, rt
671 // Purpose: if rt==0, do nothing
674 def SelBeqZ: Sel<0b00100, "beqz", IIAlu>;
677 // Format: SelTBteqZCmp rd, rs, rl, rr
678 // Purpose: b = Cmp rl, rr.
679 // If b==0 then do nothing.
680 // if b!=0 then rd = rs
682 def SelTBteqZCmp: SelT<0b000, "bteqz", 0b01010, "cmp", IIAlu>;
685 // Format: SelTBteqZCmpi rd, rs, rl, rr
686 // Purpose: b = Cmpi rl, imm.
687 // If b==0 then do nothing.
688 // if b!=0 then rd = rs
690 def SelTBteqZCmpi: SeliT<0b000, "bteqz", 0b01110, "cmpi", IIAlu>;
693 // Format: SelTBteqZSlt rd, rs, rl, rr
694 // Purpose: b = Slt rl, rr.
695 // If b==0 then do nothing.
696 // if b!=0 then rd = rs
698 def SelTBteqZSlt: SelT<0b000, "bteqz", 0b00010, "slt", IIAlu>;
701 // Format: SelTBteqZSlti rd, rs, rl, rr
702 // Purpose: b = Slti rl, imm.
703 // If b==0 then do nothing.
704 // if b!=0 then rd = rs
706 def SelTBteqZSlti: SeliT<0b000, "bteqz", 0b01010, "slti", IIAlu>;
709 // Format: SelTBteqZSltu rd, rs, rl, rr
710 // Purpose: b = Sltu rl, rr.
711 // If b==0 then do nothing.
712 // if b!=0 then rd = rs
714 def SelTBteqZSltu: SelT<0b000, "bteqz", 0b00011, "sltu", IIAlu>;
717 // Format: SelTBteqZSltiu rd, rs, rl, rr
718 // Purpose: b = Sltiu rl, imm.
719 // If b==0 then do nothing.
720 // if b!=0 then rd = rs
722 def SelTBteqZSltiu: SeliT<0b000, "bteqz", 0b01011, "sltiu", IIAlu>;
725 // Format: SelBnez rd, rs, rt
726 // Purpose: if rt!=0, do nothing
729 def SelBneZ: Sel<0b00101, "bnez", IIAlu>;
732 // Format: SelTBtneZCmp rd, rs, rl, rr
733 // Purpose: b = Cmp rl, rr.
734 // If b!=0 then do nothing.
735 // if b0=0 then rd = rs
737 def SelTBtneZCmp: SelT<0b001, "btnez", 0b01010, "cmp", IIAlu>;
740 // Format: SelTBtnezCmpi rd, rs, rl, rr
741 // Purpose: b = Cmpi rl, imm.
742 // If b!=0 then do nothing.
743 // if b==0 then rd = rs
745 def SelTBtneZCmpi: SeliT<0b000, "btnez", 0b01110, "cmpi", IIAlu>;
748 // Format: SelTBtneZSlt rd, rs, rl, rr
749 // Purpose: b = Slt rl, rr.
750 // If b!=0 then do nothing.
751 // if b==0 then rd = rs
753 def SelTBtneZSlt: SelT<0b001, "btnez", 0b00010, "slt", IIAlu>;
756 // Format: SelTBtneZSlti rd, rs, rl, rr
757 // Purpose: b = Slti rl, imm.
758 // If b!=0 then do nothing.
759 // if b==0 then rd = rs
761 def SelTBtneZSlti: SeliT<0b001, "btnez", 0b01010, "slti", IIAlu>;
764 // Format: SelTBtneZSltu rd, rs, rl, rr
765 // Purpose: b = Sltu rl, rr.
766 // If b!=0 then do nothing.
767 // if b==0 then rd = rs
769 def SelTBtneZSltu: SelT<0b001, "btnez", 0b00011, "sltu", IIAlu>;
772 // Format: SelTBtneZSltiu rd, rs, rl, rr
773 // Purpose: b = Slti rl, imm.
774 // If b!=0 then do nothing.
775 // if b==0 then rd = rs
777 def SelTBtneZSltiu: SeliT<0b001, "btnez", 0b01011, "sltiu", IIAlu>;
780 // Format: SH ry, offset(rx) MIPS16e
781 // Purpose: Store Halfword (Extended)
782 // To store a halfword to memory.
785 FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore;
788 // Format: SLL rx, ry, sa MIPS16e
789 // Purpose: Shift Word Left Logical (Extended)
790 // To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
792 def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
795 // Format: SLLV ry, rx MIPS16e
796 // Purpose: Shift Word Left Logical Variable
797 // To execute a left-shift of a word by a variable number of bits.
799 def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
802 // Format: SLTI rx, immediate MIPS16e
803 // Purpose: Set on Less Than Immediate (Extended)
804 // To record the result of a less-than comparison with a constant.
806 def SltiCCRxImmX16: FEXT_CCRXI16_ins<0b01010, "slti", IIAlu>;
809 // Format: SLTIU rx, immediate MIPS16e
810 // Purpose: Set on Less Than Immediate Unsigned (Extended)
811 // To record the result of a less-than comparison with a constant.
813 def SltiuCCRxImmX16: FEXT_CCRXI16_ins<0b01011, "sltiu", IIAlu>;
816 // Format: SLT rx, ry MIPS16e
817 // Purpose: Set on Less Than
818 // To record the result of a less-than comparison.
820 def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>;
822 def SltCCRxRy16: FCCRR16_ins<0b00010, "slt", IIAlu>;
824 // Format: SLTU rx, ry MIPS16e
825 // Purpose: Set on Less Than Unsigned
826 // To record the result of an unsigned less-than comparison.
828 def SltuRxRyRz16: FRRTR16_ins<0b00011, "sltu", IIAlu> {
833 def SltuCCRxRy16: FCCRR16_ins<0b00011, "sltu", IIAlu>;
835 // Format: SRAV ry, rx MIPS16e
836 // Purpose: Shift Word Right Arithmetic Variable
837 // To execute an arithmetic right-shift of a word by a variable
840 def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
844 // Format: SRA rx, ry, sa MIPS16e
845 // Purpose: Shift Word Right Arithmetic (Extended)
846 // To execute an arithmetic right-shift of a word by a fixed
847 // number of bits—1 to 8 bits.
849 def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
853 // Format: SRLV ry, rx MIPS16e
854 // Purpose: Shift Word Right Logical Variable
855 // To execute a logical right-shift of a word by a variable
858 def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
862 // Format: SRL rx, ry, sa MIPS16e
863 // Purpose: Shift Word Right Logical (Extended)
864 // To execute a logical right-shift of a word by a fixed
865 // number of bits—1 to 31 bits.
867 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
870 // Format: SUBU rz, rx, ry MIPS16e
871 // Purpose: Subtract Unsigned Word
872 // To subtract 32-bit integers
874 def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
877 // Format: SW ry, offset(rx) MIPS16e
878 // Purpose: Store Word (Extended)
879 // To store a word to memory.
882 FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore;
885 // Format: SW rx, offset(sp) MIPS16e
886 // Purpose: Store Word rx (SP-Relative)
887 // To store an SP-relative word to memory.
889 def SwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b11010, "sw", IIStore>, MayStore;
893 // Format: XOR rx, ry MIPS16e
895 // To do a bitwise logical XOR.
897 def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
899 class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
900 let Predicates = [InMips16Mode];
905 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
906 Mips16Pat<(OpNode CPU16Regs:$r),
909 def: ArithLogicU_pat<not, NotRxRy16>;
910 def: ArithLogicU_pat<ineg, NegRxRy16>;
912 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
913 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
914 (I CPU16Regs:$l, CPU16Regs:$r)>;
916 def: ArithLogic16_pat<add, AdduRxRyRz16>;
917 def: ArithLogic16_pat<and, AndRxRxRy16>;
918 def: ArithLogic16_pat<mul, MultRxRyRz16>;
919 def: ArithLogic16_pat<or, OrRxRxRy16>;
920 def: ArithLogic16_pat<sub, SubuRxRyRz16>;
921 def: ArithLogic16_pat<xor, XorRxRxRy16>;
923 // Arithmetic and logical instructions with 2 register operands.
925 class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
926 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
927 (I CPU16Regs:$in, imm_type:$imm)>;
929 def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
930 def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
931 def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
932 def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
934 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
935 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
936 (I CPU16Regs:$r, CPU16Regs:$ra)>;
938 def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
939 def: shift_rotate_reg16_pat<sra, SravRxRy16>;
940 def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
942 class LoadM16_pat<PatFrag OpNode, Instruction I> :
943 Mips16Pat<(OpNode addr:$addr), (I addr:$addr)>;
945 def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
946 def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
947 def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
948 def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
949 def: LoadM16_pat<load, LwRxRyOffMemX16>;
951 class StoreM16_pat<PatFrag OpNode, Instruction I> :
952 Mips16Pat<(OpNode CPU16Regs:$r, addr:$addr), (I CPU16Regs:$r, addr:$addr)>;
954 def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
955 def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
956 def: StoreM16_pat<store, SwRxRyOffMemX16>;
958 // Unconditional branch
959 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
960 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
961 let Predicates = [RelocPIC, InMips16Mode];
964 // Jump and Link (Call)
965 let isCall=1, hasDelaySlot=1 in
967 FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
968 "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
971 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
972 hasExtraSrcRegAllocReq = 1 in
973 def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
978 class SetCC_R16<PatFrag cond_op, Instruction I>:
979 Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
980 (I CPU16Regs:$rx, CPU16Regs:$ry)>;
982 class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
983 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
984 (I CPU16Regs:$rx, imm_type:$imm16)>;
986 // Large (>16 bit) immediate loads
987 def : Mips16Pat<(i32 imm:$imm),
988 (OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16),
989 (LiRxImmX16 (LO16 imm:$imm)))>;
991 // Carry MipsPatterns
992 def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
993 (SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
994 def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
995 (AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
996 def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
997 (AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
1000 // Some branch conditional patterns are not generated by llvm at this time.
1001 // Some are for seemingly arbitrary reasons not used: i.e. with signed number
1002 // comparison they are used and for unsigned a different pattern is used.
1003 // I am pushing upstream from the full mips16 port and it seemed that I needed
1004 // these earlier and the mips32 port has these but now I cannot create test
1005 // cases that use these patterns. While I sort this all out I will leave these
1006 // extra patterns commented out and if I can be sure they are really not used,
1007 // I will delete the code. I don't want to check the code in uncommented without
1008 // a valid test case. In some cases, the compiler is generating patterns with
1009 // setcc instead and earlier I had implemented setcc first so may have masked
1010 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
1011 // figure out how to enable the brcond patterns or else possibly new
1012 // combinations of of brcond and setcc.
1018 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1019 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1024 <(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1025 (BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1029 <(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
1030 (BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16)
1034 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1037 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1038 (BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1045 <(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1046 (BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1050 // never called because compiler transforms a >= k to a > (k-1)
1052 <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1053 (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1060 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1061 (BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1065 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1066 (BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
1073 <(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1074 (BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1081 <(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1082 (BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1086 <(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
1087 (BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
1091 <(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
1092 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1096 // This needs to be there but I forget which code will generate it
1099 <(brcond CPU16Regs:$rx, bb:$targ16),
1100 (BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
1109 // <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1110 // (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
1117 // <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1118 // (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1126 // <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1127 // (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
1130 def: UncondBranch16_pat<br, BimmX16>;
1133 def: Mips16Pat<(i32 immSExt16:$in),
1134 (AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
1136 def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
1142 <(MipsDivRem CPU16Regs:$rx, CPU16Regs:$ry),
1143 (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1149 <(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry),
1150 (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
1155 // if !(a < b) x = y
1157 def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
1158 CPU16Regs:$x, CPU16Regs:$y),
1159 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1160 CPU16Regs:$a, CPU16Regs:$b)>;
1167 def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
1168 CPU16Regs:$x, CPU16Regs:$y),
1169 (SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
1170 CPU16Regs:$b, CPU16Regs:$a)>;
1175 // if !(a < b) x = y;
1178 (select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
1179 CPU16Regs:$x, CPU16Regs:$y),
1180 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1181 CPU16Regs:$a, CPU16Regs:$b)>;
1188 def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
1189 CPU16Regs:$x, CPU16Regs:$y),
1190 (SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
1191 CPU16Regs:$b, CPU16Regs:$a)>;
1195 // due to an llvm optimization, i don't think that this will ever
1196 // be used. This is transformed into x = (a > k-1)?x:y
1201 // (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
1202 // CPU16Regs:$T, CPU16Regs:$F),
1203 // (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
1204 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1207 // (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
1208 // CPU16Regs:$T, CPU16Regs:$F),
1209 // (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
1210 // CPU16Regs:$lhs, immSExt16:$rhs)>;
1215 // if !(a < k) x = y;
1218 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1219 CPU16Regs:$x, CPU16Regs:$y),
1220 (SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
1221 CPU16Regs:$a, immSExt16:$b)>;
1227 // x = (a <= b)? x : y
1231 def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
1232 CPU16Regs:$x, CPU16Regs:$y),
1233 (SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
1234 CPU16Regs:$b, CPU16Regs:$a)>;
1238 // x = (a <= b)? x : y
1242 def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
1243 CPU16Regs:$x, CPU16Regs:$y),
1244 (SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
1245 CPU16Regs:$b, CPU16Regs:$a)>;
1249 // x = (a == b)? x : y
1251 // if (a != b) x = y
1253 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
1254 CPU16Regs:$x, CPU16Regs:$y),
1255 (SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
1256 CPU16Regs:$b, CPU16Regs:$a)>;
1260 // x = (a == 0)? x : y
1262 // if (a != 0) x = y
1264 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
1265 CPU16Regs:$x, CPU16Regs:$y),
1266 (SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
1272 // x = (a == k)? x : y
1274 // if (a != k) x = y
1276 def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
1277 CPU16Regs:$x, CPU16Regs:$y),
1278 (SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
1279 CPU16Regs:$a, immZExt16:$k)>;
1284 // x = (a != b)? x : y
1286 // if (a == b) x = y
1289 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
1290 CPU16Regs:$x, CPU16Regs:$y),
1291 (SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
1292 CPU16Regs:$b, CPU16Regs:$a)>;
1296 // x = (a != 0)? x : y
1298 // if (a == 0) x = y
1300 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
1301 CPU16Regs:$x, CPU16Regs:$y),
1302 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1310 def : Mips16Pat<(select CPU16Regs:$a,
1311 CPU16Regs:$x, CPU16Regs:$y),
1312 (SelBneZ CPU16Regs:$x, CPU16Regs:$y,
1318 // x = (a != k)? x : y
1320 // if (a == k) x = y
1322 def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
1323 CPU16Regs:$x, CPU16Regs:$y),
1324 (SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
1325 CPU16Regs:$a, immZExt16:$k)>;
1328 // When writing C code to test setxx these patterns,
1329 // some will be transformed into
1330 // other things. So we test using C code but using -O3 and -O0
1335 <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
1336 (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
1339 <(seteq CPU16Regs:$lhs, 0),
1340 (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
1348 <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
1349 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1353 // For constants, llvm transforms this to:
1354 // x > (k -1) and then reverses the operands to use setlt. So this pattern
1355 // is not used now by the compiler. (Presumably checking that k-1 does not
1356 // overflow). The compiler never uses this at a the current time, due to
1357 // other optimizations.
1360 // <(setge CPU16Regs:$lhs, immSExt16:$rhs),
1361 // (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
1362 // (LiRxImmX16 1))>;
1364 // This catches the x >= -32768 case by transforming it to x > -32769
1367 <(setgt CPU16Regs:$lhs, -32769),
1368 (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
1377 <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
1378 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1384 <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
1385 (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1390 def: SetCC_R16<setlt, SltCCRxRy16>;
1392 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
1398 <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
1399 (SltuCCRxRy16 (LiRxImmX16 0),
1400 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
1407 <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
1408 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
1411 // this pattern will never be used because the compiler will transform
1412 // x >= k to x > (k - 1) and then use SLT
1415 // <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
1416 // (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
1417 // (LiRxImmX16 1))>;
1423 <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
1424 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
1430 <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
1431 (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
1436 def: SetCC_R16<setult, SltuCCRxRy16>;
1438 def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
1440 def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
1441 (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;