1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: bc1any2, bc1any4
29 // Rencoded: [ls][wd]c2
31 def brtarget21 : Operand<OtherVT> {
32 let EncoderMethod = "getBranchTarget21OpValue";
33 let OperandType = "OPERAND_PCREL";
34 let DecoderMethod = "DecodeBranchTarget21";
35 let ParserMatchClass = MipsJumpTargetAsmOperand;
38 def brtarget26 : Operand<OtherVT> {
39 let EncoderMethod = "getBranchTarget26OpValue";
40 let OperandType = "OPERAND_PCREL";
41 let DecoderMethod = "DecodeBranchTarget26";
42 let ParserMatchClass = MipsJumpTargetAsmOperand;
45 def jmpoffset16 : Operand<OtherVT> {
46 let EncoderMethod = "getJumpOffset16OpValue";
47 let ParserMatchClass = MipsJumpTargetAsmOperand;
50 def calloffset16 : Operand<iPTR> {
51 let EncoderMethod = "getJumpOffset16OpValue";
52 let ParserMatchClass = MipsJumpTargetAsmOperand;
55 //===----------------------------------------------------------------------===//
57 // Instruction Encodings
59 //===----------------------------------------------------------------------===//
61 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
62 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
63 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
64 class AUI_ENC : AUI_FM;
65 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
67 class BAL_ENC : BAL_FM;
68 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
69 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
70 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
71 DecodeDisambiguates<"AddiGroupBranch">;
72 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
73 DecodeDisambiguatedBy<"DaddiGroupBranch">;
74 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
75 DecodeDisambiguates<"DaddiGroupBranch">;
76 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
77 DecodeDisambiguatedBy<"DaddiGroupBranch">;
79 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
80 DecodeDisambiguates<"BgtzlGroupBranch">;
81 class BGEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>,
82 DecodeDisambiguatedBy<"BlezlGroupBranch">;
83 class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>,
84 DecodeDisambiguatedBy<"BlezGroupBranch">;
85 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
86 DecodeDisambiguates<"BlezlGroupBranch">;
87 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
88 DecodeDisambiguatedBy<"BgtzGroupBranch">;
90 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
91 DecodeDisambiguatedBy<"BlezlGroupBranch">;
92 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
93 DecodeDisambiguates<"BgtzGroupBranch">;
94 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
95 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
97 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
98 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>,
99 DecodeDisambiguates<"BlezGroupBranch">;
100 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
102 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
103 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
104 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
105 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
107 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
108 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
109 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;
110 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
111 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>,
112 DecodeDisambiguatedBy<"BlezGroupBranch">;
113 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
114 DecodeDisambiguatedBy<"DaddiGroupBranch">;
115 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
116 DecodeDisambiguatedBy<"AddiGroupBranch">;
117 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
118 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
119 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
120 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
121 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
122 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
123 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
124 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
126 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
127 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
128 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
129 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
131 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
132 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
134 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
135 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
137 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
138 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
140 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
141 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
142 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
143 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
145 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
146 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
147 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
148 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
150 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
151 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
152 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
153 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
155 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
156 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
157 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
158 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
160 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
161 RegisterOperand FGROpnd,
162 SDPatternOperator Op = null_frag> {
163 dag OutOperandList = (outs FGRCCOpnd:$fd);
164 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
165 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
166 list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
169 //===----------------------------------------------------------------------===//
171 // Instruction Multiclasses
173 //===----------------------------------------------------------------------===//
175 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
176 RegisterOperand FGROpnd>{
177 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
178 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
180 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
181 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>,
183 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
184 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>,
186 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
187 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>,
189 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
190 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd, setolt>,
192 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
193 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>,
195 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
196 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd, setole>,
198 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
199 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>,
201 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
202 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
204 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
205 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
207 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
208 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
210 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
211 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
213 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
214 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
216 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
217 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
219 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
220 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
222 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
223 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
227 //===----------------------------------------------------------------------===//
229 // Instruction Descriptions
231 //===----------------------------------------------------------------------===//
233 class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
235 dag OutOperandList = (outs GPROpnd:$rs);
236 dag InOperandList = (ins ImmOpnd:$imm);
237 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
238 list<dag> Pattern = [];
241 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
242 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
243 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2>;
245 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
247 dag OutOperandList = (outs GPROpnd:$rd);
248 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
249 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
250 list<dag> Pattern = [];
253 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
255 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
256 dag OutOperandList = (outs GPROpnd:$rs);
257 dag InOperandList = (ins simm16:$imm);
258 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
259 list<dag> Pattern = [];
262 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
263 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
265 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
266 dag OutOperandList = (outs GPROpnd:$rs);
267 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
268 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
269 list<dag> Pattern = [];
272 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
274 class BRANCH_DESC_BASE {
276 bit isTerminator = 1;
277 bit hasDelaySlot = 0;
280 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
281 dag InOperandList = (ins opnd:$offset);
282 dag OutOperandList = (outs);
283 string AsmString = !strconcat(instr_asm, "\t$offset");
287 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
288 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
289 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
290 dag OutOperandList = (outs);
291 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
292 list<Register> Defs = [AT];
295 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
296 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
297 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
298 dag OutOperandList = (outs);
299 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
300 list<Register> Defs = [AT];
303 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
304 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
305 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
306 dag OutOperandList = (outs);
307 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
308 list<Register> Defs = [AT];
311 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
313 bit hasDelaySlot = 1;
314 list<Register> Defs = [RA];
317 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
319 list<Register> Defs = [RA];
322 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
323 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
324 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
325 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
326 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
328 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
329 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
331 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
332 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
334 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
335 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
337 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
338 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
339 dag OutOperandList = (outs);
340 string AsmString = instr_asm;
341 bit hasDelaySlot = 1;
344 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
345 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
347 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
348 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
349 dag OutOperandList = (outs);
350 string AsmString = instr_asm;
351 bit hasDelaySlot = 1;
354 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
355 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
357 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
358 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
360 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
361 RegisterOperand GPROpnd> {
362 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
363 string AsmString = !strconcat(opstr, "\t$rt, $offset");
364 list<dag> Pattern = [];
365 bit isTerminator = 1;
366 bit hasDelaySlot = 0;
367 string DecoderMethod = "DecodeSimm16";
370 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
373 list<Register> Defs = [RA];
376 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
378 list<Register> Defs = [AT];
381 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
383 bit isIndirectBranch = 1;
384 bit hasDelaySlot = 1;
389 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
390 dag OutOperandList = (outs GPROpnd:$rd);
391 dag InOperandList = (ins GPROpnd:$rt);
392 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
393 list<dag> Pattern = [];
396 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
398 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
399 SDPatternOperator Op=null_frag> {
400 dag OutOperandList = (outs GPROpnd:$rd);
401 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
402 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
403 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
405 // This instruction doesn't trap division by zero itself. We must insert
406 // teq instructions as well.
407 bit usesCustomInserter = 1;
410 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, sdiv>;
411 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>;
412 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>;
413 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>;
415 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
416 list<Register> Defs = [RA];
419 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
420 list<Register> Defs = [RA];
423 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
424 list<Register> Defs = [RA];
427 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
428 list<Register> Defs = [RA];
431 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
432 list<Register> Defs = [RA];
435 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
436 list<Register> Defs = [RA];
439 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
440 SDPatternOperator Op=null_frag> {
441 dag OutOperandList = (outs GPROpnd:$rd);
442 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
443 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
444 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
447 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>;
448 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>;
449 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;
450 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
452 class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
453 dag OutOperandList = (outs FGROpnd:$fd);
454 dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
455 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
456 list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in,
459 string Constraints = "$fd_in = $fd";
462 class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
463 // We must insert a SUBREG_TO_REG around $fd_in
464 bit usesCustomInserter = 1;
466 class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
468 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
469 dag OutOperandList = (outs GPROpnd:$rd);
470 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
471 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
472 list<dag> Pattern = [];
475 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
476 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
478 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
479 dag OutOperandList = (outs FGROpnd:$fd);
480 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
481 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
482 list<dag> Pattern = [];
483 string Constraints = "$fd_in = $fd";
486 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
487 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
488 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
489 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
491 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
492 dag OutOperandList = (outs FGROpnd:$fd);
493 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
494 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
495 list<dag> Pattern = [];
498 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
499 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
500 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
501 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
503 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
504 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
505 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
506 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
508 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
509 dag OutOperandList = (outs FGROpnd:$fd);
510 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
511 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
512 list<dag> Pattern = [];
515 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
516 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
517 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
518 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
520 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
521 dag OutOperandList = (outs FGROpnd:$fd);
522 dag InOperandList = (ins FGROpnd:$fs);
523 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
524 list<dag> Pattern = [];
527 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
528 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
529 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
530 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
532 //===----------------------------------------------------------------------===//
534 // Instruction Definitions
536 //===----------------------------------------------------------------------===//
538 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
539 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
540 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
541 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
542 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
543 def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6;
544 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
545 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6;
546 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6;
547 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
548 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
549 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
550 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
551 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
552 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
553 def BGEC : BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
554 def BGEUC : BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
555 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
556 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
557 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
558 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
559 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
560 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
561 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
562 def BLTC; // Also aliased to bgtc with operands swapped
563 def BLTUC; // Also aliased to bgtuc with operands swapped
564 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
565 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
566 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
567 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
568 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
569 def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
570 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
571 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
572 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
573 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
574 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
575 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
576 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
577 def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
578 def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
579 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
580 // def LSA; // See MSA
581 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
582 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
583 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
584 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
585 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
586 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
587 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
588 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
589 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
590 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
591 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
592 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
593 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
594 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
595 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
596 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
597 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
598 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
599 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
600 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
601 def NAL; // BAL with rd=0
602 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
603 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
604 def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
605 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
606 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
607 def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
608 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
609 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
610 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
611 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;
613 //===----------------------------------------------------------------------===//
615 // Patterns and Pseudo Instructions
617 //===----------------------------------------------------------------------===//
619 // f32 comparisons supported via another comparison
620 def : MipsPat<(setone f32:$lhs, f32:$rhs),
621 (NOR (CMP_UEQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
622 def : MipsPat<(seto f32:$lhs, f32:$rhs),
623 (NOR (CMP_UN_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
624 def : MipsPat<(setune f32:$lhs, f32:$rhs),
625 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
626 def : MipsPat<(seteq f32:$lhs, f32:$rhs), (CMP_EQ_S f32:$lhs, f32:$rhs)>,
628 def : MipsPat<(setgt f32:$lhs, f32:$rhs), (CMP_LE_S f32:$rhs, f32:$lhs)>,
630 def : MipsPat<(setge f32:$lhs, f32:$rhs), (CMP_LT_S f32:$rhs, f32:$lhs)>,
632 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLT_S f32:$lhs, f32:$rhs)>,
634 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLE_S f32:$lhs, f32:$rhs)>,
636 def : MipsPat<(setne f32:$lhs, f32:$rhs),
637 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
639 // f64 comparisons supported via another comparison
640 def : MipsPat<(setone f64:$lhs, f64:$rhs),
641 (NOR (CMP_UEQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
642 def : MipsPat<(seto f64:$lhs, f64:$rhs),
643 (NOR (CMP_UN_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
644 def : MipsPat<(setune f64:$lhs, f64:$rhs),
645 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
646 def : MipsPat<(seteq f64:$lhs, f64:$rhs), (CMP_EQ_D f64:$lhs, f64:$rhs)>,
648 def : MipsPat<(setgt f64:$lhs, f64:$rhs), (CMP_LE_D f64:$rhs, f64:$lhs)>,
650 def : MipsPat<(setge f64:$lhs, f64:$rhs), (CMP_LT_D f64:$rhs, f64:$lhs)>,
652 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLT_D f64:$lhs, f64:$rhs)>,
654 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLE_D f64:$lhs, f64:$rhs)>,
656 def : MipsPat<(setne f64:$lhs, f64:$rhs),
657 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
660 def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
661 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
663 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, i32:$f),
664 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
666 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, i32:$f),
667 (OR (SELNEZ i32:$f, i32:$cond), (SELEQZ i32:$t, i32:$cond))>,
669 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
670 (OR (SELNEZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
671 (SELEQZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
673 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
674 (OR (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)),
675 (SELEQZ i32:$t, (XORi i32:$cond, immZExt16:$imm)))>,
677 def : MipsPat<(select (i32 (setgt i32:$cond, immSExt16Plus1:$imm)), i32:$t,
679 (OR (SELNEZ i32:$t, (SLTi i32:$cond, (Plus1 imm:$imm))),
680 (SELEQZ i32:$f, (SLTi i32:$cond, (Plus1 imm:$imm))))>,
682 def : MipsPat<(select (i32 (setugt i32:$cond, immSExt16Plus1:$imm)),
684 (OR (SELNEZ i32:$t, (SLTiu i32:$cond, (Plus1 imm:$imm))),
685 (SELEQZ i32:$f, (SLTiu i32:$cond, (Plus1 imm:$imm))))>,
688 def : MipsPat<(select i32:$cond, i32:$t, immz),
689 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
690 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, immz),
691 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
692 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, immz),
693 (SELEQZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
694 def : MipsPat<(select i32:$cond, immz, i32:$f),
695 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
696 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i32:$f),
697 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
698 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i32:$f),
699 (SELNEZ i32:$f, i32:$cond)>, ISA_MIPS32R6;