1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
30 // Removed: bc1any2, bc1any4
32 // Removed: bc2f, bc2t
35 // Removed: c.cond.fmt, bc1[ft]
40 // Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
42 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
43 // Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
44 // Removed: movf, movt
45 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
46 // Removed: movn, movz
47 // Removed: mult, multu
52 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
53 // Rencoded: [ls][wd]c2
55 //===----------------------------------------------------------------------===//
57 // Instruction Encodings
59 //===----------------------------------------------------------------------===//
61 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
62 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
63 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
64 class AUI_ENC : AUI_FM;
65 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
66 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
67 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
68 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
69 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
70 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
71 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
72 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
73 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
74 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
76 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
77 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
78 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
79 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
81 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
82 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
84 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
85 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
86 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
87 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
89 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
90 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
91 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
92 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
94 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
95 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
96 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
97 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
99 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
100 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
101 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
102 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
104 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, RegisterOperand FGROpnd> {
105 dag OutOperandList = (outs FGROpnd:$fd);
106 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
107 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
108 list<dag> Pattern = [];
111 //===----------------------------------------------------------------------===//
113 // Instruction Multiclasses
115 //===----------------------------------------------------------------------===//
117 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
118 RegisterOperand FGROpnd>{
119 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
120 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
122 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
123 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>,
125 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
126 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>,
128 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
129 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>,
131 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
132 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd>,
134 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
135 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>,
137 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
138 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd>,
140 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
141 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>,
143 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
144 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
146 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
147 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
149 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
150 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
152 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
153 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
155 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
156 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
158 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
159 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
161 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
162 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
164 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
165 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
169 //===----------------------------------------------------------------------===//
171 // Instruction Descriptions
173 //===----------------------------------------------------------------------===//
175 class ADDIUPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
176 dag OutOperandList = (outs GPROpnd:$rs);
177 dag InOperandList = (ins simm19_lsl2:$imm);
178 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
179 list<dag> Pattern = [];
182 class ADDIUPC_DESC : ADDIUPC_DESC_BASE<"addiupc", GPR32Opnd>;
184 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
186 dag OutOperandList = (outs GPROpnd:$rd);
187 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
188 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
189 list<dag> Pattern = [];
192 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
194 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
195 dag OutOperandList = (outs GPROpnd:$rs);
196 dag InOperandList = (ins simm16:$imm);
197 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
198 list<dag> Pattern = [];
201 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
202 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
204 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
205 dag OutOperandList = (outs GPROpnd:$rs);
206 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
207 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
208 list<dag> Pattern = [];
211 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
213 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
214 dag OutOperandList = (outs GPROpnd:$rd);
215 dag InOperandList = (ins GPROpnd:$rt);
216 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
217 list<dag> Pattern = [];
220 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
222 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
223 dag OutOperandList = (outs GPROpnd:$rd);
224 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
225 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
226 list<dag> Pattern = [];
229 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>;
230 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>;
231 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>;
232 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>;
234 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
235 dag OutOperandList = (outs GPROpnd:$rd);
236 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
237 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
238 list<dag> Pattern = [];
241 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
242 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
243 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
244 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
246 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
247 dag OutOperandList = (outs FGROpnd:$fd);
248 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
249 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
250 list<dag> Pattern = [];
251 string Constraints = "$fd_in = $fd";
254 class SEL_D_DESC : COP1_4R_DESC_BASE<"sel.d", FGR64Opnd>;
255 class SEL_S_DESC : COP1_4R_DESC_BASE<"sel.s", FGR32Opnd>;
257 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
258 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
259 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
260 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
262 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
263 dag OutOperandList = (outs FGROpnd:$fd);
264 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
265 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
266 list<dag> Pattern = [];
269 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
270 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
271 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
272 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
274 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
275 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
276 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
277 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
279 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
280 dag OutOperandList = (outs FGROpnd:$fd);
281 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
282 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
283 list<dag> Pattern = [];
286 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
287 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
288 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
289 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
291 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
292 dag OutOperandList = (outs FGROpnd:$fd);
293 dag InOperandList = (ins FGROpnd:$fs);
294 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
295 list<dag> Pattern = [];
298 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
299 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
300 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
301 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
303 //===----------------------------------------------------------------------===//
305 // Instruction Definitions
307 //===----------------------------------------------------------------------===//
309 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
310 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
311 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
312 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
313 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
323 def BGEC; // Also aliased to blec with operands swapped
324 def BGEUC; // Also aliased to bleuc with operands swapped
329 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
332 def BLTC; // Also aliased to bgtc with operands swapped
333 def BLTUC; // Also aliased to bgtuc with operands swapped
341 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
342 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
343 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
344 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
345 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
346 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
349 // def LSA; // See MSA
352 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
353 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
354 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
355 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
356 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
357 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
358 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
359 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
360 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
361 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
362 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
363 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
364 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
365 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
366 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
367 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
368 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
369 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
370 def NAL; // BAL with rd=0
371 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
372 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
374 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
375 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
377 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
378 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
379 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
380 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;