1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
30 // Removed: bc1any2, bc1any4
32 // Removed: bc2f, bc2t
35 // Removed: c.cond.fmt, bc1[ft]
40 // Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
42 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
43 // Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
44 // Removed: movf, movt
45 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
46 // Removed: movn, movz
47 // Removed: mult, multu
52 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
53 // Rencoded: [ls][wd]c2
55 def brtarget21 : Operand<OtherVT> {
56 let EncoderMethod = "getBranchTarget21OpValue";
57 let OperandType = "OPERAND_PCREL";
58 let DecoderMethod = "DecodeBranchTarget21";
59 let ParserMatchClass = MipsJumpTargetAsmOperand;
62 def brtarget26 : Operand<OtherVT> {
63 let EncoderMethod = "getBranchTarget26OpValue";
64 let OperandType = "OPERAND_PCREL";
65 let DecoderMethod = "DecodeBranchTarget26";
66 let ParserMatchClass = MipsJumpTargetAsmOperand;
69 def jmpoffset16 : Operand<OtherVT> {
70 let EncoderMethod = "getJumpOffset16OpValue";
71 let ParserMatchClass = MipsJumpTargetAsmOperand;
74 def calloffset16 : Operand<iPTR> {
75 let EncoderMethod = "getJumpOffset16OpValue";
76 let ParserMatchClass = MipsJumpTargetAsmOperand;
79 //===----------------------------------------------------------------------===//
81 // Instruction Encodings
83 //===----------------------------------------------------------------------===//
85 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
86 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
87 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
88 class AUI_ENC : AUI_FM;
89 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
91 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
92 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
93 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
94 DecodeDisambiguates<"AddiGroupBranch">;
95 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
96 DecodeDisambiguatedBy<"DaddiGroupBranch">;
97 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
98 DecodeDisambiguates<"DaddiGroupBranch">;
99 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
100 DecodeDisambiguatedBy<"DaddiGroupBranch">;
102 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
103 DecodeDisambiguates<"BgtzlGroupBranch">;
104 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
105 DecodeDisambiguates<"BlezlGroupBranch">;
106 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
107 DecodeDisambiguatedBy<"BgtzGroupBranch">;
109 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
110 DecodeDisambiguatedBy<"BlezlGroupBranch">;
111 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
112 DecodeDisambiguates<"BgtzGroupBranch">;
113 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
114 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
116 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
117 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>;
118 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
120 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
121 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
122 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
123 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
125 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
126 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
128 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
129 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>;
130 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
131 DecodeDisambiguatedBy<"DaddiGroupBranch">;
132 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
133 DecodeDisambiguatedBy<"AddiGroupBranch">;
134 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
135 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
136 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
137 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
138 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
139 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
140 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
141 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
143 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
144 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
145 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
146 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
148 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
149 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
151 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
152 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
154 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
155 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
157 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
158 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
159 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
160 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
162 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
163 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
164 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
165 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
167 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
168 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
169 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
170 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
172 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
173 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
174 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
175 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
177 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, RegisterOperand FGROpnd> {
178 dag OutOperandList = (outs FGROpnd:$fd);
179 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
180 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
181 list<dag> Pattern = [];
184 //===----------------------------------------------------------------------===//
186 // Instruction Multiclasses
188 //===----------------------------------------------------------------------===//
190 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
191 RegisterOperand FGROpnd>{
192 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
193 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
195 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
196 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>,
198 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
199 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>,
201 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
202 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>,
204 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
205 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd>,
207 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
208 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>,
210 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
211 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd>,
213 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
214 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>,
216 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
217 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
219 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
220 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
222 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
223 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
225 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
226 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
228 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
229 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
231 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
232 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
234 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
235 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
237 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
238 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
242 //===----------------------------------------------------------------------===//
244 // Instruction Descriptions
246 //===----------------------------------------------------------------------===//
248 class PCREL19_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
249 dag OutOperandList = (outs GPROpnd:$rs);
250 dag InOperandList = (ins simm19_lsl2:$imm);
251 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
252 list<dag> Pattern = [];
255 class ADDIUPC_DESC : PCREL19_DESC_BASE<"addiupc", GPR32Opnd>;
256 class LWPC_DESC: PCREL19_DESC_BASE<"lwpc", GPR32Opnd>;
257 class LWUPC_DESC: PCREL19_DESC_BASE<"lwupc", GPR32Opnd>;
259 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
261 dag OutOperandList = (outs GPROpnd:$rd);
262 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
263 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
264 list<dag> Pattern = [];
267 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
269 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
270 dag OutOperandList = (outs GPROpnd:$rs);
271 dag InOperandList = (ins simm16:$imm);
272 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
273 list<dag> Pattern = [];
276 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
277 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
279 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
280 dag OutOperandList = (outs GPROpnd:$rs);
281 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
282 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
283 list<dag> Pattern = [];
286 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
288 class BRANCH_DESC_BASE {
290 bit isTerminator = 1;
291 bit hasDelaySlot = 0;
294 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
295 dag InOperandList = (ins opnd:$offset);
296 dag OutOperandList = (outs);
297 string AsmString = !strconcat(instr_asm, "\t$offset");
301 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
302 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
303 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
304 dag OutOperandList = (outs);
305 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
306 list<Register> Defs = [AT];
309 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
310 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
311 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
312 dag OutOperandList = (outs);
313 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
314 list<Register> Defs = [AT];
317 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
318 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
319 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
320 dag OutOperandList = (outs);
321 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
322 list<Register> Defs = [AT];
325 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
327 list<Register> Defs = [RA];
330 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
331 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
332 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
334 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
335 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
337 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
338 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
340 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
341 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
343 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
344 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
345 dag OutOperandList = (outs);
346 string AsmString = instr_asm;
347 bit hasDelaySlot = 1;
350 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
351 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
353 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
354 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
355 dag OutOperandList = (outs);
356 string AsmString = instr_asm;
357 bit hasDelaySlot = 1;
360 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
361 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
363 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
364 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
366 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
367 RegisterOperand GPROpnd> {
368 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
369 string AsmString = !strconcat(opstr, "\t$rt, $offset");
370 list<dag> Pattern = [];
371 bit isTerminator = 1;
372 bit hasDelaySlot = 0;
373 string DecoderMethod = "DecodeSimm16";
376 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
379 list<Register> Defs = [RA];
382 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
384 list<Register> Defs = [AT];
387 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
388 dag OutOperandList = (outs GPROpnd:$rd);
389 dag InOperandList = (ins GPROpnd:$rt);
390 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
391 list<dag> Pattern = [];
394 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
396 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
397 dag OutOperandList = (outs GPROpnd:$rd);
398 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
399 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
400 list<dag> Pattern = [];
403 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>;
404 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>;
405 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>;
406 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>;
408 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
409 list<Register> Defs = [RA];
412 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
413 list<Register> Defs = [RA];
416 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
417 list<Register> Defs = [RA];
420 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
421 list<Register> Defs = [RA];
424 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
425 list<Register> Defs = [RA];
428 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
429 list<Register> Defs = [RA];
431 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
432 dag OutOperandList = (outs GPROpnd:$rd);
433 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
434 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
435 list<dag> Pattern = [];
438 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
439 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
440 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
441 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
443 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
444 dag OutOperandList = (outs FGROpnd:$fd);
445 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
446 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
447 list<dag> Pattern = [];
448 string Constraints = "$fd_in = $fd";
451 class SEL_D_DESC : COP1_4R_DESC_BASE<"sel.d", FGR64Opnd>;
452 class SEL_S_DESC : COP1_4R_DESC_BASE<"sel.s", FGR32Opnd>;
454 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
455 dag OutOperandList = (outs GPROpnd:$rd);
456 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
457 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
458 list<dag> Pattern = [];
461 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
462 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
464 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
465 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
466 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
467 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
469 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
470 dag OutOperandList = (outs FGROpnd:$fd);
471 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
472 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
473 list<dag> Pattern = [];
476 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
477 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
478 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
479 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
481 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
482 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
483 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
484 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
486 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
487 dag OutOperandList = (outs FGROpnd:$fd);
488 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
489 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
490 list<dag> Pattern = [];
493 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
494 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
495 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
496 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
498 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
499 dag OutOperandList = (outs FGROpnd:$fd);
500 dag InOperandList = (ins FGROpnd:$fs);
501 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
502 list<dag> Pattern = [];
505 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
506 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
507 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
508 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
510 //===----------------------------------------------------------------------===//
512 // Instruction Definitions
514 //===----------------------------------------------------------------------===//
516 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
517 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
518 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
519 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
520 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
521 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
522 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6;
523 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6;
524 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
525 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
526 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
527 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
528 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
529 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
530 def BGEC; // Also aliased to blec with operands swapped
531 def BGEUC; // Also aliased to bleuc with operands swapped
532 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
533 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
534 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
535 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
536 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
537 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
538 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
539 def BLTC; // Also aliased to bgtc with operands swapped
540 def BLTUC; // Also aliased to bgtuc with operands swapped
541 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
542 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
543 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
544 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
545 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
546 def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
547 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
548 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
549 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
550 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
551 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
552 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
553 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
554 def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
555 def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
556 // def LSA; // See MSA
557 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
558 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
559 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
560 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
561 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
562 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
563 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
564 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
565 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
566 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
567 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
568 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
569 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
570 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
571 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
572 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
573 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
574 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
575 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
576 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
577 def NAL; // BAL with rd=0
578 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
579 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
580 def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6;
581 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
582 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
583 def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6;
584 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
585 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
586 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
587 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;