1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: /.ps$/, cvt.ps.s, cvt.ps.pw
30 // Removed: bc1any2, bc1any4
32 // Removed: bc2f, bc2t
35 // Removed: c.cond.fmt, bc1[ft]
40 // Removed: lwl, lwr, lwle, lwre, swl, swr, swle, swre
42 // Removed: madd.[ds], nmadd.[ds], nmsub.[ds], sub.[ds]
43 // Removed: mfhi, mflo, mthi, mtlo, madd, maddu, msub, msubu, mul
44 // Removed: movf, movt
45 // Removed: movf.fmt, movt.fmt, movn.fmt, movz.fmt
46 // Removed: movn, movz
47 // Removed: mult, multu
52 // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei
53 // Rencoded: [ls][wd]c2
55 //===----------------------------------------------------------------------===//
57 // Instruction Encodings
59 //===----------------------------------------------------------------------===//
61 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
62 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
63 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
64 class AUI_ENC : AUI_FM;
65 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
66 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
67 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
68 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
69 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
70 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
71 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
72 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
73 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
74 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
75 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
76 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
78 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
79 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
80 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
81 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
83 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
84 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
85 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
86 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
88 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
89 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
90 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
91 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
93 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
94 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
96 //===----------------------------------------------------------------------===//
98 // Instruction Descriptions
100 //===----------------------------------------------------------------------===//
102 class ADDIUPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
103 dag OutOperandList = (outs GPROpnd:$rs);
104 dag InOperandList = (ins simm19_lsl2:$imm);
105 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
106 list<dag> Pattern = [];
109 class ADDIUPC_DESC : ADDIUPC_DESC_BASE<"addiupc", GPR32Opnd>;
111 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
113 dag OutOperandList = (outs GPROpnd:$rd);
114 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
115 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
116 list<dag> Pattern = [];
119 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
121 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
122 dag OutOperandList = (outs GPROpnd:$rs);
123 dag InOperandList = (ins simm16:$imm);
124 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
125 list<dag> Pattern = [];
128 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
129 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
131 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
132 dag OutOperandList = (outs GPROpnd:$rs);
133 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
134 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
135 list<dag> Pattern = [];
138 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
140 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
141 dag OutOperandList = (outs GPROpnd:$rd);
142 dag InOperandList = (ins GPROpnd:$rt);
143 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
144 list<dag> Pattern = [];
147 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
149 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
150 dag OutOperandList = (outs GPROpnd:$rd);
151 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
152 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
153 list<dag> Pattern = [];
156 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd>;
157 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd>;
158 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd>;
159 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd>;
161 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
162 dag OutOperandList = (outs GPROpnd:$rd);
163 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
164 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
165 list<dag> Pattern = [];
168 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>;
169 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
170 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
171 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
173 class SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
174 dag OutOperandList = (outs FGROpnd:$fd);
175 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
176 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
177 list<dag> Pattern = [];
178 string Constraints = "$fd_in = $fd";
181 class SEL_D_DESC : SEL_DESC_BASE<"sel.d", FGR64Opnd>;
182 class SEL_S_DESC : SEL_DESC_BASE<"sel.s", FGR32Opnd>;
184 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
185 dag OutOperandList = (outs FGROpnd:$fd);
186 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
187 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
188 list<dag> Pattern = [];
191 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
192 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
193 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
194 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
196 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
197 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
198 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
199 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
201 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
202 dag OutOperandList = (outs FGROpnd:$fd);
203 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
204 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
205 list<dag> Pattern = [];
208 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
209 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
210 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
211 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
213 class RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
214 dag OutOperandList = (outs FGROpnd:$fd);
215 dag InOperandList = (ins FGROpnd:$fs);
216 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
217 list<dag> Pattern = [];
220 class RINT_S_DESC : RINT_DESC_BASE<"rint.s", FGR32Opnd>;
221 class RINT_D_DESC : RINT_DESC_BASE<"rint.d", FGR64Opnd>;
223 //===----------------------------------------------------------------------===//
225 // Instruction Definitions
227 //===----------------------------------------------------------------------===//
229 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
230 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
231 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
232 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
233 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
243 def BGEC; // Also aliased to blec with operands swapped
244 def BGEUC; // Also aliased to bleuc with operands swapped
249 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
252 def BLTC; // Also aliased to bgtc with operands swapped
253 def BLTUC; // Also aliased to bgtuc with operands swapped
265 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
266 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
269 // def LSA; // See MSA
273 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
274 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
275 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
276 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
277 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
278 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
279 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
280 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
281 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
282 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
284 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
285 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
286 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
287 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
288 def NAL; // BAL with rd=0
289 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
290 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
292 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
293 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
295 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
296 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
297 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
298 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;