1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
17 // Reencoded: jr -> jalr
18 // Reencoded: jr.hb -> jalr.hb
20 def brtarget21 : Operand<OtherVT> {
21 let EncoderMethod = "getBranchTarget21OpValue";
22 let OperandType = "OPERAND_PCREL";
23 let DecoderMethod = "DecodeBranchTarget21";
24 let ParserMatchClass = MipsJumpTargetAsmOperand;
27 def brtarget26 : Operand<OtherVT> {
28 let EncoderMethod = "getBranchTarget26OpValue";
29 let OperandType = "OPERAND_PCREL";
30 let DecoderMethod = "DecodeBranchTarget26";
31 let ParserMatchClass = MipsJumpTargetAsmOperand;
34 def jmpoffset16 : Operand<OtherVT> {
35 let EncoderMethod = "getJumpOffset16OpValue";
36 let ParserMatchClass = MipsJumpTargetAsmOperand;
39 def calloffset16 : Operand<iPTR> {
40 let EncoderMethod = "getJumpOffset16OpValue";
41 let ParserMatchClass = MipsJumpTargetAsmOperand;
44 //===----------------------------------------------------------------------===//
46 // Instruction Encodings
48 //===----------------------------------------------------------------------===//
50 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
51 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
52 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
53 class AUI_ENC : AUI_FM;
54 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
56 class BAL_ENC : BAL_FM;
57 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
58 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
59 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
60 DecodeDisambiguates<"AddiGroupBranch">;
61 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
62 DecodeDisambiguatedBy<"DaddiGroupBranch">;
63 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
64 DecodeDisambiguates<"DaddiGroupBranch">;
65 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
66 DecodeDisambiguatedBy<"DaddiGroupBranch">;
68 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
69 DecodeDisambiguates<"BgtzlGroupBranch">;
70 class BGEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>,
71 DecodeDisambiguatedBy<"BlezlGroupBranch">;
72 class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>,
73 DecodeDisambiguatedBy<"BlezGroupBranch">;
74 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
75 DecodeDisambiguates<"BlezlGroupBranch">;
76 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
77 DecodeDisambiguatedBy<"BgtzGroupBranch">;
79 class BLTC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZL>,
80 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
81 class BLTUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BGTZ>,
82 DecodeDisambiguatedBy<"BgtzGroupBranch">;
84 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
85 DecodeDisambiguatedBy<"BlezlGroupBranch">;
86 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
87 DecodeDisambiguates<"BgtzGroupBranch">;
88 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
89 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
91 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
92 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>,
93 DecodeDisambiguates<"BlezGroupBranch">;
94 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
96 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
97 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
98 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
99 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
101 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
102 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
103 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;
104 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
105 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>,
106 DecodeDisambiguatedBy<"BlezGroupBranch">;
107 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
108 DecodeDisambiguatedBy<"DaddiGroupBranch">;
109 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
110 DecodeDisambiguatedBy<"AddiGroupBranch">;
111 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
112 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
113 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
114 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
115 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
116 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
117 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
118 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
120 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
121 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
122 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
123 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
125 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
126 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
128 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
129 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
131 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
132 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
134 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
135 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
136 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
137 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
139 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
140 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
141 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
142 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
144 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
145 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
146 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
147 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
149 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
150 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
151 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
152 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
154 class CACHE_ENC : SPECIAL3_MEM_FM<OPCODE6_CACHE>;
155 class PREF_ENC : SPECIAL3_MEM_FM<OPCODE6_PREF>;
157 class LDC2_R6_ENC : COP2LDST_FM<OPCODE5_LDC2>;
158 class LWC2_R6_ENC : COP2LDST_FM<OPCODE5_LWC2>;
159 class SDC2_R6_ENC : COP2LDST_FM<OPCODE5_SDC2>;
160 class SWC2_R6_ENC : COP2LDST_FM<OPCODE5_SWC2>;
162 class LSA_R6_ENC : SPECIAL_LSA_FM<OPCODE6_LSA>;
164 class LL_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LL>;
165 class SC_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SC>;
167 class CLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLO>;
168 class CLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_CLZ>;
170 class SDBBP_R6_ENC : SPECIAL_SDBBP_FM;
172 //===----------------------------------------------------------------------===//
174 // Instruction Multiclasses
176 //===----------------------------------------------------------------------===//
178 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
179 RegisterOperand FGROpnd,
180 SDPatternOperator Op = null_frag> {
181 dag OutOperandList = (outs FGRCCOpnd:$fd);
182 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
183 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
184 list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
187 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
188 RegisterOperand FGROpnd>{
189 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>,
190 CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>,
191 ISA_MIPS32R6, HARDFLOAT;
192 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
193 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>,
194 ISA_MIPS32R6, HARDFLOAT;
195 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
196 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>,
197 ISA_MIPS32R6, HARDFLOAT;
198 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
199 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>,
200 ISA_MIPS32R6, HARDFLOAT;
201 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
202 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, setolt>,
203 ISA_MIPS32R6, HARDFLOAT;
204 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
205 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>,
206 ISA_MIPS32R6, HARDFLOAT;
207 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
208 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, setole>,
209 ISA_MIPS32R6, HARDFLOAT;
210 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
211 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>,
212 ISA_MIPS32R6, HARDFLOAT;
213 def CMP_SAF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SAF>,
214 CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>,
215 ISA_MIPS32R6, HARDFLOAT;
216 def CMP_SUN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUN>,
217 CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>,
218 ISA_MIPS32R6, HARDFLOAT;
219 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
220 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
221 ISA_MIPS32R6, HARDFLOAT;
222 def CMP_SUEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUEQ>,
223 CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>,
224 ISA_MIPS32R6, HARDFLOAT;
225 def CMP_SLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLT>,
226 CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>,
227 ISA_MIPS32R6, HARDFLOAT;
228 def CMP_SULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULT>,
229 CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>,
230 ISA_MIPS32R6, HARDFLOAT;
231 def CMP_SLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLE>,
232 CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>,
233 ISA_MIPS32R6, HARDFLOAT;
234 def CMP_SULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULE>,
235 CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>,
236 ISA_MIPS32R6, HARDFLOAT;
239 //===----------------------------------------------------------------------===//
241 // Instruction Descriptions
243 //===----------------------------------------------------------------------===//
245 class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
246 Operand ImmOpnd> : MipsR6Arch<instr_asm> {
247 dag OutOperandList = (outs GPROpnd:$rs);
248 dag InOperandList = (ins ImmOpnd:$imm);
249 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
250 list<dag> Pattern = [];
253 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
254 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
255 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2>;
257 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
258 Operand ImmOpnd> : MipsR6Arch<instr_asm> {
259 dag OutOperandList = (outs GPROpnd:$rd);
260 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
261 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
262 list<dag> Pattern = [];
265 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
267 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
268 : MipsR6Arch<instr_asm> {
269 dag OutOperandList = (outs GPROpnd:$rs);
270 dag InOperandList = (ins simm16:$imm);
271 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
272 list<dag> Pattern = [];
275 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
276 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
278 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
279 : MipsR6Arch<instr_asm> {
280 dag OutOperandList = (outs GPROpnd:$rs);
281 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
282 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
283 list<dag> Pattern = [];
286 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
288 class BRANCH_DESC_BASE {
290 bit isTerminator = 1;
291 bit hasDelaySlot = 0;
294 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE,
295 MipsR6Arch<instr_asm> {
296 dag InOperandList = (ins opnd:$offset);
297 dag OutOperandList = (outs);
298 string AsmString = !strconcat(instr_asm, "\t$offset");
302 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
303 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
304 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
305 dag OutOperandList = (outs);
306 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
307 list<Register> Defs = [AT];
310 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
311 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
312 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
313 dag OutOperandList = (outs);
314 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
315 list<Register> Defs = [AT];
318 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
319 RegisterOperand GPROpnd>
320 : BRANCH_DESC_BASE, MipsR6Arch<instr_asm> {
321 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
322 dag OutOperandList = (outs);
323 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
324 list<Register> Defs = [AT];
327 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
329 bit hasDelaySlot = 1;
330 list<Register> Defs = [RA];
333 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
335 list<Register> Defs = [RA];
338 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
339 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
340 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
341 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
342 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
344 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;
345 class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>;
347 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
348 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
350 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
351 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
353 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
354 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
356 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
357 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
358 dag OutOperandList = (outs);
359 string AsmString = instr_asm;
360 bit hasDelaySlot = 1;
363 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
364 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
366 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
367 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
368 dag OutOperandList = (outs);
369 string AsmString = instr_asm;
370 bit hasDelaySlot = 1;
373 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
374 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
376 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
377 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
379 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
380 RegisterOperand GPROpnd>
381 : MipsR6Arch<opstr> {
382 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
383 string AsmString = !strconcat(opstr, "\t$rt, $offset");
384 list<dag> Pattern = [];
385 bit isTerminator = 1;
386 bit hasDelaySlot = 0;
389 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
392 list<Register> Defs = [RA];
395 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
397 list<Register> Defs = [AT];
400 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
402 bit isIndirectBranch = 1;
403 bit hasDelaySlot = 1;
408 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
409 : MipsR6Arch<instr_asm> {
410 dag OutOperandList = (outs GPROpnd:$rd);
411 dag InOperandList = (ins GPROpnd:$rt);
412 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
413 list<dag> Pattern = [];
416 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
418 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
419 SDPatternOperator Op=null_frag>
420 : MipsR6Arch<instr_asm> {
421 dag OutOperandList = (outs GPROpnd:$rd);
422 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
423 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
424 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
426 // This instruction doesn't trap division by zero itself. We must insert
427 // teq instructions as well.
428 bit usesCustomInserter = 1;
431 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, sdiv>;
432 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>;
433 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>;
434 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>;
436 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
437 list<Register> Defs = [RA];
440 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
441 list<Register> Defs = [RA];
444 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
445 list<Register> Defs = [RA];
448 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
449 list<Register> Defs = [RA];
452 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
453 list<Register> Defs = [RA];
456 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
457 list<Register> Defs = [RA];
460 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
461 SDPatternOperator Op=null_frag> : MipsR6Arch<instr_asm> {
462 dag OutOperandList = (outs GPROpnd:$rd);
463 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
464 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
465 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
468 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>;
469 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>;
470 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;
471 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
473 class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
474 dag OutOperandList = (outs FGROpnd:$fd);
475 dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
476 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
477 list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in,
480 string Constraints = "$fd_in = $fd";
483 class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
484 // We must insert a SUBREG_TO_REG around $fd_in
485 bit usesCustomInserter = 1;
487 class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
489 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
490 : MipsR6Arch<instr_asm> {
491 dag OutOperandList = (outs GPROpnd:$rd);
492 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
493 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
494 list<dag> Pattern = [];
497 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
498 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
500 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
501 dag OutOperandList = (outs FGROpnd:$fd);
502 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
503 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
504 list<dag> Pattern = [];
505 string Constraints = "$fd_in = $fd";
508 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
509 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
510 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
511 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
513 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
514 dag OutOperandList = (outs FGROpnd:$fd);
515 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
516 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
517 list<dag> Pattern = [];
520 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
521 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
522 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
523 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
525 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
526 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
527 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
528 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
530 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
531 dag OutOperandList = (outs FGROpnd:$fd);
532 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
533 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
534 list<dag> Pattern = [];
537 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
538 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
539 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
540 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
542 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
543 dag OutOperandList = (outs FGROpnd:$fd);
544 dag InOperandList = (ins FGROpnd:$fs);
545 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
546 list<dag> Pattern = [];
549 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
550 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
551 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
552 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
554 class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd,
555 RegisterOperand GPROpnd> : MipsR6Arch<instr_asm> {
556 dag OutOperandList = (outs);
557 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
558 string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
559 list<dag> Pattern = [];
560 string DecoderMethod = "DecodeCacheOpR6";
563 class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>;
564 class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, GPR32Opnd>;
566 class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> {
567 dag OutOperandList = (outs COPOpnd:$rt);
568 dag InOperandList = (ins mem_simm11:$addr);
569 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
570 list<dag> Pattern = [];
572 string DecoderMethod = "DecodeFMemCop2R6";
575 class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd>;
576 class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd>;
578 class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> {
579 dag OutOperandList = (outs);
580 dag InOperandList = (ins COPOpnd:$rt, mem_simm11:$addr);
581 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
582 list<dag> Pattern = [];
584 string DecoderMethod = "DecodeFMemCop2R6";
587 class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd>;
588 class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd>;
590 class LSA_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
591 Operand ImmOpnd> : MipsR6Arch<instr_asm> {
592 dag OutOperandList = (outs GPROpnd:$rd);
593 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
594 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2");
595 list<dag> Pattern = [];
598 class LSA_R6_DESC : LSA_R6_DESC_BASE<"lsa", GPR32Opnd, uimm2>;
600 class LL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
601 dag OutOperandList = (outs GPROpnd:$rt);
602 dag InOperandList = (ins mem_simm9:$addr);
603 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
604 list<dag> Pattern = [];
608 class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd>;
610 class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
611 dag OutOperandList = (outs GPROpnd:$dst);
612 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
613 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
614 list<dag> Pattern = [];
616 string Constraints = "$rt = $dst";
619 class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd>;
621 class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
622 : MipsR6Arch<instr_asm> {
623 dag OutOperandList = (outs GPROpnd:$rd);
624 dag InOperandList = (ins GPROpnd:$rs);
625 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
628 class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> :
629 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> {
630 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz (not GPROpnd:$rs)))];
633 class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> :
634 CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> {
635 list<dag> Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))];
638 class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd>;
639 class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd>;
641 class SDBBP_R6_DESC {
642 dag OutOperandList = (outs);
643 dag InOperandList = (ins uimm20:$code_);
644 string AsmString = "sdbbp\t$code_";
645 list<dag> Pattern = [];
648 //===----------------------------------------------------------------------===//
650 // Instruction Definitions
652 //===----------------------------------------------------------------------===//
654 def ADDIUPC : R6MMR6Rel, ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
655 def ALIGN : R6MMR6Rel, ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
656 def ALUIPC : R6MMR6Rel, ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
657 def AUI : R6MMR6Rel, AUI_ENC, AUI_DESC, ISA_MIPS32R6;
658 def AUIPC : R6MMR6Rel, AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
659 def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6;
660 def BALC : R6MMR6Rel, BALC_ENC, BALC_DESC, ISA_MIPS32R6;
661 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT;
662 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6, HARDFLOAT;
663 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
664 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
665 def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6;
666 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
667 def BEQZALC : R6MMR6Rel, BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
668 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
669 def BGEC : BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
670 def BGEUC : BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
671 def BGEZALC : R6MMR6Rel, BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
672 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
673 def BGTZALC : R6MMR6Rel, BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
674 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
675 def BITSWAP : R6MMR6Rel, BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
676 def BLEZALC : R6MMR6Rel, BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
677 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
678 def BLTC : BLTC_ENC, BLTC_DESC, ISA_MIPS32R6;
679 def BLTUC : BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6;
680 def BLTZALC : R6MMR6Rel, BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
681 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
682 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
683 def BNEZALC : R6MMR6Rel, BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
684 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
685 def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
686 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
687 def CACHE_R6 : R6MMR6Rel, CACHE_ENC, CACHE_DESC, ISA_MIPS32R6;
688 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6, HARDFLOAT;
689 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6, HARDFLOAT;
690 def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
691 def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
692 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
693 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
694 def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6;
695 def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
696 def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
697 def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6;
698 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
699 def LDC2_R6 : LDC2_R6_ENC, LDC2_R6_DESC, ISA_MIPS32R6;
700 def LL_R6 : LL_R6_ENC, LL_R6_DESC, ISA_MIPS32R6;
701 def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
702 def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
703 def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
704 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
705 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
706 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
707 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
708 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
709 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT;
710 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6, HARDFLOAT;
711 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
712 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
713 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;
714 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;
715 def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6;
716 def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;
717 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
718 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
719 def MUH : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6;
720 def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
721 def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
722 def MULU : R6MMR6Rel, MULU_ENC, MULU_DESC, ISA_MIPS32R6;
723 def NAL; // BAL with rd=0
724 def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
725 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
726 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
727 def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
728 def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
729 def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
730 def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
731 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, HARDFLOAT;
732 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6, HARDFLOAT;
733 def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
734 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6, HARDFLOAT;
735 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6, HARDFLOAT;
736 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6, HARDFLOAT;
737 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6, HARDFLOAT;
738 def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
740 //===----------------------------------------------------------------------===//
742 // Instruction Aliases
744 //===----------------------------------------------------------------------===//
746 def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
747 def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6;
749 //===----------------------------------------------------------------------===//
751 // Patterns and Pseudo Instructions
753 //===----------------------------------------------------------------------===//
755 // f32 comparisons supported via another comparison
756 def : MipsPat<(setone f32:$lhs, f32:$rhs),
757 (NOR (CMP_UEQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
758 def : MipsPat<(seto f32:$lhs, f32:$rhs),
759 (NOR (CMP_UN_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
760 def : MipsPat<(setune f32:$lhs, f32:$rhs),
761 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
762 def : MipsPat<(seteq f32:$lhs, f32:$rhs), (CMP_EQ_S f32:$lhs, f32:$rhs)>,
764 def : MipsPat<(setgt f32:$lhs, f32:$rhs), (CMP_LE_S f32:$rhs, f32:$lhs)>,
766 def : MipsPat<(setge f32:$lhs, f32:$rhs), (CMP_LT_S f32:$rhs, f32:$lhs)>,
768 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_LT_S f32:$lhs, f32:$rhs)>,
770 def : MipsPat<(setle f32:$lhs, f32:$rhs), (CMP_LE_S f32:$lhs, f32:$rhs)>,
772 def : MipsPat<(setne f32:$lhs, f32:$rhs),
773 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
775 // f64 comparisons supported via another comparison
776 def : MipsPat<(setone f64:$lhs, f64:$rhs),
777 (NOR (CMP_UEQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
778 def : MipsPat<(seto f64:$lhs, f64:$rhs),
779 (NOR (CMP_UN_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
780 def : MipsPat<(setune f64:$lhs, f64:$rhs),
781 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
782 def : MipsPat<(seteq f64:$lhs, f64:$rhs), (CMP_EQ_D f64:$lhs, f64:$rhs)>,
784 def : MipsPat<(setgt f64:$lhs, f64:$rhs), (CMP_LE_D f64:$rhs, f64:$lhs)>,
786 def : MipsPat<(setge f64:$lhs, f64:$rhs), (CMP_LT_D f64:$rhs, f64:$lhs)>,
788 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_LT_D f64:$lhs, f64:$rhs)>,
790 def : MipsPat<(setle f64:$lhs, f64:$rhs), (CMP_LE_D f64:$lhs, f64:$rhs)>,
792 def : MipsPat<(setne f64:$lhs, f64:$rhs),
793 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
796 def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
797 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
799 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, i32:$f),
800 (OR (SELEQZ i32:$t, i32:$cond), (SELNEZ i32:$f, i32:$cond))>,
802 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, i32:$f),
803 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
805 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
806 (OR (SELEQZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
807 (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
809 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
810 (OR (SELNEZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
811 (SELEQZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
813 def : MipsPat<(select (i32 (setgt i32:$cond, immSExt16Plus1:$imm)), i32:$t,
815 (OR (SELEQZ i32:$t, (SLTi i32:$cond, (Plus1 imm:$imm))),
816 (SELNEZ i32:$f, (SLTi i32:$cond, (Plus1 imm:$imm))))>,
818 def : MipsPat<(select (i32 (setugt i32:$cond, immSExt16Plus1:$imm)),
820 (OR (SELEQZ i32:$t, (SLTiu i32:$cond, (Plus1 imm:$imm))),
821 (SELNEZ i32:$f, (SLTiu i32:$cond, (Plus1 imm:$imm))))>,
824 def : MipsPat<(select i32:$cond, i32:$t, immz),
825 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
826 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, immz),
827 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
828 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, immz),
829 (SELEQZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
830 def : MipsPat<(select i32:$cond, immz, i32:$f),
831 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
832 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i32:$f),
833 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
834 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i32:$f),
835 (SELNEZ i32:$f, i32:$cond)>, ISA_MIPS32R6;