1 //=- Mips32r6InstrInfo.td - Mips32r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips32r6 instructions.
12 //===----------------------------------------------------------------------===//
14 include "Mips32r6InstrFormats.td"
16 // Notes about removals/changes from MIPS32r6:
18 // Reencoded: cache, pref
19 // Reencoded: clo, clz
20 // Reencoded: jr -> jalr
21 // Reencoded: jr.hb -> jalr.hb
28 // Removed: bc1any2, bc1any4
32 // Rencoded: [ls][wd]c2
34 def brtarget21 : Operand<OtherVT> {
35 let EncoderMethod = "getBranchTarget21OpValue";
36 let OperandType = "OPERAND_PCREL";
37 let DecoderMethod = "DecodeBranchTarget21";
38 let ParserMatchClass = MipsJumpTargetAsmOperand;
41 def brtarget26 : Operand<OtherVT> {
42 let EncoderMethod = "getBranchTarget26OpValue";
43 let OperandType = "OPERAND_PCREL";
44 let DecoderMethod = "DecodeBranchTarget26";
45 let ParserMatchClass = MipsJumpTargetAsmOperand;
48 def jmpoffset16 : Operand<OtherVT> {
49 let EncoderMethod = "getJumpOffset16OpValue";
50 let ParserMatchClass = MipsJumpTargetAsmOperand;
53 def calloffset16 : Operand<iPTR> {
54 let EncoderMethod = "getJumpOffset16OpValue";
55 let ParserMatchClass = MipsJumpTargetAsmOperand;
58 //===----------------------------------------------------------------------===//
60 // Instruction Encodings
62 //===----------------------------------------------------------------------===//
64 class ADDIUPC_ENC : PCREL19_FM<OPCODE2_ADDIUPC>;
65 class ALIGN_ENC : SPECIAL3_ALIGN_FM<OPCODE6_ALIGN>;
66 class ALUIPC_ENC : PCREL16_FM<OPCODE5_ALUIPC>;
67 class AUI_ENC : AUI_FM;
68 class AUIPC_ENC : PCREL16_FM<OPCODE5_AUIPC>;
70 class BALC_ENC : BRANCH_OFF26_FM<0b111010>;
71 class BC_ENC : BRANCH_OFF26_FM<0b110010>;
72 class BEQC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
73 DecodeDisambiguates<"AddiGroupBranch">;
74 class BEQZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_ADDI>,
75 DecodeDisambiguatedBy<"DaddiGroupBranch">;
76 class BNEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
77 DecodeDisambiguates<"DaddiGroupBranch">;
78 class BNEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_DADDI>,
79 DecodeDisambiguatedBy<"DaddiGroupBranch">;
81 class BLTZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZL>,
82 DecodeDisambiguates<"BgtzlGroupBranch">;
83 class BGEC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZL>,
84 DecodeDisambiguatedBy<"BlezlGroupBranch">;
85 class BGEUC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_BLEZ>,
86 DecodeDisambiguatedBy<"BlezGroupBranch">;
87 class BGEZC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZL>,
88 DecodeDisambiguates<"BlezlGroupBranch">;
89 class BGTZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZ>,
90 DecodeDisambiguatedBy<"BgtzGroupBranch">;
92 class BLEZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZL>,
93 DecodeDisambiguatedBy<"BlezlGroupBranch">;
94 class BLTZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BGTZ>,
95 DecodeDisambiguates<"BgtzGroupBranch">;
96 class BGTZC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BGTZL>,
97 DecodeDisambiguatedBy<"BgtzlGroupBranch">;
99 class BEQZC_ENC : CMP_BRANCH_OFF21_FM<0b110110>;
100 class BGEZALC_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM<OPGROUP_BLEZ>,
101 DecodeDisambiguates<"BlezGroupBranch">;
102 class BNEZC_ENC : CMP_BRANCH_OFF21_FM<0b111110>;
104 class BC1EQZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1EQZ>;
105 class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>;
106 class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>;
107 class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>;
109 class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>;
110 class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>;
111 class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>;
112 class BITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_BITSWAP>;
113 class BLEZALC_ENC : CMP_BRANCH_1R_RT_OFF16_FM<OPGROUP_BLEZ>,
114 DecodeDisambiguatedBy<"BlezGroupBranch">;
115 class BNVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_DADDI>,
116 DecodeDisambiguatedBy<"DaddiGroupBranch">;
117 class BOVC_ENC : CMP_BRANCH_2R_OFF16_FM<OPGROUP_ADDI>,
118 DecodeDisambiguatedBy<"AddiGroupBranch">;
119 class DIV_ENC : SPECIAL_3R_FM<0b00010, 0b011010>;
120 class DIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011011>;
121 class MOD_ENC : SPECIAL_3R_FM<0b00011, 0b011010>;
122 class MODU_ENC : SPECIAL_3R_FM<0b00011, 0b011011>;
123 class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>;
124 class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>;
125 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
126 class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>;
128 class MADDF_S_ENC : COP1_3R_FM<0b011000, FIELD_FMT_S>;
129 class MADDF_D_ENC : COP1_3R_FM<0b011000, FIELD_FMT_D>;
130 class MSUBF_S_ENC : COP1_3R_FM<0b011001, FIELD_FMT_S>;
131 class MSUBF_D_ENC : COP1_3R_FM<0b011001, FIELD_FMT_D>;
133 class SEL_D_ENC : COP1_3R_FM<0b010000, FIELD_FMT_D>;
134 class SEL_S_ENC : COP1_3R_FM<0b010000, FIELD_FMT_S>;
136 class SELEQZ_ENC : SPECIAL_3R_FM<0b00000, 0b110101>;
137 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
139 class LWPC_ENC : PCREL19_FM<OPCODE2_LWPC>;
140 class LWUPC_ENC : PCREL19_FM<OPCODE2_LWUPC>;
142 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
143 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
144 class MIN_S_ENC : COP1_3R_FM<0b011100, FIELD_FMT_S>;
145 class MIN_D_ENC : COP1_3R_FM<0b011100, FIELD_FMT_D>;
147 class MAXA_S_ENC : COP1_3R_FM<0b011111, FIELD_FMT_S>;
148 class MAXA_D_ENC : COP1_3R_FM<0b011111, FIELD_FMT_D>;
149 class MINA_S_ENC : COP1_3R_FM<0b011110, FIELD_FMT_S>;
150 class MINA_D_ENC : COP1_3R_FM<0b011110, FIELD_FMT_D>;
152 class SELEQZ_S_ENC : COP1_3R_FM<0b010100, FIELD_FMT_S>;
153 class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>;
154 class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>;
155 class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>;
157 class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>;
158 class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>;
159 class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>;
160 class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>;
162 class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
163 RegisterOperand FGROpnd,
164 SDPatternOperator Op = null_frag> {
165 dag OutOperandList = (outs FGRCCOpnd:$fd);
166 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
167 string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
168 list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
171 //===----------------------------------------------------------------------===//
173 // Instruction Multiclasses
175 //===----------------------------------------------------------------------===//
177 multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
178 RegisterOperand FGROpnd>{
179 def CMP_F_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_F>,
180 CMP_CONDN_DESC_BASE<"f", Typestr, FGROpnd>,
182 def CMP_UN_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
183 CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>,
185 def CMP_EQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
186 CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>,
188 def CMP_UEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>,
189 CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>,
191 def CMP_OLT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLT>,
192 CMP_CONDN_DESC_BASE<"olt", Typestr, FGROpnd, setolt>,
194 def CMP_ULT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>,
195 CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>,
197 def CMP_OLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_OLE>,
198 CMP_CONDN_DESC_BASE<"ole", Typestr, FGROpnd, setole>,
200 def CMP_ULE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>,
201 CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>,
203 def CMP_SF_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SF>,
204 CMP_CONDN_DESC_BASE<"sf", Typestr, FGROpnd>,
206 def CMP_NGLE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGLE>,
207 CMP_CONDN_DESC_BASE<"ngle", Typestr, FGROpnd>,
209 def CMP_SEQ_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>,
210 CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
212 def CMP_NGL_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGL>,
213 CMP_CONDN_DESC_BASE<"ngl", Typestr, FGROpnd>,
215 def CMP_LT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
216 CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
218 def CMP_NGE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGE>,
219 CMP_CONDN_DESC_BASE<"nge", Typestr, FGROpnd>,
221 def CMP_LE_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
222 CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
224 def CMP_NGT_#NAME : COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_NGT>,
225 CMP_CONDN_DESC_BASE<"ngt", Typestr, FGROpnd>,
229 //===----------------------------------------------------------------------===//
231 // Instruction Descriptions
233 //===----------------------------------------------------------------------===//
235 class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
237 dag OutOperandList = (outs GPROpnd:$rs);
238 dag InOperandList = (ins ImmOpnd:$imm);
239 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
240 list<dag> Pattern = [];
243 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
244 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
245 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2>;
247 class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
249 dag OutOperandList = (outs GPROpnd:$rd);
250 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
251 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
252 list<dag> Pattern = [];
255 class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
257 class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
258 dag OutOperandList = (outs GPROpnd:$rs);
259 dag InOperandList = (ins simm16:$imm);
260 string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
261 list<dag> Pattern = [];
264 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
265 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
267 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
268 dag OutOperandList = (outs GPROpnd:$rs);
269 dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
270 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
271 list<dag> Pattern = [];
274 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
276 class BRANCH_DESC_BASE {
278 bit isTerminator = 1;
279 bit hasDelaySlot = 0;
282 class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE {
283 dag InOperandList = (ins opnd:$offset);
284 dag OutOperandList = (outs);
285 string AsmString = !strconcat(instr_asm, "\t$offset");
289 class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
290 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
291 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset);
292 dag OutOperandList = (outs);
293 string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
294 list<Register> Defs = [AT];
297 class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
298 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
299 dag InOperandList = (ins GPROpnd:$rs, opnd:$offset);
300 dag OutOperandList = (outs);
301 string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
302 list<Register> Defs = [AT];
305 class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
306 RegisterOperand GPROpnd> : BRANCH_DESC_BASE {
307 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
308 dag OutOperandList = (outs);
309 string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
310 list<Register> Defs = [AT];
313 class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
315 list<Register> Defs = [RA];
318 class BC_DESC : BC_DESC_BASE<"bc", brtarget26>;
319 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
320 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
321 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
322 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
324 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
325 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
327 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
328 class BGTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR32Opnd>;
330 class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
331 class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
333 class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
334 dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
335 dag OutOperandList = (outs);
336 string AsmString = instr_asm;
337 bit hasDelaySlot = 1;
340 class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
341 class BC1NEZ_DESC : COP1_BCCZ_DESC_BASE<"bc1nez $ft, $offset">;
343 class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
344 dag InOperandList = (ins COP2Opnd:$ct, brtarget:$offset);
345 dag OutOperandList = (outs);
346 string AsmString = instr_asm;
347 bit hasDelaySlot = 1;
350 class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
351 class BC2NEZ_DESC : COP2_BCCZ_DESC_BASE<"bc2nez $ct, $offset">;
353 class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
354 class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
356 class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
357 RegisterOperand GPROpnd> {
358 dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
359 string AsmString = !strconcat(opstr, "\t$rt, $offset");
360 list<dag> Pattern = [];
361 bit isTerminator = 1;
362 bit hasDelaySlot = 0;
363 string DecoderMethod = "DecodeSimm16";
366 class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
369 list<Register> Defs = [RA];
372 class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR32Opnd> {
374 list<Register> Defs = [AT];
377 class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
379 bit isIndirectBranch = 1;
380 bit hasDelaySlot = 1;
385 class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
386 dag OutOperandList = (outs GPROpnd:$rd);
387 dag InOperandList = (ins GPROpnd:$rt);
388 string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
389 list<dag> Pattern = [];
392 class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
394 class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
395 SDPatternOperator Op=null_frag> {
396 dag OutOperandList = (outs GPROpnd:$rd);
397 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
398 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
399 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
401 // This instruction doesn't trap division by zero itself. We must insert
402 // teq instructions as well.
403 bit usesCustomInserter = 1;
406 class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, sdiv>;
407 class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>;
408 class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>;
409 class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>;
411 class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
412 list<Register> Defs = [RA];
415 class BGEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
416 list<Register> Defs = [RA];
419 class BGTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
420 list<Register> Defs = [RA];
423 class BLEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
424 list<Register> Defs = [RA];
427 class BLTZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
428 list<Register> Defs = [RA];
431 class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
432 list<Register> Defs = [RA];
435 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
436 SDPatternOperator Op=null_frag> {
437 dag OutOperandList = (outs GPROpnd:$rd);
438 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
439 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
440 list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
443 class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>;
444 class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>;
445 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;
446 class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
448 class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
449 dag OutOperandList = (outs FGROpnd:$fd);
450 dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
451 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
452 list<dag> Pattern = [(set FGROpnd:$fd, (select FGRCCOpnd:$fd_in,
455 string Constraints = "$fd_in = $fd";
458 class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> {
459 // We must insert a SUBREG_TO_REG around $fd_in
460 bit usesCustomInserter = 1;
462 class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
464 class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
465 dag OutOperandList = (outs GPROpnd:$rd);
466 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
467 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
468 list<dag> Pattern = [];
471 class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
472 class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
474 class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
475 dag OutOperandList = (outs FGROpnd:$fd);
476 dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
477 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
478 list<dag> Pattern = [];
479 string Constraints = "$fd_in = $fd";
482 class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
483 class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
484 class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
485 class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
487 class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
488 dag OutOperandList = (outs FGROpnd:$fd);
489 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
490 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
491 list<dag> Pattern = [];
494 class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
495 class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
496 class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
497 class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
499 class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
500 class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
501 class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
502 class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
504 class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
505 dag OutOperandList = (outs FGROpnd:$fd);
506 dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
507 string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
508 list<dag> Pattern = [];
511 class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
512 class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
513 class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
514 class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
516 class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
517 dag OutOperandList = (outs FGROpnd:$fd);
518 dag InOperandList = (ins FGROpnd:$fs);
519 string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
520 list<dag> Pattern = [];
523 class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
524 class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
525 class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
526 class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
528 //===----------------------------------------------------------------------===//
530 // Instruction Definitions
532 //===----------------------------------------------------------------------===//
534 def ADDIUPC : ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
535 def ALIGN : ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
536 def ALUIPC : ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
537 def AUI : AUI_ENC, AUI_DESC, ISA_MIPS32R6;
538 def AUIPC : AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
539 def BALC : BALC_ENC, BALC_DESC, ISA_MIPS32R6;
540 def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6;
541 def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6;
542 def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
543 def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
544 def BC : BC_ENC, BC_DESC, ISA_MIPS32R6;
545 def BEQC : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
546 def BEQZALC : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
547 def BEQZC : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
548 def BGEC : BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
549 def BGEUC : BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
550 def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
551 def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
552 def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
553 def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
554 def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
555 def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
556 def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
557 def BLTC; // Also aliased to bgtc with operands swapped
558 def BLTUC; // Also aliased to bgtuc with operands swapped
559 def BLTZALC : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
560 def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
561 def BNEC : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
562 def BNEZALC : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
563 def BNEZC : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
564 def BNVC : BNVC_ENC, BNVC_DESC, ISA_MIPS32R6;
565 def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6;
566 def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6;
567 def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6;
568 defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>;
569 defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>;
570 def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6;
571 def DIVU : DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
572 def JIALC : JIALC_ENC, JIALC_DESC, ISA_MIPS32R6;
573 def JIC : JIC_ENC, JIC_DESC, ISA_MIPS32R6;
574 def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6;
575 // def LSA; // See MSA
576 def LWPC : LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
577 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
578 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6;
579 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6;
580 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
581 def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
582 def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
583 def MAX_S : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
584 def MINA_D : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
585 def MINA_S : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
586 def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
587 def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
588 def MOD : MOD_ENC, MOD_DESC, ISA_MIPS32R6;
589 def MODU : MODU_ENC, MODU_DESC, ISA_MIPS32R6;
590 def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6;
591 def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6;
592 def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6;
593 def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
594 def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
595 def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6;
596 def NAL; // BAL with rd=0
597 def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6;
598 def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6;
599 def SELEQZ : SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
600 def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6;
601 def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6;
602 def SELNEZ : SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
603 def SELNEZ_D : SELNEZ_D_ENC, SELNEZ_D_DESC, ISA_MIPS32R6;
604 def SELNEZ_S : SELNEZ_S_ENC, SELNEZ_S_DESC, ISA_MIPS32R6;
605 def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
606 def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;
608 //===----------------------------------------------------------------------===//
610 // Patterns and Pseudo Instructions
612 //===----------------------------------------------------------------------===//
614 // f32 comparisons supported via another comparison
615 def : MipsPat<(setone f32:$lhs, f32:$rhs),
616 (NOR (CMP_UEQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
617 def : MipsPat<(seto f32:$lhs, f32:$rhs),
618 (NOR (CMP_UN_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
619 def : MipsPat<(setune f32:$lhs, f32:$rhs),
620 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
621 def : MipsPat<(seteq f32:$lhs, f32:$rhs), (CMP_EQ_S f32:$lhs, f32:$rhs)>,
623 def : MipsPat<(setgt f32:$lhs, f32:$rhs), (CMP_LE_S f32:$rhs, f32:$lhs)>,
625 def : MipsPat<(setge f32:$lhs, f32:$rhs), (CMP_LT_S f32:$rhs, f32:$lhs)>,
627 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLT_S f32:$lhs, f32:$rhs)>,
629 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_OLE_S f32:$lhs, f32:$rhs)>,
631 def : MipsPat<(setne f32:$lhs, f32:$rhs),
632 (NOR (CMP_EQ_S f32:$lhs, f32:$rhs), ZERO)>, ISA_MIPS32R6;
634 // f64 comparisons supported via another comparison
635 def : MipsPat<(setone f64:$lhs, f64:$rhs),
636 (NOR (CMP_UEQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
637 def : MipsPat<(seto f64:$lhs, f64:$rhs),
638 (NOR (CMP_UN_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
639 def : MipsPat<(setune f64:$lhs, f64:$rhs),
640 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
641 def : MipsPat<(seteq f64:$lhs, f64:$rhs), (CMP_EQ_D f64:$lhs, f64:$rhs)>,
643 def : MipsPat<(setgt f64:$lhs, f64:$rhs), (CMP_LE_D f64:$rhs, f64:$lhs)>,
645 def : MipsPat<(setge f64:$lhs, f64:$rhs), (CMP_LT_D f64:$rhs, f64:$lhs)>,
647 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLT_D f64:$lhs, f64:$rhs)>,
649 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_OLE_D f64:$lhs, f64:$rhs)>,
651 def : MipsPat<(setne f64:$lhs, f64:$rhs),
652 (NOR (CMP_EQ_D f64:$lhs, f64:$rhs), ZERO)>, ISA_MIPS32R6;
655 def : MipsPat<(select i32:$cond, i32:$t, i32:$f),
656 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
658 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, i32:$f),
659 (OR (SELNEZ i32:$t, i32:$cond), (SELEQZ i32:$f, i32:$cond))>,
661 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, i32:$f),
662 (OR (SELNEZ i32:$f, i32:$cond), (SELEQZ i32:$t, i32:$cond))>,
664 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
665 (OR (SELNEZ i32:$t, (XORi i32:$cond, immZExt16:$imm)),
666 (SELEQZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>,
668 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i32:$t, i32:$f),
669 (OR (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)),
670 (SELEQZ i32:$t, (XORi i32:$cond, immZExt16:$imm)))>,
672 def : MipsPat<(select (i32 (setgt i32:$cond, immSExt16Plus1:$imm)), i32:$t,
674 (OR (SELNEZ i32:$t, (SLTi i32:$cond, (Plus1 imm:$imm))),
675 (SELEQZ i32:$f, (SLTi i32:$cond, (Plus1 imm:$imm))))>,
677 def : MipsPat<(select (i32 (setugt i32:$cond, immSExt16Plus1:$imm)),
679 (OR (SELNEZ i32:$t, (SLTiu i32:$cond, (Plus1 imm:$imm))),
680 (SELEQZ i32:$f, (SLTiu i32:$cond, (Plus1 imm:$imm))))>,
683 def : MipsPat<(select i32:$cond, i32:$t, immz),
684 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
685 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i32:$t, immz),
686 (SELNEZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
687 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i32:$t, immz),
688 (SELEQZ i32:$t, i32:$cond)>, ISA_MIPS32R6;
689 def : MipsPat<(select i32:$cond, immz, i32:$f),
690 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
691 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i32:$f),
692 (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6;
693 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i32:$f),
694 (SELNEZ i32:$f, i32:$cond)>, ISA_MIPS32R6;