1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
18 // Instruction operand types
19 def shamt_64 : Operand<i64>;
22 def uimm16_64 : Operand<i64> {
23 let PrintMethod = "printUnsignedImm";
26 // Transformation Function - get Imm - 32.
27 def Subtract32 : SDNodeXForm<imm, [{
28 return getI32Imm((unsigned)N->getZExtValue() - 32);
31 // shamt field must fit in 5 bits.
32 def immZExt5_64 : ImmLeaf<i64, [{return Imm == (Imm & 0x1f);}]>;
34 // imm32_63 predicate - True if imm is in range [32, 63].
35 def imm32_63 : ImmLeaf<i64,
36 [{return (int32_t)Imm >= 32 && (int32_t)Imm < 64;}],
39 //===----------------------------------------------------------------------===//
40 // Instructions specific format
41 //===----------------------------------------------------------------------===//
43 // 64-bit shift instructions.
44 class shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm,
46 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5_64, shamt_64,
49 class shift_rotate_imm64_32<bits<6> func, bits<5> isRotate, string instr_asm,
51 shift_rotate_imm<func, isRotate, instr_asm, OpNode, imm32_63, shamt_64,
55 class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>:
56 Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
57 class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
58 Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
60 //===----------------------------------------------------------------------===//
61 // Instruction definition
62 //===----------------------------------------------------------------------===//
64 /// Arithmetic Instructions (ALU Immediate)
65 def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16,
67 def DANDi : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>;
68 def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
69 def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
70 def ORi64 : ArithLogicI<0x0d, "ori", or, uimm16_64, immZExt16, CPU64Regs>;
71 def XORi64 : ArithLogicI<0x0e, "xori", xor, uimm16_64, immZExt16, CPU64Regs>;
73 /// Arithmetic Instructions (3-Operand, R-Type)
74 def DADDu : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>;
75 def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", sub, IIAlu, CPU64Regs>;
76 def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
77 def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>;
78 def AND64 : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPU64Regs, 1>;
79 def OR64 : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPU64Regs, 1>;
80 def XOR64 : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>;
81 def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>;
83 /// Shift Instructions
84 def DSLL : shift_rotate_imm64<0x38, 0x00, "dsll", shl>;
85 def DSRL : shift_rotate_imm64<0x3a, 0x00, "dsrl", srl>;
86 def DSRA : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>;
87 def DSLL32 : shift_rotate_imm64_32<0x3c, 0x00, "dsll32", shl>;
88 def DSRL32 : shift_rotate_imm64_32<0x3e, 0x00, "dsrl32", srl>;
89 def DSRA32 : shift_rotate_imm64_32<0x3f, 0x00, "dsra32", sra>;
90 def DSLLV : shift_rotate_reg<0x24, 0x00, "dsllv", shl, CPU64Regs>;
91 def DSRLV : shift_rotate_reg<0x26, 0x00, "dsrlv", srl, CPU64Regs>;
92 def DSRAV : shift_rotate_reg<0x27, 0x00, "dsrav", sra, CPU64Regs>;
94 // Rotate Instructions
95 let Predicates = [HasMips64r2] in {
96 def DROTR : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>;
97 def DROTR32 : shift_rotate_imm64_32<0x3e, 0x01, "drotr32", rotr>;
98 def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>;
101 /// Load and Store Instructions
103 defm LB64 : LoadM64<0x20, "lb", sextloadi8>;
104 defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>;
105 defm LH64 : LoadM64<0x21, "lh", sextloadi16_a>;
106 defm LHu64 : LoadM64<0x25, "lhu", zextloadi16_a>;
107 defm LW64 : LoadM64<0x23, "lw", sextloadi32_a>;
108 defm LWu64 : LoadM64<0x27, "lwu", zextloadi32_a>;
109 defm SB64 : StoreM64<0x28, "sb", truncstorei8>;
110 defm SH64 : StoreM64<0x29, "sh", truncstorei16_a>;
111 defm SW64 : StoreM64<0x2b, "sw", truncstorei32_a>;
112 defm LD : LoadM64<0x37, "ld", load_a>;
113 defm SD : StoreM64<0x3f, "sd", store_a>;
116 defm ULH64 : LoadM64<0x21, "ulh", sextloadi16_u, 1>;
117 defm ULHu64 : LoadM64<0x25, "ulhu", zextloadi16_u, 1>;
118 defm ULW64 : LoadM64<0x23, "ulw", sextloadi32_u, 1>;
119 defm USH64 : StoreM64<0x29, "ush", truncstorei16_u, 1>;
120 defm USW64 : StoreM64<0x2b, "usw", truncstorei32_u, 1>;
121 defm ULD : LoadM64<0x37, "uld", load_u, 1>;
122 defm USD : StoreM64<0x3f, "usd", store_u, 1>;
124 /// Jump and Branch Instructions
125 def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>;
126 def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>;
127 def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>;
128 def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>;
129 def BLEZ64 : CBranchZero<0x07, 0, "blez", setle, CPU64Regs>;
130 def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>;
132 /// Multiply and Divide Instructions.
133 def DMULT : Mult64<0x1c, "dmult", IIImul>;
134 def DMULTu : Mult64<0x1d, "dmultu", IIImul>;
135 def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
136 def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>;
138 def MTHI64 : MoveToLOHI<0x11, "mthi", CPU64Regs, [HI64]>;
139 def MTLO64 : MoveToLOHI<0x13, "mtlo", CPU64Regs, [LO64]>;
140 def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>;
141 def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>;
144 def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>;
145 def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>;
147 //===----------------------------------------------------------------------===//
148 // Arbitrary patterns that map to one or more instructions
149 //===----------------------------------------------------------------------===//
152 def : Pat<(i64 immSExt16:$in),
153 (DADDiu ZERO_64, imm:$in)>;
154 def : Pat<(i64 immZExt16:$in),
155 (ORi64 ZERO_64, imm:$in)>;
158 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>,
160 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>,
164 def : Pat<(i64 (MipsLo tglobaladdr:$in)), (DADDiu ZERO_64, tglobaladdr:$in)>;
166 defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
170 defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
171 defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
172 defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
173 defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
174 defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;