1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
19 def uimm5_64 : Operand<i64> {
20 let PrintMethod = "printUnsignedImm";
23 def uimm16_64 : Operand<i64> {
24 let PrintMethod = "printUnsignedImm";
28 def simm10_64 : Operand<i64>;
30 def imm64: Operand<i64>;
32 // Transformation Function - get Imm - 32.
33 def Subtract32 : SDNodeXForm<imm, [{
34 return getImm(N, (unsigned)N->getZExtValue() - 32);
37 // shamt must fit in 6 bits.
38 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
40 // Node immediate fits as 10-bit sign extended on target immediate.
42 def immSExt10_64 : PatLeaf<(i64 imm),
43 [{ return isInt<10>(N->getSExtValue()); }]>;
45 def immZExt16_64 : PatLeaf<(i64 imm),
46 [{ return isInt<16>(N->getZExtValue()); }]>;
48 def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>;
50 // Transformation function: get log2 of low 32 bits of immediate
51 def Log2LO : SDNodeXForm<imm, [{
52 return getImm(N, Log2_64((unsigned) N->getZExtValue()));
55 // Transformation function: get log2 of high 32 bits of immediate
56 def Log2HI : SDNodeXForm<imm, [{
57 return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32)));
60 // Predicate: True if immediate is a power of 2 and fits 32 bits
61 def PowerOf2LO : PatLeaf<(imm), [{
62 if (N->getValueType(0) == MVT::i64) {
63 uint64_t Imm = N->getZExtValue();
64 return isPowerOf2_64(Imm) && (Imm & 0xffffffff) == Imm;
70 // Predicate: True if immediate is a power of 2 and exceeds 32 bits
71 def PowerOf2HI : PatLeaf<(imm), [{
72 if (N->getValueType(0) == MVT::i64) {
73 uint64_t Imm = N->getZExtValue();
74 return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm;
80 //===----------------------------------------------------------------------===//
81 // Instructions specific format
82 //===----------------------------------------------------------------------===//
83 let usesCustomInserter = 1 in {
84 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
85 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
86 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
87 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
88 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
89 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
90 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
91 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
94 /// Pseudo instructions for loading and storing accumulator registers.
95 let isPseudo = 1, isCodeGenOnly = 1 in {
96 def LOAD_ACC128 : Load<"", ACC128>;
97 def STORE_ACC128 : Store<"", ACC128>;
100 //===----------------------------------------------------------------------===//
101 // Instruction definition
102 //===----------------------------------------------------------------------===//
103 let DecoderNamespace = "Mips64" in {
104 /// Arithmetic Instructions (ALU Immediate)
105 def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>,
106 ISA_MIPS3_NOT_32R6_64R6;
107 def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
109 ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
111 let isCodeGenOnly = 1 in {
112 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
114 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
116 def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
118 def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
120 def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
122 def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
125 /// Arithmetic Instructions (3-Operand, R-Type)
126 def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>,
128 def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, ADD_FM<0, 0x2d>,
130 def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
132 def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
135 let isCodeGenOnly = 1 in {
136 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
137 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
138 def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
139 def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
140 def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
141 def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
144 /// Shift Instructions
145 def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
146 SRA_FM<0x38, 0>, ISA_MIPS3;
147 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
148 SRA_FM<0x3a, 0>, ISA_MIPS3;
149 def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
150 SRA_FM<0x3b, 0>, ISA_MIPS3;
151 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
152 SRLV_FM<0x14, 0>, ISA_MIPS3;
153 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
154 SRLV_FM<0x16, 0>, ISA_MIPS3;
155 def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
156 SRLV_FM<0x17, 0>, ISA_MIPS3;
157 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
158 SRA_FM<0x3c, 0>, ISA_MIPS3;
159 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
160 SRA_FM<0x3e, 0>, ISA_MIPS3;
161 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
162 SRA_FM<0x3f, 0>, ISA_MIPS3;
164 // Rotate Instructions
165 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
167 SRA_FM<0x3a, 1>, ISA_MIPS64R2;
168 def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
169 SRLV_FM<0x16, 1>, ISA_MIPS64R2;
170 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
171 SRA_FM<0x3e, 1>, ISA_MIPS64R2;
173 /// Load and Store Instructions
175 let isCodeGenOnly = 1 in {
176 def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>;
177 def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>;
178 def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>;
179 def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
180 def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>;
181 def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>;
182 def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>;
183 def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>;
186 def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>, ISA_MIPS3;
187 def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>, ISA_MIPS3;
188 def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>, ISA_MIPS3;
190 /// load/store left/right
191 let isCodeGenOnly = 1 in {
192 def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>;
193 def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>;
194 def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>;
195 def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>;
198 def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>,
199 ISA_MIPS3_NOT_32R6_64R6;
200 def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>,
201 ISA_MIPS3_NOT_32R6_64R6;
202 def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>,
203 ISA_MIPS3_NOT_32R6_64R6;
204 def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>,
205 ISA_MIPS3_NOT_32R6_64R6;
207 /// Load-linked, Store-conditional
208 def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>, ISA_MIPS3_NOT_32R6_64R6;
209 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
211 /// Jump and Branch Instructions
212 let isCodeGenOnly = 1 in {
213 def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>;
214 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
215 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
216 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
217 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
218 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
219 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
220 def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
221 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
222 def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
225 def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>;
226 def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>;
228 /// Multiply and Divide Instructions.
229 def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
230 MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6;
231 def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
232 MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6;
233 def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
234 II_DMULT>, ISA_MIPS3_NOT_32R6_64R6;
235 def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
236 II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6;
237 def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
238 MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6;
239 def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
240 MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6;
241 def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
242 II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
243 def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
244 II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
246 let isCodeGenOnly = 1 in {
247 def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>,
248 ISA_MIPS3_NOT_32R6_64R6;
249 def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>,
250 ISA_MIPS3_NOT_32R6_64R6;
251 def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>,
252 ISA_MIPS3_NOT_32R6_64R6;
253 def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>,
254 ISA_MIPS3_NOT_32R6_64R6;
255 def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>,
256 ISA_MIPS3_NOT_32R6_64R6;
257 def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>,
258 ISA_MIPS3_NOT_32R6_64R6;
259 def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6;
261 /// Sign Ext In Register Instructions.
262 def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>,
264 def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
269 def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
270 def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
272 /// Double Word Swap Bytes/HalfWords
273 def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
274 def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2;
276 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
278 let isCodeGenOnly = 1 in
279 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
281 def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
282 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
283 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
285 def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
286 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>;
287 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
289 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
290 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
291 "dsll\t$rd, $rt, 32", [], II_DSLL>;
292 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
293 "sll\t$rd, $rt, 0", [], II_SLL>;
294 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
295 "sll\t$rd, $rt, 0", [], II_SLL>;
298 // We need the following pseudo instruction to avoid offset calculation for
299 // long branches. See the comment in file MipsLongBranch.cpp for detailed
302 // Expands to: daddiu $dst, $src, %PART($tgt - $baltgt)
303 // where %PART may be %hi or %lo, depending on the relocation kind
304 // that $tgt is annotated with.
305 def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),
306 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
308 // Cavium Octeon cmMIPS instructions
309 let EncodingPredicates = []<Predicate>, // FIXME: The lack of HasStdEnc is probably a bug
310 AdditionalPredicates = [HasCnMips] in {
312 class Count1s<string opstr, RegisterOperand RO>:
313 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
314 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
315 let TwoOperandAliasConstraint = "$rd = $rs";
318 class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
319 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
320 !strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
321 [(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))],
322 NoItinerary, FrmR, opstr> {
323 let TwoOperandAliasConstraint = "$rt = $rs";
326 class SetCC64_R<string opstr, PatFrag cond_op> :
327 InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
328 !strconcat(opstr, "\t$rd, $rs, $rt"),
329 [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs,
331 II_SEQ_SNE, FrmR, opstr> {
332 let TwoOperandAliasConstraint = "$rd = $rs";
335 class SetCC64_I<string opstr, PatFrag cond_op>:
336 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
337 !strconcat(opstr, "\t$rt, $rs, $imm10"),
338 [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs,
339 immSExt10_64:$imm10)))],
340 II_SEQI_SNEI, FrmI, opstr> {
341 let TwoOperandAliasConstraint = "$rt = $rs";
344 class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op,
345 RegisterOperand RO, bits<64> shift = 1> :
346 InstSE<(outs), (ins RO:$rs, uimm5_64:$p, opnd:$offset),
347 !strconcat(opstr, "\t$rs, $p, $offset"),
348 [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),
349 bb:$offset)], IIBranch, FrmI, opstr> {
351 let isTerminator = 1;
352 let hasDelaySlot = 1;
357 let Pattern = [(set GPR64Opnd:$rd,
358 (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in
359 def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
362 // Branch on Bit Clear /+32
363 def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd>, BBIT_FM<0x32>;
364 def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, 0x100000000>,
367 // Branch on Bit Set /+32
368 def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd>, BBIT_FM<0x3a>;
369 def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, 0x100000000>,
372 // Multiply Doubleword to GPR
373 let Defs = [HI0, LO0, P0, P1, P2] in
374 def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
377 // Extract a signed bit field /+32
378 def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>;
379 def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>;
381 // Clear and insert a bit field /+32
382 def CINS : ExtsCins<"cins">, EXTS_FM<0x32>;
383 def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>;
385 // Move to multiplier/product register
386 def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>;
387 def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>;
388 def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>;
389 def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>;
390 def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>;
391 def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>;
393 // Count Ones in a Word/Doubleword
394 def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>;
395 def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>;
397 // Set on equal/not equal
398 def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>;
399 def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>;
400 def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>;
401 def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>;
403 // 192-bit x 64-bit Unsigned Multiply and Add
404 let Defs = [P0, P1, P2] in
405 def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>,
408 // 64-bit Unsigned Multiply and Add Move
409 let Defs = [MPL0, P0, P1, P2] in
410 def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>,
413 // 64-bit Unsigned Multiply and Add
414 let Defs = [MPL1, MPL2, P0, P1, P2] in
415 def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>,
422 //===----------------------------------------------------------------------===//
423 // Arbitrary patterns that map to one or more instructions
424 //===----------------------------------------------------------------------===//
426 // Add/sub with carry
427 def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
428 (DSUBu GPR64:$lhs, GPR64:$rhs)>, ISA_MIPS3;
429 let AdditionalPredicates = [NotDSP] in {
430 def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
431 (DADDu GPR64:$lhs, GPR64:$rhs)>, ISA_MIPS3;
432 def : MipsPat<(addc GPR64:$src, immSExt16:$imm),
433 (DADDiu GPR64:$src, imm:$imm)>, ISA_MIPS3;
437 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
438 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
439 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
440 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
443 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
444 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
445 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
446 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
447 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
448 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
450 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
451 def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
452 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
453 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
454 def : MipsPat<(MipsLo tglobaltlsaddr:$in),
455 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
456 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
458 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
459 (DADDiu GPR64:$hi, tglobaladdr:$lo)>;
460 def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
461 (DADDiu GPR64:$hi, tblockaddress:$lo)>;
462 def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
463 (DADDiu GPR64:$hi, tjumptable:$lo)>;
464 def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
465 (DADDiu GPR64:$hi, tconstpool:$lo)>;
466 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
467 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
469 def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
470 def : WrapperPat<tconstpool, DADDiu, GPR64>;
471 def : WrapperPat<texternalsym, DADDiu, GPR64>;
472 def : WrapperPat<tblockaddress, DADDiu, GPR64>;
473 def : WrapperPat<tjumptable, DADDiu, GPR64>;
474 def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
476 defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
479 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
480 (BLEZ64 i64:$lhs, bb:$dst)>;
481 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
482 (BGEZ64 i64:$lhs, bb:$dst)>;
485 defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
486 defm : SetlePats<GPR64, SLT64, SLTu64>;
487 defm : SetgtPats<GPR64, SLT64, SLTu64>;
488 defm : SetgePats<GPR64, SLT64, SLTu64>;
489 defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
492 def : MipsPat<(trunc (assertsext GPR64:$src)),
493 (EXTRACT_SUBREG GPR64:$src, sub_32)>;
494 def : MipsPat<(trunc (assertzext GPR64:$src)),
495 (EXTRACT_SUBREG GPR64:$src, sub_32)>;
496 def : MipsPat<(i32 (trunc GPR64:$src)),
497 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
499 // 32-to-64-bit extension
500 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
501 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
502 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
504 // Sign extend in register
505 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
506 (SLL64_64 GPR64:$src)>;
509 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
511 // Octeon bbit0/bbit1 MipsPattern
512 let Predicates = [HasMips64, HasCnMips] in {
513 def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
514 (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>;
515 def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
516 (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;
517 def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
518 (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>;
519 def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
520 (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;
523 //===----------------------------------------------------------------------===//
524 // Instruction aliases
525 //===----------------------------------------------------------------------===//
526 def : MipsInstAlias<"move $dst, $src",
527 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
529 def : MipsInstAlias<"daddu $rs, $rt, $imm",
530 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
532 def : MipsInstAlias<"dadd $rs, $rt, $imm",
533 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
534 0>, ISA_MIPS3_NOT_32R6_64R6;
535 def : MipsInstAlias<"daddu $rs, $imm",
536 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
538 def : MipsInstAlias<"dadd $rs, $imm",
539 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
540 0>, ISA_MIPS3_NOT_32R6_64R6;
541 def : MipsInstAlias<"dsll $rd, $rt, $rs",
542 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
544 def : MipsInstAlias<"dsubu $rt, $rs, $imm",
545 (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
546 InvertedImOperand64:$imm), 0>, ISA_MIPS3;
547 def : MipsInstAlias<"dsubi $rs, $rt, $imm",
548 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
549 InvertedImOperand64:$imm),
550 0>, ISA_MIPS3_NOT_32R6_64R6;
551 def : MipsInstAlias<"dsubi $rs, $imm",
552 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
553 InvertedImOperand64:$imm),
554 0>, ISA_MIPS3_NOT_32R6_64R6;
555 def : MipsInstAlias<"dsub $rs, $rt, $imm",
556 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
557 InvertedImOperand64:$imm),
558 0>, ISA_MIPS3_NOT_32R6_64R6;
559 def : MipsInstAlias<"dsub $rs, $imm",
560 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
561 InvertedImOperand64:$imm),
562 0>, ISA_MIPS3_NOT_32R6_64R6;
563 def : MipsInstAlias<"dsubu $rs, $imm",
564 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs,
565 InvertedImOperand64:$imm),
567 def : MipsInstAlias<"dsra $rd, $rt, $rs",
568 (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
570 def : MipsInstAlias<"dsrl $rd, $rt, $rs",
571 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
574 class LoadImm64< string instr_asm, Operand Od, RegisterOperand RO> :
575 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64),
576 !strconcat(instr_asm, "\t$rt, $imm64")> ;
577 def LoadImm64Reg : LoadImm64<"dli", imm64, GPR64Opnd>;
579 /// Move between CPU and coprocessor registers
580 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
581 def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
582 def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
583 def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
584 def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
587 // Two operand (implicit 0 selector) versions:
588 def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
589 def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
590 def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
591 def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
593 let Predicates = [HasMips64, HasCnMips] in {
594 def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>;
595 def : MipsInstAlias<"syncs", (SYNC 0x6), 0>;
596 def : MipsInstAlias<"syncw", (SYNC 0x4), 0>;
597 def : MipsInstAlias<"syncws", (SYNC 0x5), 0>;