1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
18 // Instruction operand types
19 def shamt_64 : Operand<i64>;
22 def uimm16_64 : Operand<i64> {
23 let PrintMethod = "printUnsignedImm";
26 // Transformation Function - get Imm - 32.
27 def Subtract32 : SDNodeXForm<imm, [{
28 return getImm(N, (unsigned)N->getZExtValue() - 32);
31 // shamt must fit in 6 bits.
32 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
34 //===----------------------------------------------------------------------===//
35 // Instructions specific format
36 //===----------------------------------------------------------------------===//
38 // 64-bit shift instructions.
39 let DecoderNamespace = "Mips64" in {
40 class shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm,
42 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt6, shamt,
46 class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>:
47 Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
48 class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
49 Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
51 multiclass Atomic2Ops64<PatFrag Op, string Opstr> {
52 def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>,
53 Requires<[NotN64, HasStdEnc]>;
54 def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>,
55 Requires<[IsN64, HasStdEnc]> {
56 let isCodeGenOnly = 1;
60 multiclass AtomicCmpSwap64<PatFrag Op, string Width> {
61 def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>,
62 Requires<[NotN64, HasStdEnc]>;
63 def _P8 : AtomicCmpSwap<Op, Width, CPU64Regs, CPU64Regs>,
64 Requires<[IsN64, HasStdEnc]> {
65 let isCodeGenOnly = 1;
69 let usesCustomInserter = 1, Predicates = [HasStdEnc],
70 DecoderNamespace = "Mips64" in {
71 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">;
72 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">;
73 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64, "load_and_64">;
74 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64, "load_or_64">;
75 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64, "load_xor_64">;
76 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64, "load_nand_64">;
77 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64, "swap_64">;
78 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64, "64">;
81 //===----------------------------------------------------------------------===//
82 // Instruction definition
83 //===----------------------------------------------------------------------===//
84 let DecoderNamespace = "Mips64" in {
85 /// Arithmetic Instructions (ALU Immediate)
86 def DADDi : ArithLogicI<0x18, "daddi", simm16_64, immSExt16, CPU64Regs>;
87 def DADDiu : ArithLogicI<0x19, "daddiu", simm16_64, immSExt16, CPU64Regs,
88 add>, IsAsCheapAsAMove;
89 def DANDi : ArithLogicI<0x0c, "andi", uimm16_64, immZExt16, CPU64Regs, and>;
90 def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
91 def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
92 def ORi64 : ArithLogicI<0x0d, "ori", uimm16_64, immZExt16, CPU64Regs, or>;
93 def XORi64 : ArithLogicI<0x0e, "xori", uimm16_64, immZExt16, CPU64Regs, xor>;
94 def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>;
96 /// Arithmetic Instructions (3-Operand, R-Type)
97 def DADD : ArithLogicR<0x00, 0x2C, "dadd", IIAlu, CPU64Regs, 1>;
98 def DADDu : ArithLogicR<0x00, 0x2d, "daddu", IIAlu, CPU64Regs, 1, add>;
99 def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", IIAlu, CPU64Regs, 0, sub>;
100 def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
101 def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>;
102 def AND64 : ArithLogicR<0x00, 0x24, "and", IIAlu, CPU64Regs, 1, and>;
103 def OR64 : ArithLogicR<0x00, 0x25, "or", IIAlu, CPU64Regs, 1, or>;
104 def XOR64 : ArithLogicR<0x00, 0x26, "xor", IIAlu, CPU64Regs, 1, xor>;
105 def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>;
107 /// Shift Instructions
108 def DSLL : shift_rotate_imm64<0x38, 0x00, "dsll", shl>;
109 def DSRL : shift_rotate_imm64<0x3a, 0x00, "dsrl", srl>;
110 def DSRA : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>;
111 def DSLLV : shift_rotate_reg<0x14, 0x00, "dsllv", shl, CPU64Regs>;
112 def DSRLV : shift_rotate_reg<0x16, 0x00, "dsrlv", srl, CPU64Regs>;
113 def DSRAV : shift_rotate_reg<0x17, 0x00, "dsrav", sra, CPU64Regs>;
114 let Pattern = []<dag> in {
115 def DSLL32 : shift_rotate_imm64<0x3c, 0x00, "dsll32", shl>;
116 def DSRL32 : shift_rotate_imm64<0x3e, 0x00, "dsrl32", srl>;
117 def DSRA32 : shift_rotate_imm64<0x3f, 0x00, "dsra32", sra>;
120 // Rotate Instructions
121 let Predicates = [HasMips64r2, HasStdEnc],
122 DecoderNamespace = "Mips64" in {
123 def DROTR : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>;
124 def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>;
127 let DecoderNamespace = "Mips64" in {
128 /// Load and Store Instructions
130 defm LB64 : LoadM64<0x20, "lb", sextloadi8>;
131 defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>;
132 defm LH64 : LoadM64<0x21, "lh", sextloadi16>;
133 defm LHu64 : LoadM64<0x25, "lhu", zextloadi16>;
134 defm LW64 : LoadM64<0x23, "lw", sextloadi32>;
135 defm LWu64 : LoadM64<0x27, "lwu", zextloadi32>;
136 defm SB64 : StoreM64<0x28, "sb", truncstorei8>;
137 defm SH64 : StoreM64<0x29, "sh", truncstorei16>;
138 defm SW64 : StoreM64<0x2b, "sw", truncstorei32>;
139 defm LD : LoadM64<0x37, "ld", load>;
140 defm SD : StoreM64<0x3f, "sd", store>;
142 /// load/store left/right
143 let isCodeGenOnly = 1 in {
144 defm LWL64 : LoadLeftRightM64<0x22, "lwl", MipsLWL>;
145 defm LWR64 : LoadLeftRightM64<0x26, "lwr", MipsLWR>;
146 defm SWL64 : StoreLeftRightM64<0x2a, "swl", MipsSWL>;
147 defm SWR64 : StoreLeftRightM64<0x2e, "swr", MipsSWR>;
149 defm LDL : LoadLeftRightM64<0x1a, "ldl", MipsLDL>;
150 defm LDR : LoadLeftRightM64<0x1b, "ldr", MipsLDR>;
151 defm SDL : StoreLeftRightM64<0x2c, "sdl", MipsSDL>;
152 defm SDR : StoreLeftRightM64<0x2d, "sdr", MipsSDR>;
154 /// Load-linked, Store-conditional
155 def LLD : LLBase<0x34, "lld", CPU64Regs, mem>,
156 Requires<[NotN64, HasStdEnc]>;
157 def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>,
158 Requires<[IsN64, HasStdEnc]> {
159 let isCodeGenOnly = 1;
161 def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>,
162 Requires<[NotN64, HasStdEnc]>;
163 def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>,
164 Requires<[IsN64, HasStdEnc]> {
165 let isCodeGenOnly = 1;
168 /// Jump and Branch Instructions
169 def JR64 : IndirectBranch<CPU64Regs>;
170 def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>;
171 def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>;
172 def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>;
173 def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>;
174 def BLEZ64 : CBranchZero<0x06, 0, "blez", setle, CPU64Regs>;
175 def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>;
177 let DecoderNamespace = "Mips64" in
178 def JALR64 : JumpLinkReg<0x00, 0x09, "jalr", CPU64Regs>;
179 def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, IsTailCall;
181 let DecoderNamespace = "Mips64" in {
182 /// Multiply and Divide Instructions.
183 def DMULT : Mult64<0x1c, "dmult", IIImul>;
184 def DMULTu : Mult64<0x1d, "dmultu", IIImul>;
185 def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
186 def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>;
188 def MTHI64 : MoveToLOHI<0x11, "mthi", CPU64Regs, [HI64]>;
189 def MTLO64 : MoveToLOHI<0x13, "mtlo", CPU64Regs, [LO64]>;
190 def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>;
191 def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>;
193 /// Sign Ext In Register Instructions.
194 def SEB64 : SignExtInReg<0x10, "seb", i8, CPU64Regs>;
195 def SEH64 : SignExtInReg<0x18, "seh", i16, CPU64Regs>;
198 def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>;
199 def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>;
201 /// Double Word Swap Bytes/HalfWords
202 def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>;
203 def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>;
205 def LEA_ADDiu64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>;
207 let DecoderNamespace = "Mips64" in {
208 def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>;
210 def DEXT : ExtBase<3, "dext", CPU64Regs>;
211 let Pattern = []<dag> in {
212 def DEXTU : ExtBase<2, "dextu", CPU64Regs>;
213 def DEXTM : ExtBase<1, "dextm", CPU64Regs>;
215 def DINS : InsBase<7, "dins", CPU64Regs>;
216 let Pattern = []<dag> in {
217 def DINSU : InsBase<6, "dinsu", CPU64Regs>;
218 def DINSM : InsBase<5, "dinsm", CPU64Regs>;
221 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
222 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
223 "dsll\t$rd, $rt, 32", [], IIAlu>;
224 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
225 "sll\t$rd, $rt, 0", [], IIAlu>;
226 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
227 "sll\t$rd, $rt, 0", [], IIAlu>;
230 //===----------------------------------------------------------------------===//
231 // Arbitrary patterns that map to one or more instructions
232 //===----------------------------------------------------------------------===//
235 let Predicates = [NotN64, HasStdEnc] in {
236 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
237 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
238 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
239 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
241 let Predicates = [IsN64, HasStdEnc] in {
242 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>;
243 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>;
244 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>;
245 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>;
249 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
250 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
251 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
252 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
253 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
254 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
256 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
257 def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
258 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
259 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
260 def : MipsPat<(MipsLo tglobaltlsaddr:$in),
261 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
262 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
264 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
265 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
266 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)),
267 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>;
268 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)),
269 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
270 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
271 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
272 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)),
273 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>;
275 def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>;
276 def : WrapperPat<tconstpool, DADDiu, CPU64Regs>;
277 def : WrapperPat<texternalsym, DADDiu, CPU64Regs>;
278 def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>;
279 def : WrapperPat<tjumptable, DADDiu, CPU64Regs>;
280 def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>;
282 defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
286 defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
287 defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
288 defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
289 defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
290 defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
293 def : MipsPat<(i32 (trunc CPU64Regs:$src)),
294 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>,
295 Requires<[IsN64, HasStdEnc]>;
297 // 32-to-64-bit extension
298 def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
299 def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;
300 def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
302 // Sign extend in register
303 def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)),
304 (SLL64_64 CPU64Regs:$src)>;
307 def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
309 //===----------------------------------------------------------------------===//
310 // Instruction aliases
311 //===----------------------------------------------------------------------===//
312 def : InstAlias<"move $dst,$src", (DADD CPU64Regs:$dst,CPU64Regs:$src,ZERO_64)>;
314 /// Move between CPU and coprocessor registers
315 let DecoderNamespace = "Mips64" in {
316 def MFC0_3OP64 : MFC3OP<0x10, 0, (outs CPU64Regs:$rt),
317 (ins CPU64Regs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">;
318 def MTC0_3OP64 : MFC3OP<0x10, 4, (outs CPU64Regs:$rd, uimm16:$sel),
319 (ins CPU64Regs:$rt),"mtc0\t$rt, $rd, $sel">;
320 def MFC2_3OP64 : MFC3OP<0x12, 0, (outs CPU64Regs:$rt),
321 (ins CPU64Regs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">;
322 def MTC2_3OP64 : MFC3OP<0x12, 4, (outs CPU64Regs:$rd, uimm16:$sel),
323 (ins CPU64Regs:$rt),"mtc2\t$rt, $rd, $sel">;
324 def DMFC0_3OP64 : MFC3OP<0x10, 1, (outs CPU64Regs:$rt),
325 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc0\t$rt, $rd, $sel">;
326 def DMTC0_3OP64 : MFC3OP<0x10, 5, (outs CPU64Regs:$rd, uimm16:$sel),
327 (ins CPU64Regs:$rt),"dmtc0\t$rt, $rd, $sel">;
328 def DMFC2_3OP64 : MFC3OP<0x12, 1, (outs CPU64Regs:$rt),
329 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc2\t$rt, $rd, $sel">;
330 def DMTC2_3OP64 : MFC3OP<0x12, 5, (outs CPU64Regs:$rd, uimm16:$sel),
331 (ins CPU64Regs:$rt),"dmtc2\t$rt, $rd, $sel">;
333 // Two operand (implicit 0 selector) versions:
334 def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
335 def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
336 def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
337 def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
338 def : InstAlias<"dmfc0 $rt, $rd", (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
339 def : InstAlias<"dmtc0 $rt, $rd", (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
340 def : InstAlias<"dmfc2 $rt, $rd", (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
341 def : InstAlias<"dmtc2 $rt, $rd", (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;