1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
18 // Instruction operand types
19 def shamt_64 : Operand<i64>;
22 def uimm16_64 : Operand<i64> {
23 let PrintMethod = "printUnsignedImm";
26 // Transformation Function - get Imm - 32.
27 def Subtract32 : SDNodeXForm<imm, [{
28 return getImm(N, (unsigned)N->getZExtValue() - 32);
31 // shamt must fit in 6 bits.
32 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
34 //===----------------------------------------------------------------------===//
35 // Instructions specific format
36 //===----------------------------------------------------------------------===//
38 // 64-bit shift instructions.
39 let DecoderNamespace = "Mips64" in {
40 class shift_rotate_imm64<string opstr, SDPatternOperator OpNode = null_frag>:
41 shift_rotate_imm<opstr, immZExt6, shamt, CPU64Regs, OpNode>;
43 multiclass Atomic2Ops64<PatFrag Op> {
44 def #NAME# : Atomic2Ops<Op, CPU64Regs, CPURegs>,
45 Requires<[NotN64, HasStdEnc]>;
46 def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>,
47 Requires<[IsN64, HasStdEnc]> {
48 let isCodeGenOnly = 1;
52 multiclass AtomicCmpSwap64<PatFrag Op> {
53 def #NAME# : AtomicCmpSwap<Op, CPU64Regs, CPURegs>,
54 Requires<[NotN64, HasStdEnc]>;
55 def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>,
56 Requires<[IsN64, HasStdEnc]> {
57 let isCodeGenOnly = 1;
61 let usesCustomInserter = 1, Predicates = [HasStdEnc],
62 DecoderNamespace = "Mips64" in {
63 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>;
64 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>;
65 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>;
66 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>;
67 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>;
68 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>;
69 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>;
70 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>;
73 //===----------------------------------------------------------------------===//
74 // Instruction definition
75 //===----------------------------------------------------------------------===//
76 let DecoderNamespace = "Mips64" in {
77 /// Arithmetic Instructions (ALU Immediate)
78 def DADDi : ArithLogicI<"daddi", simm16_64, CPU64Regs>, ADDI_FM<0x18>;
79 def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64Regs, immSExt16, add>,
80 ADDI_FM<0x19>, IsAsCheapAsAMove;
81 def DANDi : ArithLogicI<"andi", uimm16_64, CPU64Regs, immZExt16, and>,
83 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>,
85 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>,
87 def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64Regs, immZExt16, or>,
89 def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64Regs, immZExt16, xor>,
91 def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM;
93 /// Arithmetic Instructions (3-Operand, R-Type)
94 def DADD : ArithLogicR<"dadd", CPU64Regs>, ADD_FM<0, 0x2c>;
95 def DADDu : ArithLogicR<"daddu", CPU64Regs, 1, IIAlu, add>, ADD_FM<0, 0x2d>;
96 def DSUBu : ArithLogicR<"dsubu", CPU64Regs, 0, IIAlu, sub>, ADD_FM<0, 0x2f>;
97 def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>;
98 def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>;
99 def AND64 : ArithLogicR<"and", CPU64Regs, 1, IIAlu, and>, ADD_FM<0, 0x24>;
100 def OR64 : ArithLogicR<"or", CPU64Regs, 1, IIAlu, or>, ADD_FM<0, 0x25>;
101 def XOR64 : ArithLogicR<"xor", CPU64Regs, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
102 def NOR64 : LogicNOR<"nor", CPU64Regs>, ADD_FM<0, 0x27>;
104 /// Shift Instructions
105 def DSLL : shift_rotate_imm64<"dsll", shl>, SRA_FM<0x38, 0>;
106 def DSRL : shift_rotate_imm64<"dsrl", srl>, SRA_FM<0x3a, 0>;
107 def DSRA : shift_rotate_imm64<"dsra", sra>, SRA_FM<0x3b, 0>;
108 def DSLLV : shift_rotate_reg<"dsllv", shl, CPU64Regs>, SRLV_FM<0x14, 0>;
109 def DSRLV : shift_rotate_reg<"dsrlv", srl, CPU64Regs>, SRLV_FM<0x16, 0>;
110 def DSRAV : shift_rotate_reg<"dsrav", sra, CPU64Regs>, SRLV_FM<0x17, 0>;
111 def DSLL32 : shift_rotate_imm64<"dsll32">, SRA_FM<0x3c, 0>;
112 def DSRL32 : shift_rotate_imm64<"dsrl32">, SRA_FM<0x3e, 0>;
113 def DSRA32 : shift_rotate_imm64<"dsra32">, SRA_FM<0x3f, 0>;
115 // Rotate Instructions
116 let Predicates = [HasMips64r2, HasStdEnc],
117 DecoderNamespace = "Mips64" in {
118 def DROTR : shift_rotate_imm64<"drotr", rotr>, SRA_FM<0x3a, 1>;
119 def DROTRV : shift_rotate_reg<"drotrv", rotr, CPU64Regs>, SRLV_FM<0x16, 1>;
122 let DecoderNamespace = "Mips64" in {
123 /// Load and Store Instructions
125 defm LB64 : LoadM<"lb", sextloadi8, CPU64Regs>, LW_FM<0x20>;
126 defm LBu64 : LoadM<"lbu", zextloadi8, CPU64Regs>, LW_FM<0x24>;
127 defm LH64 : LoadM<"lh", sextloadi16, CPU64Regs>, LW_FM<0x21>;
128 defm LHu64 : LoadM<"lhu", zextloadi16, CPU64Regs>, LW_FM<0x25>;
129 defm LW64 : LoadM<"lw", sextloadi32, CPU64Regs>, LW_FM<0x23>;
130 defm LWu64 : LoadM<"lwu", zextloadi32, CPU64Regs>, LW_FM<0x27>;
131 defm SB64 : StoreM<"sb", truncstorei8, CPU64Regs>, LW_FM<0x28>;
132 defm SH64 : StoreM<"sh", truncstorei16, CPU64Regs>, LW_FM<0x29>;
133 defm SW64 : StoreM<"sw", truncstorei32, CPU64Regs>, LW_FM<0x2b>;
134 defm LD : LoadM<"ld", load, CPU64Regs>, LW_FM<0x37>;
135 defm SD : StoreM<"sd", store, CPU64Regs>, LW_FM<0x3f>;
137 /// load/store left/right
138 let isCodeGenOnly = 1 in {
139 defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>;
140 defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>;
141 defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>;
142 defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>;
144 defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>;
145 defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>;
146 defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>;
147 defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>;
149 /// Load-linked, Store-conditional
150 let Predicates = [NotN64, HasStdEnc] in {
151 def LLD : LLBase<"lld", CPU64Regs, mem>, LW_FM<0x34>;
152 def SCD : SCBase<"scd", CPU64Regs, mem>, LW_FM<0x3c>;
155 let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in {
156 def LLD_P8 : LLBase<"lld", CPU64Regs, mem64>, LW_FM<0x34>;
157 def SCD_P8 : SCBase<"scd", CPU64Regs, mem64>, LW_FM<0x3c>;
160 /// Jump and Branch Instructions
161 def JR64 : IndirectBranch<CPU64Regs>, MTLO_FM<8>;
162 def BEQ64 : CBranch<"beq", seteq, CPU64Regs>, BEQ_FM<4>;
163 def BNE64 : CBranch<"bne", setne, CPU64Regs>, BEQ_FM<5>;
164 def BGEZ64 : CBranchZero<"bgez", setge, CPU64Regs>, BGEZ_FM<1, 1>;
165 def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64Regs>, BGEZ_FM<7, 0>;
166 def BLEZ64 : CBranchZero<"blez", setle, CPU64Regs>, BGEZ_FM<6, 0>;
167 def BLTZ64 : CBranchZero<"bltz", setlt, CPU64Regs>, BGEZ_FM<1, 0>;
169 let DecoderNamespace = "Mips64" in
170 def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM;
171 def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
173 let DecoderNamespace = "Mips64" in {
174 /// Multiply and Divide Instructions.
175 def DMULT : Mult<"dmult", IIImul, CPU64Regs, [HI64, LO64]>, MULT_FM<0, 0x1c>;
176 def DMULTu : Mult<"dmultu", IIImul, CPU64Regs, [HI64, LO64]>, MULT_FM<0, 0x1d>;
177 def DSDIV : Div<MipsDivRem, "ddiv", IIIdiv, CPU64Regs, [HI64, LO64]>,
179 def DUDIV : Div<MipsDivRemU, "ddivu", IIIdiv, CPU64Regs, [HI64, LO64]>,
182 def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>;
183 def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>;
184 def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>;
185 def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>;
187 /// Sign Ext In Register Instructions.
188 def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10>;
189 def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18>;
192 def DCLZ : CountLeading0<"dclz", CPU64Regs>, CLO_FM<0x24>;
193 def DCLO : CountLeading1<"dclo", CPU64Regs>, CLO_FM<0x25>;
195 /// Double Word Swap Bytes/HalfWords
196 def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>;
197 def DSHD : SubwordSwap<0x24, 0x5, "dshd", CPU64Regs>;
199 def LEA_ADDiu64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>;
201 let DecoderNamespace = "Mips64" in {
202 def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>;
204 def DEXT : ExtBase<3, "dext", CPU64Regs>;
205 let Pattern = []<dag> in {
206 def DEXTU : ExtBase<2, "dextu", CPU64Regs>;
207 def DEXTM : ExtBase<1, "dextm", CPU64Regs>;
209 def DINS : InsBase<7, "dins", CPU64Regs>;
210 let Pattern = []<dag> in {
211 def DINSU : InsBase<6, "dinsu", CPU64Regs>;
212 def DINSM : InsBase<5, "dinsm", CPU64Regs>;
215 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
216 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
217 "dsll\t$rd, $rt, 32", [], IIAlu>;
218 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
219 "sll\t$rd, $rt, 0", [], IIAlu>;
220 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
221 "sll\t$rd, $rt, 0", [], IIAlu>;
224 //===----------------------------------------------------------------------===//
225 // Arbitrary patterns that map to one or more instructions
226 //===----------------------------------------------------------------------===//
229 let Predicates = [NotN64, HasStdEnc] in {
230 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
231 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
232 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
233 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
235 let Predicates = [IsN64, HasStdEnc] in {
236 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>;
237 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>;
238 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>;
239 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>;
243 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
244 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
245 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
246 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
247 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
248 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
250 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
251 def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
252 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
253 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
254 def : MipsPat<(MipsLo tglobaltlsaddr:$in),
255 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
256 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
258 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
259 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
260 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)),
261 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>;
262 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)),
263 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
264 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
265 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
266 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)),
267 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>;
269 def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>;
270 def : WrapperPat<tconstpool, DADDiu, CPU64Regs>;
271 def : WrapperPat<texternalsym, DADDiu, CPU64Regs>;
272 def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>;
273 def : WrapperPat<tjumptable, DADDiu, CPU64Regs>;
274 def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>;
276 defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
280 defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
281 defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
282 defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
283 defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
284 defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
287 def : MipsPat<(i32 (trunc CPU64Regs:$src)),
288 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>,
289 Requires<[IsN64, HasStdEnc]>;
291 // 32-to-64-bit extension
292 def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
293 def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;
294 def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
296 // Sign extend in register
297 def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)),
298 (SLL64_64 CPU64Regs:$src)>;
301 def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
303 //===----------------------------------------------------------------------===//
304 // Instruction aliases
305 //===----------------------------------------------------------------------===//
306 def : InstAlias<"move $dst,$src", (DADD CPU64Regs:$dst,CPU64Regs:$src,ZERO_64)>;
308 /// Move between CPU and coprocessor registers
309 let DecoderNamespace = "Mips64" in {
310 def MFC0_3OP64 : MFC3OP<0x10, 0, (outs CPU64Regs:$rt),
311 (ins CPU64Regs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">;
312 def MTC0_3OP64 : MFC3OP<0x10, 4, (outs CPU64Regs:$rd, uimm16:$sel),
313 (ins CPU64Regs:$rt),"mtc0\t$rt, $rd, $sel">;
314 def MFC2_3OP64 : MFC3OP<0x12, 0, (outs CPU64Regs:$rt),
315 (ins CPU64Regs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">;
316 def MTC2_3OP64 : MFC3OP<0x12, 4, (outs CPU64Regs:$rd, uimm16:$sel),
317 (ins CPU64Regs:$rt),"mtc2\t$rt, $rd, $sel">;
318 def DMFC0_3OP64 : MFC3OP<0x10, 1, (outs CPU64Regs:$rt),
319 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc0\t$rt, $rd, $sel">;
320 def DMTC0_3OP64 : MFC3OP<0x10, 5, (outs CPU64Regs:$rd, uimm16:$sel),
321 (ins CPU64Regs:$rt),"dmtc0\t$rt, $rd, $sel">;
322 def DMFC2_3OP64 : MFC3OP<0x12, 1, (outs CPU64Regs:$rt),
323 (ins CPU64Regs:$rd, uimm16:$sel),"dmfc2\t$rt, $rd, $sel">;
324 def DMTC2_3OP64 : MFC3OP<0x12, 5, (outs CPU64Regs:$rd, uimm16:$sel),
325 (ins CPU64Regs:$rt),"dmtc2\t$rt, $rd, $sel">;
327 // Two operand (implicit 0 selector) versions:
328 def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
329 def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
330 def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
331 def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
332 def : InstAlias<"dmfc0 $rt, $rd", (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
333 def : InstAlias<"dmtc0 $rt, $rd", (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
334 def : InstAlias<"dmfc2 $rt, $rd", (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
335 def : InstAlias<"dmtc2 $rt, $rd", (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;