1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
19 def uimm16_64 : Operand<i64> {
20 let PrintMethod = "printUnsignedImm";
24 def simm10_64 : Operand<i64>;
26 // Transformation Function - get Imm - 32.
27 def Subtract32 : SDNodeXForm<imm, [{
28 return getImm(N, (unsigned)N->getZExtValue() - 32);
31 // shamt must fit in 6 bits.
32 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
34 // Node immediate fits as 10-bit sign extended on target immediate.
36 def immSExt10_64 : PatLeaf<(i64 imm),
37 [{ return isInt<10>(N->getSExtValue()); }]>;
39 //===----------------------------------------------------------------------===//
40 // Instructions specific format
41 //===----------------------------------------------------------------------===//
42 let usesCustomInserter = 1 in {
43 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
44 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
45 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
46 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
47 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
48 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
49 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
50 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
53 /// Pseudo instructions for loading and storing accumulator registers.
54 let isPseudo = 1, isCodeGenOnly = 1 in {
55 def LOAD_ACC128 : Load<"", ACC128>;
56 def STORE_ACC128 : Store<"", ACC128>;
59 //===----------------------------------------------------------------------===//
60 // Instruction definition
61 //===----------------------------------------------------------------------===//
62 let DecoderNamespace = "Mips64" in {
63 /// Arithmetic Instructions (ALU Immediate)
64 def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>;
65 def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
67 ADDI_FM<0x19>, IsAsCheapAsAMove;
69 let isCodeGenOnly = 1 in {
70 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
72 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
74 def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
76 def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
78 def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
80 def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
83 /// Arithmetic Instructions (3-Operand, R-Type)
84 def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>;
85 def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
87 def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>,
89 def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>;
91 let isCodeGenOnly = 1 in {
92 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
93 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
94 def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
95 def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
96 def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
97 def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
100 /// Shift Instructions
101 def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
103 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
105 def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
107 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
109 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
111 def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
113 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
115 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
117 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
120 // Rotate Instructions
121 let Predicates = [HasStdEnc, HasMips64r2] in {
122 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
123 immZExt6>, SRA_FM<0x3a, 1>;
124 def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
126 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
130 /// Load and Store Instructions
132 let isCodeGenOnly = 1 in {
133 def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>;
134 def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>;
135 def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>;
136 def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
137 def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>;
138 def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>;
139 def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>;
140 def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>;
143 def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>;
144 def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>;
145 def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>;
147 /// load/store left/right
148 let isCodeGenOnly = 1 in {
149 def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>;
150 def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>;
151 def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>;
152 def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>;
155 def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>;
156 def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>;
157 def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>;
158 def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>;
160 /// Load-linked, Store-conditional
161 def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>;
162 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>;
164 /// Jump and Branch Instructions
165 let isCodeGenOnly = 1 in {
166 def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>;
167 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
168 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
169 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
170 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
171 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
172 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
173 def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
174 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
175 def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
178 /// Multiply and Divide Instructions.
179 def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
181 def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
183 def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
185 def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
187 def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
189 def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
191 def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
193 def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
196 let isCodeGenOnly = 1 in {
197 def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>;
198 def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>;
199 def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>;
200 def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>;
201 def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>;
202 def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>;
203 def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>;
205 /// Sign Ext In Register Instructions.
206 def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
207 def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
211 def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>;
212 def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>;
214 /// Double Word Swap Bytes/HalfWords
215 def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>;
216 def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>;
218 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
220 let isCodeGenOnly = 1 in
221 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
223 def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
224 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
225 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
227 def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
228 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>;
229 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
231 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
232 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
233 "dsll\t$rd, $rt, 32", [], II_DSLL>;
234 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
235 "sll\t$rd, $rt, 0", [], II_SLL>;
236 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
237 "sll\t$rd, $rt, 0", [], II_SLL>;
240 // We need the following two pseudo instructions to avoid offset calculation for
241 // long branches. See the comment in file MipsLongBranch.cpp for detailed
244 // Expands to: lui $dst, %highest($tgt - $baltgt)
245 def LONG_BRANCH_LUi64 : PseudoSE<(outs GPR64Opnd:$dst),
246 (ins brtarget:$tgt, brtarget:$baltgt), []>;
248 // Expands to: daddiu $dst, $src, %PART($tgt - $baltgt)
249 // where %PART may be %higher, %hi or %lo, depending on the relocation kind
250 // that $tgt is annotated with.
251 def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),
252 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
254 // Cavium Octeon cmMIPS instructions
255 let Predicates = [HasCnMips] in {
257 class Count1s<string opstr, RegisterOperand RO>:
258 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
259 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
260 let TwoOperandAliasConstraint = "$rd = $rs";
263 class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
264 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
265 !strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
266 [(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))],
267 NoItinerary, FrmR, opstr> {
268 let TwoOperandAliasConstraint = "$rt = $rs";
271 class SetCC64_R<string opstr, PatFrag cond_op> :
272 InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
273 !strconcat(opstr, "\t$rd, $rs, $rt"),
274 [(set GPR64Opnd:$rd, (cond_op GPR64Opnd:$rs, GPR64Opnd:$rt))],
275 II_SEQ_SNE, FrmR, opstr> {
276 let TwoOperandAliasConstraint = "$rd = $rs";
279 class SetCC64_I<string opstr, PatFrag cond_op>:
280 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
281 !strconcat(opstr, "\t$rt, $rs, $imm10"),
282 [(set GPR64Opnd:$rt, (cond_op GPR64Opnd:$rs, immSExt10_64:$imm10))],
283 II_SEQI_SNEI, FrmI, opstr> {
284 let TwoOperandAliasConstraint = "$rt = $rs";
288 let Pattern = [(set GPR64Opnd:$rd,
289 (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in
290 def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
293 // Multiply Doubleword to GPR
294 let Defs = [HI0, LO0, P0, P1, P2] in
295 def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
298 // Extract a signed bit field /+32
299 def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>;
300 def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>;
302 // Clear and insert a bit field /+32
303 def CINS : ExtsCins<"cins">, EXTS_FM<0x32>;
304 def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>;
306 // Move to multiplier/product register
307 def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>;
308 def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>;
309 def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>;
310 def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>;
311 def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>;
312 def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>;
314 // Count Ones in a Word/Doubleword
315 def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>;
316 def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>;
318 // Set on equal/not equal
319 def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>;
320 def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>;
321 def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>;
322 def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>;
324 // 192-bit x 64-bit Unsigned Multiply and Add
325 let Defs = [P0, P1, P2] in
326 def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>,
329 // 64-bit Unsigned Multiply and Add Move
330 let Defs = [MPL0, P0, P1, P2] in
331 def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>,
334 // 64-bit Unsigned Multiply and Add
335 let Defs = [MPL1, MPL2, P0, P1, P2] in
336 def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>,
343 //===----------------------------------------------------------------------===//
344 // Arbitrary patterns that map to one or more instructions
345 //===----------------------------------------------------------------------===//
348 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
349 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
350 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
351 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
354 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
355 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
356 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
357 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
358 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
359 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
361 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
362 def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
363 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
364 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
365 def : MipsPat<(MipsLo tglobaltlsaddr:$in),
366 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
367 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
369 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
370 (DADDiu GPR64:$hi, tglobaladdr:$lo)>;
371 def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
372 (DADDiu GPR64:$hi, tblockaddress:$lo)>;
373 def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
374 (DADDiu GPR64:$hi, tjumptable:$lo)>;
375 def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
376 (DADDiu GPR64:$hi, tconstpool:$lo)>;
377 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
378 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
380 def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
381 def : WrapperPat<tconstpool, DADDiu, GPR64>;
382 def : WrapperPat<texternalsym, DADDiu, GPR64>;
383 def : WrapperPat<tblockaddress, DADDiu, GPR64>;
384 def : WrapperPat<tjumptable, DADDiu, GPR64>;
385 def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
387 defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
390 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
391 (BLEZ64 i64:$lhs, bb:$dst)>;
392 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
393 (BGEZ64 i64:$lhs, bb:$dst)>;
396 defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
397 defm : SetlePats<GPR64, SLT64, SLTu64>;
398 defm : SetgtPats<GPR64, SLT64, SLTu64>;
399 defm : SetgePats<GPR64, SLT64, SLTu64>;
400 defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
403 def : MipsPat<(i32 (trunc GPR64:$src)),
404 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>,
405 Requires<[HasStdEnc]>;
407 // 32-to-64-bit extension
408 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
409 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
410 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
412 // Sign extend in register
413 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
414 (SLL64_64 GPR64:$src)>;
417 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
419 //===----------------------------------------------------------------------===//
420 // Instruction aliases
421 //===----------------------------------------------------------------------===//
422 def : InstAlias<"move $dst, $src",
423 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
425 def : InstAlias<"daddu $rs, $rt, $imm",
426 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
428 def : InstAlias<"dadd $rs, $rt, $imm",
429 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
431 def : InstAlias<"daddu $rs, $imm",
432 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
434 def : InstAlias<"dadd $rs, $imm",
435 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
437 def : InstAlias<"add $rs, $imm",
438 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
440 def : InstAlias<"addu $rs, $imm",
441 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
443 def : InstAlias<"dsll $rd, $rt, $rs",
444 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>;
445 def : InstAlias<"dsubu $rt, $rs, $imm",
446 (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
447 InvertedImOperand64: $imm),0>;
448 def : InstAlias<"dsub $rs, $imm",
449 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, InvertedImOperand64:$imm),
451 def : InstAlias<"dsubu $rs, $imm",
452 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, InvertedImOperand64:$imm),
454 def : InstAlias<"dsrl $rd, $rt, $rs",
455 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>;
457 /// Move between CPU and coprocessor registers
458 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
459 def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
460 def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>;
461 def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>;
462 def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>;
465 // Two operand (implicit 0 selector) versions:
466 def : InstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
467 def : InstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
468 def : InstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
469 def : InstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;