1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
19 def uimm16_64 : Operand<i64> {
20 let PrintMethod = "printUnsignedImm";
23 // Transformation Function - get Imm - 32.
24 def Subtract32 : SDNodeXForm<imm, [{
25 return getImm(N, (unsigned)N->getZExtValue() - 32);
28 // shamt must fit in 6 bits.
29 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
31 //===----------------------------------------------------------------------===//
32 // Instructions specific format
33 //===----------------------------------------------------------------------===//
34 let usesCustomInserter = 1 in {
35 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
36 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
37 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
38 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
39 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
40 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
41 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
42 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
45 /// Pseudo instructions for loading and storing accumulator registers.
46 let isPseudo = 1, isCodeGenOnly = 1 in {
47 def LOAD_ACC128 : Load<"", ACC128>;
48 def STORE_ACC128 : Store<"", ACC128>;
51 //===----------------------------------------------------------------------===//
52 // Instruction definition
53 //===----------------------------------------------------------------------===//
54 let DecoderNamespace = "Mips64" in {
55 /// Arithmetic Instructions (ALU Immediate)
56 def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>;
57 def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
59 ADDI_FM<0x19>, IsAsCheapAsAMove;
61 let isCodeGenOnly = 1 in {
62 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
64 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
66 def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
68 def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
70 def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
72 def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
75 /// Arithmetic Instructions (3-Operand, R-Type)
76 def DADD : ArithLogicR<"dadd", GPR64Opnd>, ADD_FM<0, 0x2c>;
77 def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
79 def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>,
82 let isCodeGenOnly = 1 in {
83 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
84 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
85 def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
86 def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
87 def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
88 def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
91 /// Shift Instructions
92 def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
94 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
96 def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
98 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
100 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
102 def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
104 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
106 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
108 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
111 // Rotate Instructions
112 let Predicates = [HasMips64r2, HasStdEnc] in {
113 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
114 immZExt6>, SRA_FM<0x3a, 1>;
115 def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
117 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
121 /// Load and Store Instructions
123 let isCodeGenOnly = 1 in {
124 def LB64 : Load<"lb", GPR64Opnd, sextloadi8, IILoad>, LW_FM<0x20>;
125 def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, IILoad>, LW_FM<0x24>;
126 def LH64 : Load<"lh", GPR64Opnd, sextloadi16, IILoad>, LW_FM<0x21>;
127 def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, IILoad>, LW_FM<0x25>;
128 def LW64 : Load<"lw", GPR64Opnd, sextloadi32, IILoad>, LW_FM<0x23>;
129 def SB64 : Store<"sb", GPR64Opnd, truncstorei8, IIStore>, LW_FM<0x28>;
130 def SH64 : Store<"sh", GPR64Opnd, truncstorei16, IIStore>, LW_FM<0x29>;
131 def SW64 : Store<"sw", GPR64Opnd, truncstorei32, IIStore>, LW_FM<0x2b>;
134 def LWu : Load<"lwu", GPR64Opnd, zextloadi32, IILoad>, LW_FM<0x27>;
135 def LD : Load<"ld", GPR64Opnd, load, IILoad>, LW_FM<0x37>;
136 def SD : Store<"sd", GPR64Opnd, store, IIStore>, LW_FM<0x3f>;
138 /// load/store left/right
139 let isCodeGenOnly = 1 in {
140 def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, IILoad>, LW_FM<0x22>;
141 def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, IILoad>, LW_FM<0x26>;
142 def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, IIStore>, LW_FM<0x2a>;
143 def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, IIStore>, LW_FM<0x2e>;
146 def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, IILoad>, LW_FM<0x1a>;
147 def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, IILoad>, LW_FM<0x1b>;
148 def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, IIStore>, LW_FM<0x2c>;
149 def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, IIStore>, LW_FM<0x2d>;
151 /// Load-linked, Store-conditional
152 def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>;
153 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>;
155 /// Jump and Branch Instructions
156 let isCodeGenOnly = 1 in {
157 def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>;
158 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
159 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
160 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
161 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
162 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
163 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
164 def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
165 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
166 def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
169 /// Multiply and Divide Instructions.
170 def DMULT : Mult<"dmult", IIImult, GPR64Opnd, [HI0_64, LO0_64]>,
172 def DMULTu : Mult<"dmultu", IIImult, GPR64Opnd, [HI0_64, LO0_64]>,
174 def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
176 def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
178 def DSDIV : Div<"ddiv", IIIdiv, GPR64Opnd, [HI0_64, LO0_64]>, MULT_FM<0, 0x1e>;
179 def DUDIV : Div<"ddivu", IIIdiv, GPR64Opnd, [HI0_64, LO0_64]>, MULT_FM<0, 0x1f>;
180 def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
182 def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
185 let isCodeGenOnly = 1 in {
186 def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>;
187 def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>;
188 def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>;
189 def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>;
190 def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>;
191 def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>;
192 def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>;
194 /// Sign Ext In Register Instructions.
195 def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
196 def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
200 def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>;
201 def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>;
203 /// Double Word Swap Bytes/HalfWords
204 def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>;
205 def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>;
207 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
209 let isCodeGenOnly = 1 in
210 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
212 def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
213 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
214 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
216 def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
217 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>;
218 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
220 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
221 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
222 "dsll\t$rd, $rt, 32", [], II_DSLL>;
223 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
224 "sll\t$rd, $rt, 0", [], II_SLL>;
225 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
226 "sll\t$rd, $rt, 0", [], II_SLL>;
229 //===----------------------------------------------------------------------===//
230 // Arbitrary patterns that map to one or more instructions
231 //===----------------------------------------------------------------------===//
234 let Predicates = [HasStdEnc] in {
235 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
236 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
237 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
238 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
242 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
243 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
244 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
245 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
246 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
247 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
249 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
250 def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
251 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
252 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
253 def : MipsPat<(MipsLo tglobaltlsaddr:$in),
254 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
255 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
257 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
258 (DADDiu GPR64:$hi, tglobaladdr:$lo)>;
259 def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
260 (DADDiu GPR64:$hi, tblockaddress:$lo)>;
261 def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
262 (DADDiu GPR64:$hi, tjumptable:$lo)>;
263 def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
264 (DADDiu GPR64:$hi, tconstpool:$lo)>;
265 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
266 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
268 def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
269 def : WrapperPat<tconstpool, DADDiu, GPR64>;
270 def : WrapperPat<texternalsym, DADDiu, GPR64>;
271 def : WrapperPat<tblockaddress, DADDiu, GPR64>;
272 def : WrapperPat<tjumptable, DADDiu, GPR64>;
273 def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
275 defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
278 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
279 (BLEZ64 i64:$lhs, bb:$dst)>;
280 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
281 (BGEZ64 i64:$lhs, bb:$dst)>;
284 defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
285 defm : SetlePats<GPR64, SLT64, SLTu64>;
286 defm : SetgtPats<GPR64, SLT64, SLTu64>;
287 defm : SetgePats<GPR64, SLT64, SLTu64>;
288 defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
291 def : MipsPat<(i32 (trunc GPR64:$src)),
292 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>,
293 Requires<[HasStdEnc]>;
295 // 32-to-64-bit extension
296 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
297 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
298 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
300 // Sign extend in register
301 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
302 (SLL64_64 GPR64:$src)>;
305 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
307 //===----------------------------------------------------------------------===//
308 // Instruction aliases
309 //===----------------------------------------------------------------------===//
310 def : InstAlias<"move $dst, $src",
311 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
312 Requires<[HasMips64]>;
313 def : InstAlias<"daddu $rs, $rt, $imm",
314 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
316 def : InstAlias<"dadd $rs, $rt, $imm",
317 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
320 /// Move between CPU and coprocessor registers
321 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
322 def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
323 def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>;
324 def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>;
325 def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>;
328 // Two operand (implicit 0 selector) versions:
329 def : InstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
330 def : InstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
331 def : InstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
332 def : InstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;