1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
18 // Instruction operand types
19 def shamt_64 : Operand<i64>;
22 def uimm16_64 : Operand<i64> {
23 let PrintMethod = "printUnsignedImm";
26 // Transformation Function - get Imm - 32.
27 def Subtract32 : SDNodeXForm<imm, [{
28 return getImm(N, (unsigned)N->getZExtValue() - 32);
31 // shamt field must fit in 5 bits.
32 def immZExt5_64 : ImmLeaf<i64, [{return Imm == (Imm & 0x1f);}]>;
34 // imm32_63 predicate - True if imm is in range [32, 63].
35 def imm32_63 : ImmLeaf<i32,
36 [{return (int32_t)Imm >= 32 && (int32_t)Imm < 64;}],
40 def immSExt32 : ImmLeaf<i64, [{return isInt<32>(Imm);}]>;
42 // Transformation Function - get the higher 16 bits.
43 def HIGHER : SDNodeXForm<imm, [{
44 return getImm(N, (N->getZExtValue() >> 32) & 0xFFFF);
47 // Transformation Function - get the highest 16 bits.
48 def HIGHEST : SDNodeXForm<imm, [{
49 return getImm(N, (N->getZExtValue() >> 48) & 0xFFFF);
52 //===----------------------------------------------------------------------===//
53 // Instructions specific format
54 //===----------------------------------------------------------------------===//
56 // 64-bit shift instructions.
57 class shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm,
59 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt,
62 class shift_rotate_imm64_32<bits<6> func, bits<5> isRotate, string instr_asm,
64 shift_rotate_imm<func, isRotate, instr_asm, OpNode, imm32_63, shamt,
67 // Jump and Link (Call)
68 let isCall=1, hasDelaySlot=1,
69 // All calls clobber the non-callee saved registers...
70 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
71 K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
72 class JumpLink64<bits<6> op, string instr_asm>:
73 FJ<op, (outs), (ins calltarget64:$target, variable_ops),
74 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
77 class JumpLinkReg64<bits<6> op, bits<6> func, string instr_asm>:
78 FR<op, func, (outs), (ins CPU64Regs:$rs, variable_ops),
79 !strconcat(instr_asm, "\t$rs"),
80 [(MipsJmpLink CPU64Regs:$rs)], IIBranch> {
86 class BranchLink64<string instr_asm>:
87 FI<0x1, (outs), (ins CPU64Regs:$rs, brtarget:$imm16, variable_ops),
88 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch>;
92 class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>:
93 Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
94 class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
95 Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
97 multiclass Atomic2Ops64<PatFrag Op, string Opstr> {
98 def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>, Requires<[NotN64]>;
99 def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>, Requires<[IsN64]>;
102 multiclass AtomicCmpSwap64<PatFrag Op, string Width> {
103 def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>, Requires<[NotN64]>;
104 def _P8 : AtomicCmpSwap<Op, Width, CPU64Regs, CPU64Regs>,
108 let usesCustomInserter = 1, Predicates = [HasMips64] in {
109 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">;
110 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">;
111 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64, "load_and_64">;
112 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64, "load_or_64">;
113 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64, "load_xor_64">;
114 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64, "load_nand_64">;
115 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64, "swap_64">;
116 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64, "64">;
119 //===----------------------------------------------------------------------===//
120 // Instruction definition
121 //===----------------------------------------------------------------------===//
123 /// Arithmetic Instructions (ALU Immediate)
124 def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16,
126 def DANDi : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>;
127 def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
128 def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
129 def ORi64 : ArithLogicI<0x0d, "ori", or, uimm16_64, immZExt16, CPU64Regs>;
130 def XORi64 : ArithLogicI<0x0e, "xori", xor, uimm16_64, immZExt16, CPU64Regs>;
131 def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>;
133 /// Arithmetic Instructions (3-Operand, R-Type)
134 def DADDu : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>;
135 def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", sub, IIAlu, CPU64Regs>;
136 def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
137 def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>;
138 def AND64 : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPU64Regs, 1>;
139 def OR64 : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPU64Regs, 1>;
140 def XOR64 : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>;
141 def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>;
143 /// Shift Instructions
144 def DSLL : shift_rotate_imm64<0x38, 0x00, "dsll", shl>;
145 def DSRL : shift_rotate_imm64<0x3a, 0x00, "dsrl", srl>;
146 def DSRA : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>;
147 def DSLL32 : shift_rotate_imm64_32<0x3c, 0x00, "dsll32", shl>;
148 def DSRL32 : shift_rotate_imm64_32<0x3e, 0x00, "dsrl32", srl>;
149 def DSRA32 : shift_rotate_imm64_32<0x3f, 0x00, "dsra32", sra>;
150 def DSLLV : shift_rotate_reg<0x24, 0x00, "dsllv", shl, CPU64Regs>;
151 def DSRLV : shift_rotate_reg<0x26, 0x00, "dsrlv", srl, CPU64Regs>;
152 def DSRAV : shift_rotate_reg<0x27, 0x00, "dsrav", sra, CPU64Regs>;
154 // Rotate Instructions
155 let Predicates = [HasMips64r2] in {
156 def DROTR : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>;
157 def DROTR32 : shift_rotate_imm64_32<0x3e, 0x01, "drotr32", rotr>;
158 def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>;
161 /// Load and Store Instructions
163 defm LB64 : LoadM64<0x20, "lb", sextloadi8>;
164 defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>;
165 defm LH64 : LoadM64<0x21, "lh", sextloadi16_a>;
166 defm LHu64 : LoadM64<0x25, "lhu", zextloadi16_a>;
167 defm LW64 : LoadM64<0x23, "lw", sextloadi32_a>;
168 defm LWu64 : LoadM64<0x27, "lwu", zextloadi32_a>;
169 defm SB64 : StoreM64<0x28, "sb", truncstorei8>;
170 defm SH64 : StoreM64<0x29, "sh", truncstorei16_a>;
171 defm SW64 : StoreM64<0x2b, "sw", truncstorei32_a>;
172 defm LD : LoadM64<0x37, "ld", load_a>;
173 defm SD : StoreM64<0x3f, "sd", store_a>;
176 defm ULH64 : LoadM64<0x21, "ulh", sextloadi16_u, 1>;
177 defm ULHu64 : LoadM64<0x25, "ulhu", zextloadi16_u, 1>;
178 defm ULW64 : LoadM64<0x23, "ulw", sextloadi32_u, 1>;
179 defm USH64 : StoreM64<0x29, "ush", truncstorei16_u, 1>;
180 defm USW64 : StoreM64<0x2b, "usw", truncstorei32_u, 1>;
181 defm ULD : LoadM64<0x37, "uld", load_u, 1>;
182 defm USD : StoreM64<0x3f, "usd", store_u, 1>;
184 /// Load-linked, Store-conditional
185 def LLD : LLBase<0x34, "lld", CPU64Regs, mem>, Requires<[NotN64]>;
186 def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>, Requires<[IsN64]>;
187 def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>, Requires<[NotN64]>;
188 def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, Requires<[IsN64]>;
190 /// Jump and Branch Instructions
191 def JR64 : JumpFR<0x00, 0x08, "jr", CPU64Regs>;
192 def JAL64 : JumpLink64<0x03, "jal">;
193 def JALR64 : JumpLinkReg64<0x00, 0x09, "jalr">;
194 def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>;
195 def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>;
196 def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>;
197 def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>;
198 def BLEZ64 : CBranchZero<0x07, 0, "blez", setle, CPU64Regs>;
199 def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>;
201 /// Multiply and Divide Instructions.
202 def DMULT : Mult64<0x1c, "dmult", IIImul>;
203 def DMULTu : Mult64<0x1d, "dmultu", IIImul>;
204 def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
205 def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>;
207 def MTHI64 : MoveToLOHI<0x11, "mthi", CPU64Regs, [HI64]>;
208 def MTLO64 : MoveToLOHI<0x13, "mtlo", CPU64Regs, [LO64]>;
209 def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>;
210 def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>;
213 def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>;
214 def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>;
216 def LEA_ADDiu64 : EffectiveAddress<"addiu\t$rt, $addr", CPU64Regs, mem_ea_64>;
218 let Uses = [SP_64] in
219 def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>,
222 def DEXT : ExtBase<3, "dext", CPU64Regs>;
223 def DINS : InsBase<7, "dins", CPU64Regs>;
225 //===----------------------------------------------------------------------===//
226 // Arbitrary patterns that map to one or more instructions
227 //===----------------------------------------------------------------------===//
230 def : Pat<(i64 immSExt16:$in),
231 (DADDiu ZERO_64, imm:$in)>;
232 def : Pat<(i64 immZExt16:$in),
233 (ORi64 ZERO_64, imm:$in)>;
236 def : Pat<(i64 immSExt32:$imm),
237 (ORi64 (LUi64 (HI16 imm:$imm)), (LO16 imm:$imm))>;
239 // Arbitrary immediates
240 def : Pat<(i64 imm:$imm),
241 (ORi64 (DSLL (ORi64 (DSLL (ORi64 (LUi64 (HIGHEST imm:$imm)),
242 (HIGHER imm:$imm)), 16), (HI16 imm:$imm)), 16),
246 let Predicates = [NotN64] in {
247 def : Pat<(extloadi32_a addr:$a), (DSRL32 (DSLL32 (LW64 addr:$a), 0), 0)>;
248 def : Pat<(zextloadi32_u addr:$a), (DSRL32 (DSLL32 (ULW64 addr:$a), 0), 0)>;
250 let Predicates = [IsN64] in {
251 def : Pat<(extloadi32_a addr:$a), (DSRL32 (DSLL32 (LW64_P8 addr:$a), 0), 0)>;
252 def : Pat<(zextloadi32_u addr:$a),
253 (DSRL32 (DSLL32 (ULW64_P8 addr:$a), 0), 0)>;
257 def : Pat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
258 def : Pat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
259 def : Pat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
260 def : Pat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
262 def : Pat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
263 def : Pat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
264 def : Pat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
265 def : Pat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
267 def : Pat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
268 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
269 def : Pat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)),
270 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>;
271 def : Pat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)),
272 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
273 def : Pat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
274 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
276 def : WrapperPICPat<tglobaladdr, DADDiu, GP_64>;
277 def : WrapperPICPat<tconstpool, DADDiu, GP_64>;
278 def : WrapperPICPat<texternalsym, DADDiu, GP_64>;
279 def : WrapperPICPat<tblockaddress, DADDiu, GP_64>;
280 def : WrapperPICPat<tjumptable, DADDiu, GP_64>;
282 defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
286 defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
287 defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
288 defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
289 defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
290 defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
292 // select MipsDynAlloc
293 def : Pat<(MipsDynAlloc addr:$f), (DynAlloc64 addr:$f)>, Requires<[IsN64]>;
296 def : Pat<(i32 (trunc CPU64Regs:$src)),
297 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, Requires<[IsN64]>;