1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
18 // Instruction operand types
19 def shamt_64 : Operand<i64>;
22 def uimm16_64 : Operand<i64> {
23 let PrintMethod = "printUnsignedImm";
26 // Transformation Function - get Imm - 32.
27 def Subtract32 : SDNodeXForm<imm, [{
28 return getImm(N, (unsigned)N->getZExtValue() - 32);
31 // shamt must fit in 6 bits.
32 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
34 //===----------------------------------------------------------------------===//
35 // Instructions specific format
36 //===----------------------------------------------------------------------===//
37 let DecoderNamespace = "Mips64" in {
39 multiclass Atomic2Ops64<PatFrag Op> {
40 def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>,
41 Requires<[NotN64, HasStdEnc]>;
42 def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>,
43 Requires<[IsN64, HasStdEnc]> {
44 let isCodeGenOnly = 1;
48 multiclass AtomicCmpSwap64<PatFrag Op> {
49 def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>,
50 Requires<[NotN64, HasStdEnc]>;
51 def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>,
52 Requires<[IsN64, HasStdEnc]> {
53 let isCodeGenOnly = 1;
57 let usesCustomInserter = 1, Predicates = [HasStdEnc],
58 DecoderNamespace = "Mips64" in {
59 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>;
60 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>;
61 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>;
62 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>;
63 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>;
64 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>;
65 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>;
66 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>;
69 /// Pseudo instructions for loading and storing accumulator registers.
71 defm LOAD_AC128 : LoadM<"load_ac128", ACRegs128>;
72 defm STORE_AC128 : StoreM<"store_ac128", ACRegs128>;
75 //===----------------------------------------------------------------------===//
76 // Instruction definition
77 //===----------------------------------------------------------------------===//
78 let DecoderNamespace = "Mips64" in {
79 /// Arithmetic Instructions (ALU Immediate)
80 def DADDi : ArithLogicI<"daddi", simm16_64, CPU64RegsOpnd>, ADDI_FM<0x18>;
81 def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, immSExt16, add>,
82 ADDI_FM<0x19>, IsAsCheapAsAMove;
83 def DANDi : ArithLogicI<"andi", uimm16_64, CPU64RegsOpnd, immZExt16, and>,
85 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>,
87 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>,
89 def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64RegsOpnd, immZExt16, or>,
91 def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, immZExt16, xor>,
93 def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM;
95 /// Arithmetic Instructions (3-Operand, R-Type)
96 def DADD : ArithLogicR<"dadd", CPU64RegsOpnd>, ADD_FM<0, 0x2c>;
97 def DADDu : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIAlu, add>,
99 def DSUBu : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIAlu, sub>,
101 def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>;
102 def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>;
103 def AND64 : ArithLogicR<"and", CPU64RegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>;
104 def OR64 : ArithLogicR<"or", CPU64RegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>;
105 def XOR64 : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
106 def NOR64 : LogicNOR<"nor", CPU64RegsOpnd>, ADD_FM<0, 0x27>;
108 /// Shift Instructions
109 def DSLL : shift_rotate_imm<"dsll", shamt, CPU64RegsOpnd, shl, immZExt6>,
111 def DSRL : shift_rotate_imm<"dsrl", shamt, CPU64RegsOpnd, srl, immZExt6>,
113 def DSRA : shift_rotate_imm<"dsra", shamt, CPU64RegsOpnd, sra, immZExt6>,
115 def DSLLV : shift_rotate_reg<"dsllv", CPU64RegsOpnd, shl>, SRLV_FM<0x14, 0>;
116 def DSRLV : shift_rotate_reg<"dsrlv", CPU64RegsOpnd, srl>, SRLV_FM<0x16, 0>;
117 def DSRAV : shift_rotate_reg<"dsrav", CPU64RegsOpnd, sra>, SRLV_FM<0x17, 0>;
118 def DSLL32 : shift_rotate_imm<"dsll32", shamt, CPU64RegsOpnd>, SRA_FM<0x3c, 0>;
119 def DSRL32 : shift_rotate_imm<"dsrl32", shamt, CPU64RegsOpnd>, SRA_FM<0x3e, 0>;
120 def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64RegsOpnd>, SRA_FM<0x3f, 0>;
122 // Rotate Instructions
123 let Predicates = [HasMips64r2, HasStdEnc],
124 DecoderNamespace = "Mips64" in {
125 def DROTR : shift_rotate_imm<"drotr", shamt, CPU64RegsOpnd, rotr, immZExt6>,
127 def DROTRV : shift_rotate_reg<"drotrv", CPU64RegsOpnd, rotr>,
131 let DecoderNamespace = "Mips64" in {
132 /// Load and Store Instructions
134 defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8>, LW_FM<0x20>;
135 defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8>, LW_FM<0x24>;
136 defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16>, LW_FM<0x21>;
137 defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16>, LW_FM<0x25>;
138 defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32>, LW_FM<0x23>;
139 defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32>, LW_FM<0x27>;
140 defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8>, LW_FM<0x28>;
141 defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16>, LW_FM<0x29>;
142 defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32>, LW_FM<0x2b>;
143 defm LD : LoadM<"ld", CPU64Regs, load>, LW_FM<0x37>;
144 defm SD : StoreM<"sd", CPU64Regs, store>, LW_FM<0x3f>;
146 /// load/store left/right
147 defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>;
148 defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>;
149 defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>;
150 defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>;
152 defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>;
153 defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>;
154 defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>;
155 defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>;
157 /// Load-linked, Store-conditional
158 let Predicates = [NotN64, HasStdEnc] in {
159 def LLD : LLBase<"lld", CPU64RegsOpnd, mem>, LW_FM<0x34>;
160 def SCD : SCBase<"scd", CPU64RegsOpnd, mem>, LW_FM<0x3c>;
163 let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in {
164 def LLD_P8 : LLBase<"lld", CPU64RegsOpnd, mem64>, LW_FM<0x34>;
165 def SCD_P8 : SCBase<"scd", CPU64RegsOpnd, mem64>, LW_FM<0x3c>;
168 /// Jump and Branch Instructions
169 def JR64 : IndirectBranch<CPU64Regs>, MTLO_FM<8>;
170 def BEQ64 : CBranch<"beq", seteq, CPU64RegsOpnd>, BEQ_FM<4>;
171 def BNE64 : CBranch<"bne", setne, CPU64RegsOpnd>, BEQ_FM<5>;
172 def BGEZ64 : CBranchZero<"bgez", setge, CPU64RegsOpnd>, BGEZ_FM<1, 1>;
173 def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64RegsOpnd>, BGEZ_FM<7, 0>;
174 def BLEZ64 : CBranchZero<"blez", setle, CPU64RegsOpnd>, BGEZ_FM<6, 0>;
175 def BLTZ64 : CBranchZero<"bltz", setlt, CPU64RegsOpnd>, BGEZ_FM<1, 0>;
177 let DecoderNamespace = "Mips64" in
178 def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM;
179 def JALR64Pseudo : JumpLinkRegPseudo<CPU64Regs, JALR64, RA_64>;
180 def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
182 let DecoderNamespace = "Mips64" in {
183 /// Multiply and Divide Instructions.
184 def DMULT : Mult<"dmult", IIImul, CPU64RegsOpnd, [HI64, LO64]>,
186 def DMULTu : Mult<"dmultu", IIImul, CPU64RegsOpnd, [HI64, LO64]>,
188 def PseudoDMULT : MultDivPseudo<DMULT, ACRegs128, CPU64RegsOpnd, MipsMult,
190 def PseudoDMULTu : MultDivPseudo<DMULTu, ACRegs128, CPU64RegsOpnd, MipsMultu,
192 def DSDIV : Div<"ddiv", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1e>;
193 def DUDIV : Div<"ddivu", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>, MULT_FM<0, 0x1f>;
194 def PseudoDSDIV : MultDivPseudo<DSDIV, ACRegs128, CPU64RegsOpnd, MipsDivRem,
196 def PseudoDUDIV : MultDivPseudo<DUDIV, ACRegs128, CPU64RegsOpnd, MipsDivRemU,
199 def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>;
200 def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>;
201 def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>;
202 def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>;
204 /// Sign Ext In Register Instructions.
205 def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10, 0x20>;
206 def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18, 0x20>;
209 def DCLZ : CountLeading0<"dclz", CPU64RegsOpnd>, CLO_FM<0x24>;
210 def DCLO : CountLeading1<"dclo", CPU64RegsOpnd>, CLO_FM<0x25>;
212 /// Double Word Swap Bytes/HalfWords
213 def DSBH : SubwordSwap<"dsbh", CPU64RegsOpnd>, SEB_FM<2, 0x24>;
214 def DSHD : SubwordSwap<"dshd", CPU64RegsOpnd>, SEB_FM<5, 0x24>;
216 def LEA_ADDiu64 : EffectiveAddress<"daddiu", CPU64Regs, mem_ea_64>, LW_FM<0x19>;
219 let DecoderNamespace = "Mips64" in {
220 def RDHWR64 : ReadHardware<CPU64Regs, HW64RegsOpnd>, RDHWR_FM;
222 def DEXT : ExtBase<"dext", CPU64RegsOpnd>, EXT_FM<3>;
223 let Pattern = []<dag> in {
224 def DEXTU : ExtBase<"dextu", CPU64RegsOpnd>, EXT_FM<2>;
225 def DEXTM : ExtBase<"dextm", CPU64RegsOpnd>, EXT_FM<1>;
227 def DINS : InsBase<"dins", CPU64RegsOpnd>, EXT_FM<7>;
228 let Pattern = []<dag> in {
229 def DINSU : InsBase<"dinsu", CPU64RegsOpnd>, EXT_FM<6>;
230 def DINSM : InsBase<"dinsm", CPU64RegsOpnd>, EXT_FM<5>;
233 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
234 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
235 "dsll\t$rd, $rt, 32", [], IIAlu>;
236 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
237 "sll\t$rd, $rt, 0", [], IIAlu>;
238 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
239 "sll\t$rd, $rt, 0", [], IIAlu>;
242 //===----------------------------------------------------------------------===//
243 // Arbitrary patterns that map to one or more instructions
244 //===----------------------------------------------------------------------===//
247 let Predicates = [NotN64, HasStdEnc] in {
248 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
249 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
250 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
251 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
253 let Predicates = [IsN64, HasStdEnc] in {
254 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>;
255 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>;
256 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>;
257 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>;
261 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
262 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
263 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
264 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
265 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
266 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
268 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
269 def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
270 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
271 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
272 def : MipsPat<(MipsLo tglobaltlsaddr:$in),
273 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
274 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
276 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
277 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
278 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)),
279 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>;
280 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)),
281 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
282 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
283 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
284 def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)),
285 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>;
287 def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>;
288 def : WrapperPat<tconstpool, DADDiu, CPU64Regs>;
289 def : WrapperPat<texternalsym, DADDiu, CPU64Regs>;
290 def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>;
291 def : WrapperPat<tjumptable, DADDiu, CPU64Regs>;
292 def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>;
294 defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
297 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
298 (BLEZ64 i64:$lhs, bb:$dst)>;
299 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
300 (BGEZ64 i64:$lhs, bb:$dst)>;
303 defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
304 defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
305 defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
306 defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
307 defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
310 def : MipsPat<(i32 (trunc CPU64Regs:$src)),
311 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>,
312 Requires<[IsN64, HasStdEnc]>;
314 // 32-to-64-bit extension
315 def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
316 def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;
317 def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
319 // Sign extend in register
320 def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)),
321 (SLL64_64 CPU64Regs:$src)>;
324 def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
327 def : MipsPat<(i64 (ExtractLOHI ACRegs128:$ac, imm:$lohi_idx)),
328 (EXTRACT_SUBREG ACRegs128:$ac, imm:$lohi_idx)>;
330 //===----------------------------------------------------------------------===//
331 // Instruction aliases
332 //===----------------------------------------------------------------------===//
333 def : InstAlias<"move $dst, $src",
334 (DADDu CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>,
335 Requires<[HasMips64]>;
336 def : InstAlias<"move $dst, $src",
337 (OR64 CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>,
338 Requires<[HasMips64]>;
339 def : InstAlias<"and $rs, $rt, $imm",
340 (DANDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
342 Requires<[HasMips64]>;
343 def : InstAlias<"slt $rs, $rt, $imm",
344 (SLTi64 CPURegsOpnd:$rs, CPU64Regs:$rt, simm16_64:$imm), 1>,
345 Requires<[HasMips64]>;
346 def : InstAlias<"xor $rs, $rt, $imm",
347 (XORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
349 Requires<[HasMips64]>;
350 def : InstAlias<"not $rt, $rs",
351 (NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64), 1>,
352 Requires<[HasMips64]>;
353 def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs), 0>, Requires<[HasMips64]>;
354 def : InstAlias<"jalr $rs", (JALR64 RA_64, CPU64Regs:$rs)>,
355 Requires<[HasMips64]>;
356 def : InstAlias<"jal $rs", (JALR64 RA_64, CPU64Regs:$rs), 0>,
357 Requires<[HasMips64]>;
358 def : InstAlias<"jal $rd,$rs", (JALR64 CPU64Regs:$rd, CPU64Regs:$rs), 0>,
359 Requires<[HasMips64]>;
360 def : InstAlias<"daddu $rs, $rt, $imm",
361 (DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
363 def : InstAlias<"dadd $rs, $rt, $imm",
364 (DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
366 def : InstAlias<"or $rs, $rt, $imm",
367 (ORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
368 1>, Requires<[HasMips64]>;
369 def : InstAlias<"bnez $rs,$offset",
370 (BNE64 CPU64RegsOpnd:$rs, ZERO_64, brtarget:$offset), 1>,
371 Requires<[HasMips64]>;
372 def : InstAlias<"beqz $rs,$offset",
373 (BEQ64 CPU64RegsOpnd:$rs, ZERO_64, brtarget:$offset), 1>,
374 Requires<[HasMips64]>;
376 /// Move between CPU and coprocessor registers
377 let DecoderNamespace = "Mips64" in {
378 def DMFC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt),
379 (ins CPU64RegsOpnd:$rd, uimm16:$sel),
380 "dmfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 1>;
381 def DMTC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel),
382 (ins CPU64RegsOpnd:$rt),
383 "dmtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 5>;
384 def DMFC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt),
385 (ins CPU64RegsOpnd:$rd, uimm16:$sel),
386 "dmfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 1>;
387 def DMTC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel),
388 (ins CPU64RegsOpnd:$rt),
389 "dmtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 5>;
392 // Two operand (implicit 0 selector) versions:
393 def : InstAlias<"dmfc0 $rt, $rd",
394 (DMFC0_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>;
395 def : InstAlias<"dmtc0 $rt, $rd",
396 (DMTC0_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>;
397 def : InstAlias<"dmfc2 $rt, $rd",
398 (DMFC2_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>;
399 def : InstAlias<"dmtc2 $rt, $rd",
400 (DMTC2_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>;