1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
19 def uimm16_64 : Operand<i64> {
20 let PrintMethod = "printUnsignedImm";
23 // Transformation Function - get Imm - 32.
24 def Subtract32 : SDNodeXForm<imm, [{
25 return getImm(N, (unsigned)N->getZExtValue() - 32);
28 // shamt must fit in 6 bits.
29 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
31 //===----------------------------------------------------------------------===//
32 // Instructions specific format
33 //===----------------------------------------------------------------------===//
34 let usesCustomInserter = 1 in {
35 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
36 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
37 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
38 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
39 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
40 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
41 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
42 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
45 /// Pseudo instructions for loading and storing accumulator registers.
46 let isPseudo = 1, isCodeGenOnly = 1 in {
47 def LOAD_ACC128 : Load<"", ACC128>;
48 def STORE_ACC128 : Store<"", ACC128>;
51 //===----------------------------------------------------------------------===//
52 // Instruction definition
53 //===----------------------------------------------------------------------===//
54 let DecoderNamespace = "Mips64" in {
55 /// Arithmetic Instructions (ALU Immediate)
56 def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>;
57 def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
59 ADDI_FM<0x19>, IsAsCheapAsAMove;
61 let isCodeGenOnly = 1 in {
62 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
64 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
66 def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
68 def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
70 def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
72 def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
75 /// Arithmetic Instructions (3-Operand, R-Type)
76 def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>;
77 def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
79 def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>,
81 def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB, sub>, ADD_FM<0, 0x2e>;
83 let isCodeGenOnly = 1 in {
84 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
85 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
86 def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
87 def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
88 def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
89 def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
92 /// Shift Instructions
93 def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
95 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
97 def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
99 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
101 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
103 def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
105 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
107 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
109 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
112 // Rotate Instructions
113 let Predicates = [HasMips64r2, HasStdEnc] in {
114 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
115 immZExt6>, SRA_FM<0x3a, 1>;
116 def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
118 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
122 /// Load and Store Instructions
124 let isCodeGenOnly = 1 in {
125 def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>;
126 def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>;
127 def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>;
128 def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
129 def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>;
130 def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>;
131 def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>;
132 def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>;
135 def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>;
136 def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>;
137 def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>;
139 /// load/store left/right
140 let isCodeGenOnly = 1 in {
141 def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>;
142 def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>;
143 def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>;
144 def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>;
147 def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>;
148 def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>;
149 def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>;
150 def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>;
152 /// Load-linked, Store-conditional
153 def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>;
154 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>;
156 /// Jump and Branch Instructions
157 let isCodeGenOnly = 1 in {
158 def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>;
159 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
160 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
161 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
162 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
163 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
164 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
165 def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
166 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
167 def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
170 /// Multiply and Divide Instructions.
171 def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
173 def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
175 def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
177 def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
179 def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
181 def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
183 def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
185 def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
188 let isCodeGenOnly = 1 in {
189 def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>;
190 def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>;
191 def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>;
192 def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>;
193 def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>;
194 def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>;
195 def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>;
197 /// Sign Ext In Register Instructions.
198 def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
199 def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
203 def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>;
204 def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>;
206 /// Double Word Swap Bytes/HalfWords
207 def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>;
208 def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>;
210 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
212 let isCodeGenOnly = 1 in
213 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
215 def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
216 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
217 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
219 def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
220 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>;
221 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
223 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
224 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
225 "dsll\t$rd, $rt, 32", [], II_DSLL>;
226 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
227 "sll\t$rd, $rt, 0", [], II_SLL>;
228 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
229 "sll\t$rd, $rt, 0", [], II_SLL>;
232 // Cavium Octeon cmMIPS instructions
233 let Predicates = [HasCnMips] in {
235 class Count1s<string opstr, RegisterOperand RO>:
236 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
237 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr>;
239 class SetCC64_R<string opstr, PatFrag cond_op> :
240 InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
241 !strconcat(opstr, "\t$rd, $rs, $rt"),
242 [(set GPR64Opnd:$rd, (cond_op GPR64Opnd:$rs, GPR64Opnd:$rt))],
243 II_SEQ_SNE, FrmR, opstr>;
246 def BADDu : InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
247 "baddu\t$rd, $rs, $rt",
248 [(set GPR64Opnd:$rd, (and (add GPR64Opnd:$rs,
249 GPR64Opnd:$rt), 255))],
250 II_BADDU, FrmR, "baddu">, ADD_FM<0x1c, 0x28> {
251 let isCommutable = 1;
252 let isReMaterializable = 1;
255 // Multiply Doubleword to GPR
256 let Defs = [HI0, LO0, P0, P1, P2] in
257 def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
260 // Count Ones in a Word/Doubleword
261 def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>;
262 def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>;
264 // Set on equal/not equal
265 def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>;
266 def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>;
270 //===----------------------------------------------------------------------===//
271 // Arbitrary patterns that map to one or more instructions
272 //===----------------------------------------------------------------------===//
275 let Predicates = [HasStdEnc] in {
276 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
277 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
278 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
279 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
283 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
284 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
285 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
286 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
287 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
288 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
290 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
291 def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
292 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
293 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
294 def : MipsPat<(MipsLo tglobaltlsaddr:$in),
295 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
296 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
298 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
299 (DADDiu GPR64:$hi, tglobaladdr:$lo)>;
300 def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
301 (DADDiu GPR64:$hi, tblockaddress:$lo)>;
302 def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
303 (DADDiu GPR64:$hi, tjumptable:$lo)>;
304 def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
305 (DADDiu GPR64:$hi, tconstpool:$lo)>;
306 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
307 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
309 def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
310 def : WrapperPat<tconstpool, DADDiu, GPR64>;
311 def : WrapperPat<texternalsym, DADDiu, GPR64>;
312 def : WrapperPat<tblockaddress, DADDiu, GPR64>;
313 def : WrapperPat<tjumptable, DADDiu, GPR64>;
314 def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
316 defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
319 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
320 (BLEZ64 i64:$lhs, bb:$dst)>;
321 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
322 (BGEZ64 i64:$lhs, bb:$dst)>;
325 defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
326 defm : SetlePats<GPR64, SLT64, SLTu64>;
327 defm : SetgtPats<GPR64, SLT64, SLTu64>;
328 defm : SetgePats<GPR64, SLT64, SLTu64>;
329 defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
332 def : MipsPat<(i32 (trunc GPR64:$src)),
333 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>,
334 Requires<[HasStdEnc]>;
336 // 32-to-64-bit extension
337 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
338 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
339 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
341 // Sign extend in register
342 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
343 (SLL64_64 GPR64:$src)>;
346 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
348 //===----------------------------------------------------------------------===//
349 // Instruction aliases
350 //===----------------------------------------------------------------------===//
351 def : InstAlias<"move $dst, $src",
352 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
353 Requires<[HasMips64]>;
354 def : InstAlias<"daddu $rs, $rt, $imm",
355 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
357 def : InstAlias<"dadd $rs, $rt, $imm",
358 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
360 def : InstAlias<"daddu $rs, $imm",
361 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
363 def : InstAlias<"dadd $rs, $imm",
364 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
366 def : InstAlias<"add $rs, $imm",
367 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
369 def : InstAlias<"addu $rs, $imm",
370 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
372 let isPseudo=1, usesCustomInserter=1, isCodeGenOnly=1 in {
373 def SUBi : MipsInst<(outs GPR32Opnd: $rt), (ins GPR32Opnd: $rs, simm16: $imm),
374 "sub\t$rt, $rs, $imm", [], II_DSUB, Pseudo>;
375 def SUBiu : MipsInst<(outs GPR32Opnd: $rt), (ins GPR32Opnd: $rs, simm16: $imm),
376 "subu\t$rt, $rs, $imm", [], II_DSUB, Pseudo>;
377 def DSUBi : MipsInst<(outs GPR64Opnd: $rt), (ins GPR64Opnd: $rs, simm16_64: $imm),
378 "ssub\t$rt, $rs, $imm", [], II_DSUB, Pseudo>;
379 def DSUBiu : MipsInst<(outs GPR64Opnd: $rt), (ins GPR64Opnd: $rs, simm16_64: $imm),
380 "ssubu\t$rt, $rs, $imm", [], II_DSUB, Pseudo>;
382 def : InstAlias<"dsubu $rt, $rs, $imm",
383 (DSUBiu GPR64Opnd:$rt, GPR64Opnd:$rs, simm16_64: $imm),
385 def : InstAlias<"sub $rs, $imm",
386 (SUBi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
388 def : InstAlias<"subu $rs, $imm",
389 (SUBiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
391 def : InstAlias<"dsub $rs, $imm",
392 (DSUBi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
394 def : InstAlias<"dsubu $rs, $imm",
395 (DSUBiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
398 /// Move between CPU and coprocessor registers
399 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
400 def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
401 def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>;
402 def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>;
403 def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>;
406 // Two operand (implicit 0 selector) versions:
407 def : InstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
408 def : InstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
409 def : InstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
410 def : InstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;