1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
18 // Instruction operand types
19 def shamt_64 : Operand<i64>;
22 def uimm16_64 : Operand<i64> {
23 let PrintMethod = "printUnsignedImm";
26 // Transformation Function - get Imm - 32.
27 def Subtract32 : SDNodeXForm<imm, [{
28 return getI32Imm((unsigned)N->getZExtValue() - 32);
31 // imm32_63 predicate - True if imm is in range [32, 63].
32 def imm32_63 : ImmLeaf<i64,
33 [{return (int32_t)Imm >= 32 && (int32_t)Imm < 64;}],
36 //===----------------------------------------------------------------------===//
37 // Instructions specific format
38 //===----------------------------------------------------------------------===//
41 let isCommutable = 1 in
42 class LogicNOR64<bits<6> op, bits<6> func, string instr_asm>:
43 FR<op, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, CPU64Regs:$c),
44 !strconcat(instr_asm, "\t$dst, $b, $c"),
45 [(set CPU64Regs:$dst, (not (or CPU64Regs:$b, CPU64Regs:$c)))], IIAlu>;
48 class LogicR_shift_rotate_imm64<bits<6> func, bits<5> _rs, string instr_asm,
49 SDNode OpNode, PatFrag PF>:
50 FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, shamt_64:$c),
51 !strconcat(instr_asm, "\t$dst, $b, $c"),
52 [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, (i64 PF:$c)))],
57 class LogicR_shift_rotate_reg64<bits<6> func, bits<5> _shamt, string instr_asm,
59 FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$c, CPU64Regs:$b),
60 !strconcat(instr_asm, "\t$dst, $b, $c"),
61 [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], IIAlu> {
66 let Defs = [HI64, LO64] in {
67 let isCommutable = 1 in
68 class Mul64<bits<6> func, string instr_asm, InstrItinClass itin>:
69 FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
70 !strconcat(instr_asm, "\t$a, $b"), [], itin>;
72 class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
73 FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
74 !strconcat(instr_asm, "\t$$zero, $a, $b"),
75 [(op CPU64Regs:$a, CPU64Regs:$b)], itin>;
81 class MoveFromLOHI64<bits<6> func, string instr_asm>:
82 FR<0x00, func, (outs CPU64Regs:$dst), (ins),
83 !strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
86 class MoveToLOHI64<bits<6> func, string instr_asm>:
87 FR<0x00, func, (outs), (ins CPU64Regs:$src),
88 !strconcat(instr_asm, "\t$src"), [], IIHiLo>;
91 // Count Leading Ones/Zeros in Word
92 class CountLeading64<bits<6> func, string instr_asm, list<dag> pattern>:
93 FR<0x1c, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$src),
94 !strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
95 Requires<[HasBitCount]> {
100 //===----------------------------------------------------------------------===//
101 // Instruction definition
102 //===----------------------------------------------------------------------===//
104 /// Arithmetic Instructions (ALU Immediate)
105 def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16,
107 def DANDi : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>;
108 def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
109 def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
110 def ORi64 : ArithLogicI<0x0d, "ori", or, uimm16_64, immZExt16, CPU64Regs>;
111 def XORi64 : ArithLogicI<0x0e, "xori", xor, uimm16_64, immZExt16, CPU64Regs>;
113 /// Arithmetic Instructions (3-Operand, R-Type)
114 def DADDu : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>;
115 def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", sub, IIAlu, CPU64Regs>;
116 def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
117 def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>;
118 def AND64 : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPU64Regs, 1>;
119 def OR64 : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPU64Regs, 1>;
120 def XOR64 : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>;
121 def NOR64 : LogicNOR64<0x00, 0x27, "nor">;
123 /// Shift Instructions
124 def DSLL : LogicR_shift_rotate_imm64<0x38, 0x00, "dsll", shl, immZExt5>;
125 def DSRL : LogicR_shift_rotate_imm64<0x3a, 0x00, "dsrl", srl, immZExt5>;
126 def DSRA : LogicR_shift_rotate_imm64<0x3b, 0x00, "dsra", sra, immZExt5>;
127 def DSLL32 : LogicR_shift_rotate_imm64<0x3c, 0x00, "dsll32", shl, imm32_63>;
128 def DSRL32 : LogicR_shift_rotate_imm64<0x3e, 0x00, "dsrl32", srl, imm32_63>;
129 def DSRA32 : LogicR_shift_rotate_imm64<0x3f, 0x00, "dsra32", sra, imm32_63>;
130 def DSLLV : LogicR_shift_rotate_reg64<0x24, 0x00, "dsllv", shl>;
131 def DSRLV : LogicR_shift_rotate_reg64<0x26, 0x00, "dsrlv", srl>;
132 def DSRAV : LogicR_shift_rotate_reg64<0x27, 0x00, "dsrav", sra>;
134 // Rotate Instructions
135 let Predicates = [HasMips64r2] in {
136 def DROTR : LogicR_shift_rotate_imm64<0x3a, 0x01, "drotr", rotr, immZExt5>;
137 def DROTR32 : LogicR_shift_rotate_imm64<0x3e, 0x01, "drotr32", rotr,
139 def DROTRV : LogicR_shift_rotate_reg64<0x16, 0x01, "drotrv", rotr>;
142 /// Load and Store Instructions
144 defm LB64 : LoadM64<0x20, "lb", sextloadi8>;
145 defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>;
146 defm LH64 : LoadM64<0x21, "lh", sextloadi16_a>;
147 defm LHu64 : LoadM64<0x25, "lhu", zextloadi16_a>;
148 defm LW64 : LoadM64<0x23, "lw", sextloadi32_a>;
149 defm LWu64 : LoadM64<0x27, "lwu", zextloadi32_a>;
150 defm SB64 : StoreM64<0x28, "sb", truncstorei8>;
151 defm SH64 : StoreM64<0x29, "sh", truncstorei16_a>;
152 defm SW64 : StoreM64<0x2b, "sw", truncstorei32_a>;
153 defm LD : LoadM64<0x37, "ld", load_a>;
154 defm SD : StoreM64<0x3f, "sd", store_a>;
157 defm ULH64 : LoadM64<0x21, "ulh", sextloadi16_u, 1>;
158 defm ULHu64 : LoadM64<0x25, "ulhu", zextloadi16_u, 1>;
159 defm ULW64 : LoadM64<0x23, "ulw", sextloadi32_u, 1>;
160 defm USH64 : StoreM64<0x29, "ush", truncstorei16_u, 1>;
161 defm USW64 : StoreM64<0x2b, "usw", truncstorei32_u, 1>;
162 defm ULD : LoadM64<0x37, "uld", load_u, 1>;
163 defm USD : StoreM64<0x3f, "usd", store_u, 1>;
165 /// Jump and Branch Instructions
166 def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>;
167 def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>;
168 def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>;
169 def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>;
170 def BLEZ64 : CBranchZero<0x07, 0, "blez", setle, CPU64Regs>;
171 def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>;
173 /// Multiply and Divide Instructions.
174 def DMULT : Mul64<0x1c, "dmult", IIImul>;
175 def DMULTu : Mul64<0x1d, "dmultu", IIImul>;
176 def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
177 def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>;
180 def MTHI64 : MoveToLOHI64<0x11, "mthi">;
182 def MTLO64 : MoveToLOHI64<0x13, "mtlo">;
185 def MFHI64 : MoveFromLOHI64<0x10, "mfhi">;
187 def MFLO64 : MoveFromLOHI64<0x12, "mflo">;
190 def DCLZ : CountLeading64<0x24, "dclz",
191 [(set CPU64Regs:$dst, (ctlz CPU64Regs:$src))]>;
192 def DCLO : CountLeading64<0x25, "dclo",
193 [(set CPU64Regs:$dst, (ctlz (not CPU64Regs:$src)))]>;
195 //===----------------------------------------------------------------------===//
196 // Arbitrary patterns that map to one or more instructions
197 //===----------------------------------------------------------------------===//
200 def : Pat<(i64 immSExt16:$in),
201 (DADDiu ZERO_64, imm:$in)>;
202 def : Pat<(i64 immZExt16:$in),
203 (ORi64 ZERO_64, imm:$in)>;
206 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>,
208 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>,
212 def : Pat<(i64 (MipsLo tglobaladdr:$in)), (DADDiu ZERO_64, tglobaladdr:$in)>;
214 defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
218 defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
219 defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
220 defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
221 defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
222 defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;