1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
18 // Instruction operand types
19 def shamt_64 : Operand<i64>;
22 def uimm16_64 : Operand<i64> {
23 let PrintMethod = "printUnsignedImm";
26 // Transformation Function - get Imm - 32.
27 def Subtract32 : SDNodeXForm<imm, [{
28 return getI32Imm((unsigned)N->getZExtValue() - 32);
31 // imm32_63 predicate - True if imm is in range [32, 63].
32 def imm32_63 : ImmLeaf<i64,
33 [{return (int32_t)Imm >= 32 && (int32_t)Imm < 64;}],
36 //===----------------------------------------------------------------------===//
37 // Instructions specific format
38 //===----------------------------------------------------------------------===//
40 // Arithmetic 3 register operands
41 class ArithR64<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
42 InstrItinClass itin, bit isComm = 0>:
43 FR<op, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, CPU64Regs:$c),
44 !strconcat(instr_asm, "\t$dst, $b, $c"),
45 [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], itin> {
46 let isCommutable = isComm;
49 // Arithmetic 2 register operands
50 class ArithI64<bits<6> op, string instr_asm, SDNode OpNode,
51 Operand Od, PatLeaf imm_type> :
52 FI<op, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, Od:$c),
53 !strconcat(instr_asm, "\t$dst, $b, $c"),
54 [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, imm_type:$c))], IIAlu>;
57 let isCommutable = 1 in
58 class LogicR64<bits<6> func, string instr_asm, SDNode OpNode>:
59 FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, CPU64Regs:$c),
60 !strconcat(instr_asm, "\t$dst, $b, $c"),
61 [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], IIAlu>;
63 class LogicI64<bits<6> op, string instr_asm, SDNode OpNode>:
64 FI<op, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, uimm16_64:$c),
65 !strconcat(instr_asm, "\t$dst, $b, $c"),
66 [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, immZExt16:$c))], IIAlu>;
68 let isCommutable = 1 in
69 class LogicNOR64<bits<6> op, bits<6> func, string instr_asm>:
70 FR<op, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, CPU64Regs:$c),
71 !strconcat(instr_asm, "\t$dst, $b, $c"),
72 [(set CPU64Regs:$dst, (not (or CPU64Regs:$b, CPU64Regs:$c)))], IIAlu>;
75 class LogicR_shift_rotate_imm64<bits<6> func, bits<5> _rs, string instr_asm,
76 SDNode OpNode, PatFrag PF>:
77 FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, shamt_64:$c),
78 !strconcat(instr_asm, "\t$dst, $b, $c"),
79 [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, (i64 PF:$c)))],
84 class LogicR_shift_rotate_reg64<bits<6> func, bits<5> _shamt, string instr_asm,
86 FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$c, CPU64Regs:$b),
87 !strconcat(instr_asm, "\t$dst, $b, $c"),
88 [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], IIAlu> {
93 let Defs = [HI64, LO64] in {
94 let isCommutable = 1 in
95 class Mul64<bits<6> func, string instr_asm, InstrItinClass itin>:
96 FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
97 !strconcat(instr_asm, "\t$a, $b"), [], itin>;
99 class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
100 FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
101 !strconcat(instr_asm, "\t$$zero, $a, $b"),
102 [(op CPU64Regs:$a, CPU64Regs:$b)], itin>;
107 let rs = 0, rt = 0 in
108 class MoveFromLOHI64<bits<6> func, string instr_asm>:
109 FR<0x00, func, (outs CPU64Regs:$dst), (ins),
110 !strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
112 let rt = 0, rd = 0 in
113 class MoveToLOHI64<bits<6> func, string instr_asm>:
114 FR<0x00, func, (outs), (ins CPU64Regs:$src),
115 !strconcat(instr_asm, "\t$src"), [], IIHiLo>;
118 // Count Leading Ones/Zeros in Word
119 class CountLeading64<bits<6> func, string instr_asm, list<dag> pattern>:
120 FR<0x1c, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$src),
121 !strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
122 Requires<[HasBitCount]> {
127 //===----------------------------------------------------------------------===//
128 // Instruction definition
129 //===----------------------------------------------------------------------===//
131 /// Arithmetic Instructions (ALU Immediate)
132 def DADDiu : ArithI64<0x19, "daddiu", add, simm16_64, immSExt16>;
133 def DANDi : LogicI64<0x0c, "andi", and>;
134 def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
135 def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
136 def DORi : LogicI64<0x0d, "ori", or>;
137 def DXORi : LogicI64<0x0e, "xori", xor>;
139 /// Arithmetic Instructions (3-Operand, R-Type)
140 def DADDu : ArithR64<0x00, 0x2d, "daddu", add, IIAlu, 1>;
141 def DSUBu : ArithR64<0x00, 0x2f, "dsubu", sub, IIAlu>;
142 def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
143 def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>;
144 def DAND : LogicR64<0x24, "and", and>;
145 def DOR : LogicR64<0x25, "or", or>;
146 def DXOR : LogicR64<0x26, "xor", xor>;
147 def DNOR : LogicNOR64<0x00, 0x27, "nor">;
149 /// Shift Instructions
150 def DSLL : LogicR_shift_rotate_imm64<0x38, 0x00, "dsll", shl, immZExt5>;
151 def DSRL : LogicR_shift_rotate_imm64<0x3a, 0x00, "dsrl", srl, immZExt5>;
152 def DSRA : LogicR_shift_rotate_imm64<0x3b, 0x00, "dsra", sra, immZExt5>;
153 def DSLL32 : LogicR_shift_rotate_imm64<0x3c, 0x00, "dsll32", shl, imm32_63>;
154 def DSRL32 : LogicR_shift_rotate_imm64<0x3e, 0x00, "dsrl32", srl, imm32_63>;
155 def DSRA32 : LogicR_shift_rotate_imm64<0x3f, 0x00, "dsra32", sra, imm32_63>;
156 def DSLLV : LogicR_shift_rotate_reg64<0x24, 0x00, "dsllv", shl>;
157 def DSRLV : LogicR_shift_rotate_reg64<0x26, 0x00, "dsrlv", srl>;
158 def DSRAV : LogicR_shift_rotate_reg64<0x27, 0x00, "dsrav", sra>;
160 // Rotate Instructions
161 let Predicates = [HasMips64r2] in {
162 def DROTR : LogicR_shift_rotate_imm64<0x3a, 0x01, "drotr", rotr, immZExt5>;
163 def DROTR32 : LogicR_shift_rotate_imm64<0x3e, 0x01, "drotr32", rotr,
165 def DROTRV : LogicR_shift_rotate_reg64<0x16, 0x01, "drotrv", rotr>;
168 /// Load and Store Instructions
170 defm LB64 : LoadM64<0x20, "lb", sextloadi8>;
171 defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>;
172 defm LH64 : LoadM64<0x21, "lh", sextloadi16_a>;
173 defm LHu64 : LoadM64<0x25, "lhu", zextloadi16_a>;
174 defm LW64 : LoadM64<0x23, "lw", sextloadi32_a>;
175 defm LWu64 : LoadM64<0x27, "lwu", zextloadi32_a>;
176 defm SB64 : StoreM64<0x28, "sb", truncstorei8>;
177 defm SH64 : StoreM64<0x29, "sh", truncstorei16_a>;
178 defm SW64 : StoreM64<0x2b, "sw", truncstorei32_a>;
179 defm LD : LoadM64<0x37, "ld", load_a>;
180 defm SD : StoreM64<0x3f, "sd", store_a>;
183 defm ULH64 : LoadM64<0x21, "ulh", sextloadi16_u, 1>;
184 defm ULHu64 : LoadM64<0x25, "ulhu", zextloadi16_u, 1>;
185 defm ULW64 : LoadM64<0x23, "ulw", sextloadi32_u, 1>;
186 defm USH64 : StoreM64<0x29, "ush", truncstorei16_u, 1>;
187 defm USW64 : StoreM64<0x2b, "usw", truncstorei32_u, 1>;
188 defm ULD : LoadM64<0x37, "uld", load_u, 1>;
189 defm USD : StoreM64<0x3f, "usd", store_u, 1>;
191 /// Jump and Branch Instructions
192 def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>;
193 def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>;
194 def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>;
195 def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>;
196 def BLEZ64 : CBranchZero<0x07, 0, "blez", setle, CPU64Regs>;
197 def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>;
199 /// Multiply and Divide Instructions.
200 def DMULT : Mul64<0x1c, "dmult", IIImul>;
201 def DMULTu : Mul64<0x1d, "dmultu", IIImul>;
202 def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
203 def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>;
206 def MTHI64 : MoveToLOHI64<0x11, "mthi">;
208 def MTLO64 : MoveToLOHI64<0x13, "mtlo">;
211 def MFHI64 : MoveFromLOHI64<0x10, "mfhi">;
213 def MFLO64 : MoveFromLOHI64<0x12, "mflo">;
216 def DCLZ : CountLeading64<0x24, "dclz",
217 [(set CPU64Regs:$dst, (ctlz CPU64Regs:$src))]>;
218 def DCLO : CountLeading64<0x25, "dclo",
219 [(set CPU64Regs:$dst, (ctlz (not CPU64Regs:$src)))]>;
221 //===----------------------------------------------------------------------===//
222 // Arbitrary patterns that map to one or more instructions
223 //===----------------------------------------------------------------------===//
226 def : Pat<(i64 immSExt16:$in),
227 (DADDiu ZERO_64, imm:$in)>;
228 def : Pat<(i64 immZExt16:$in),
229 (DORi ZERO_64, imm:$in)>;
232 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>,
234 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>,
238 def : Pat<(i64 (MipsLo tglobaladdr:$in)), (DADDiu ZERO_64, tglobaladdr:$in)>;
241 def : Pat<(seteq CPU64Regs:$lhs, CPU64Regs:$rhs),
242 (SLTu64 (DXOR CPU64Regs:$lhs, CPU64Regs:$rhs), 1)>;
243 def : Pat<(setne CPU64Regs:$lhs, CPU64Regs:$rhs),
244 (SLTu64 ZERO_64, (DXOR CPU64Regs:$lhs, CPU64Regs:$rhs))>;
246 def : Pat<(setle CPU64Regs:$lhs, CPU64Regs:$rhs),
247 (XORi (SLT64 CPU64Regs:$rhs, CPU64Regs:$lhs), 1)>;
248 def : Pat<(setule CPU64Regs:$lhs, CPU64Regs:$rhs),
249 (XORi (SLTu64 CPU64Regs:$rhs, CPU64Regs:$lhs), 1)>;
251 def : Pat<(setgt CPU64Regs:$lhs, CPU64Regs:$rhs),
252 (SLT64 CPU64Regs:$rhs, CPU64Regs:$lhs)>;
253 def : Pat<(setugt CPU64Regs:$lhs, CPU64Regs:$rhs),
254 (SLTu64 CPU64Regs:$rhs, CPU64Regs:$lhs)>;
256 def : Pat<(setge CPU64Regs:$lhs, CPU64Regs:$rhs),
257 (XORi (SLT64 CPU64Regs:$lhs, CPU64Regs:$rhs), 1)>;
258 def : Pat<(setuge CPU64Regs:$lhs, CPU64Regs:$rhs),
259 (XORi (SLTu64 CPU64Regs:$lhs, CPU64Regs:$rhs), 1)>;
261 def : Pat<(setge CPU64Regs:$lhs, immSExt16:$rhs),
262 (XORi (SLTi64 CPU64Regs:$lhs, immSExt16:$rhs), 1)>;
263 def : Pat<(setuge CPU64Regs:$lhs, immSExt16:$rhs),
264 (XORi (SLTiu64 CPU64Regs:$lhs, immSExt16:$rhs), 1)>;