1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
18 // Instruction operand types
19 def shamt_64 : Operand<i64>;
22 def uimm16_64 : Operand<i64> {
23 let PrintMethod = "printUnsignedImm";
26 // Transformation Function - get Imm - 32.
27 def Subtract32 : SDNodeXForm<imm, [{
28 return getImm(N, (unsigned)N->getZExtValue() - 32);
31 // imm32_63 predicate - True if imm is in range [32, 63].
32 def imm32_63 : ImmLeaf<i32,
33 [{return (int32_t)Imm >= 32 && (int32_t)Imm < 64;}],
37 def immSExt32 : ImmLeaf<i64, [{return isInt<32>(Imm);}]>;
39 // Transformation Function - get the higher 16 bits.
40 def HIGHER : SDNodeXForm<imm, [{
41 return getImm(N, (N->getZExtValue() >> 32) & 0xFFFF);
44 // Transformation Function - get the highest 16 bits.
45 def HIGHEST : SDNodeXForm<imm, [{
46 return getImm(N, (N->getZExtValue() >> 48) & 0xFFFF);
49 //===----------------------------------------------------------------------===//
50 // Instructions specific format
51 //===----------------------------------------------------------------------===//
53 // 64-bit shift instructions.
54 class shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm,
56 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt,
59 class shift_rotate_imm64_32<bits<6> func, bits<5> isRotate, string instr_asm,
61 shift_rotate_imm<func, isRotate, instr_asm, OpNode, imm32_63, shamt,
64 // Jump and Link (Call)
65 let isCall=1, hasDelaySlot=1,
66 // All calls clobber the non-callee saved registers...
67 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
68 K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
69 class JumpLink64<bits<6> op, string instr_asm>:
70 FJ<op, (outs), (ins calltarget64:$target, variable_ops),
71 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
74 class JumpLinkReg64<bits<6> op, bits<6> func, string instr_asm>:
75 FR<op, func, (outs), (ins CPU64Regs:$rs, variable_ops),
76 !strconcat(instr_asm, "\t$rs"),
77 [(MipsJmpLink CPU64Regs:$rs)], IIBranch> {
83 class BranchLink64<string instr_asm>:
84 FI<0x1, (outs), (ins CPU64Regs:$rs, brtarget:$imm16, variable_ops),
85 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch>;
89 class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>:
90 Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
91 class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
92 Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
94 multiclass Atomic2Ops64<PatFrag Op, string Opstr> {
95 def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>, Requires<[NotN64]>;
96 def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>, Requires<[IsN64]>;
99 multiclass AtomicCmpSwap64<PatFrag Op, string Width> {
100 def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>, Requires<[NotN64]>;
101 def _P8 : AtomicCmpSwap<Op, Width, CPU64Regs, CPU64Regs>,
105 let usesCustomInserter = 1, Predicates = [HasMips64] in {
106 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">;
107 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">;
108 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64, "load_and_64">;
109 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64, "load_or_64">;
110 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64, "load_xor_64">;
111 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64, "load_nand_64">;
112 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64, "swap_64">;
113 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64, "64">;
116 //===----------------------------------------------------------------------===//
117 // Instruction definition
118 //===----------------------------------------------------------------------===//
120 /// Arithmetic Instructions (ALU Immediate)
121 def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16,
123 def DANDi : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>;
124 def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
125 def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
126 def ORi64 : ArithLogicI<0x0d, "ori", or, uimm16_64, immZExt16, CPU64Regs>;
127 def XORi64 : ArithLogicI<0x0e, "xori", xor, uimm16_64, immZExt16, CPU64Regs>;
128 def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>;
130 /// Arithmetic Instructions (3-Operand, R-Type)
131 def DADDu : ArithLogicR<0x00, 0x2d, "daddu", add, IIAlu, CPU64Regs, 1>;
132 def DSUBu : ArithLogicR<0x00, 0x2f, "dsubu", sub, IIAlu, CPU64Regs>;
133 def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
134 def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>;
135 def AND64 : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPU64Regs, 1>;
136 def OR64 : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPU64Regs, 1>;
137 def XOR64 : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPU64Regs, 1>;
138 def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>;
140 /// Shift Instructions
141 def DSLL : shift_rotate_imm64<0x38, 0x00, "dsll", shl>;
142 def DSRL : shift_rotate_imm64<0x3a, 0x00, "dsrl", srl>;
143 def DSRA : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>;
144 def DSLL32 : shift_rotate_imm64_32<0x3c, 0x00, "dsll32", shl>;
145 def DSRL32 : shift_rotate_imm64_32<0x3e, 0x00, "dsrl32", srl>;
146 def DSRA32 : shift_rotate_imm64_32<0x3f, 0x00, "dsra32", sra>;
147 def DSLLV : shift_rotate_reg<0x24, 0x00, "dsllv", shl, CPU64Regs>;
148 def DSRLV : shift_rotate_reg<0x26, 0x00, "dsrlv", srl, CPU64Regs>;
149 def DSRAV : shift_rotate_reg<0x27, 0x00, "dsrav", sra, CPU64Regs>;
151 // Rotate Instructions
152 let Predicates = [HasMips64r2] in {
153 def DROTR : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>;
154 def DROTR32 : shift_rotate_imm64_32<0x3e, 0x01, "drotr32", rotr>;
155 def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>;
158 /// Load and Store Instructions
160 defm LB64 : LoadM64<0x20, "lb", sextloadi8>;
161 defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>;
162 defm LH64 : LoadM64<0x21, "lh", sextloadi16_a>;
163 defm LHu64 : LoadM64<0x25, "lhu", zextloadi16_a>;
164 defm LW64 : LoadM64<0x23, "lw", sextloadi32_a>;
165 defm LWu64 : LoadM64<0x27, "lwu", zextloadi32_a>;
166 defm SB64 : StoreM64<0x28, "sb", truncstorei8>;
167 defm SH64 : StoreM64<0x29, "sh", truncstorei16_a>;
168 defm SW64 : StoreM64<0x2b, "sw", truncstorei32_a>;
169 defm LD : LoadM64<0x37, "ld", load_a>;
170 defm SD : StoreM64<0x3f, "sd", store_a>;
173 defm ULH64 : LoadM64<0x21, "ulh", sextloadi16_u, 1>;
174 defm ULHu64 : LoadM64<0x25, "ulhu", zextloadi16_u, 1>;
175 defm ULW64 : LoadM64<0x23, "ulw", sextloadi32_u, 1>;
176 defm USH64 : StoreM64<0x29, "ush", truncstorei16_u, 1>;
177 defm USW64 : StoreM64<0x2b, "usw", truncstorei32_u, 1>;
178 defm ULD : LoadM64<0x37, "uld", load_u, 1>;
179 defm USD : StoreM64<0x3f, "usd", store_u, 1>;
181 /// Load-linked, Store-conditional
182 def LLD : LLBase<0x34, "lld", CPU64Regs, mem>, Requires<[NotN64]>;
183 def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>, Requires<[IsN64]>;
184 def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>, Requires<[NotN64]>;
185 def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, Requires<[IsN64]>;
187 /// Jump and Branch Instructions
188 def JR64 : JumpFR<0x00, 0x08, "jr", CPU64Regs>;
189 def JAL64 : JumpLink64<0x03, "jal">;
190 def JALR64 : JumpLinkReg64<0x00, 0x09, "jalr">;
191 def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>;
192 def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>;
193 def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>;
194 def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>;
195 def BLEZ64 : CBranchZero<0x07, 0, "blez", setle, CPU64Regs>;
196 def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>;
198 /// Multiply and Divide Instructions.
199 def DMULT : Mult64<0x1c, "dmult", IIImul>;
200 def DMULTu : Mult64<0x1d, "dmultu", IIImul>;
201 def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
202 def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>;
204 def MTHI64 : MoveToLOHI<0x11, "mthi", CPU64Regs, [HI64]>;
205 def MTLO64 : MoveToLOHI<0x13, "mtlo", CPU64Regs, [LO64]>;
206 def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>;
207 def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>;
210 def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>;
211 def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>;
213 def LEA_ADDiu64 : EffectiveAddress<"addiu\t$rt, $addr", CPU64Regs, mem_ea_64>;
215 let Uses = [SP_64] in
216 def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>,
219 def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>;
221 def DEXT : ExtBase<3, "dext", CPU64Regs>;
222 def DINS : InsBase<7, "dins", CPU64Regs>;
224 def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
225 "dsll32\t$rd, $rt, 0", [], IIAlu>;
227 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
228 "sll\t$rd, $rt, 0", [], IIAlu>;
230 //===----------------------------------------------------------------------===//
231 // Arbitrary patterns that map to one or more instructions
232 //===----------------------------------------------------------------------===//
235 def : Pat<(i64 immSExt16:$in),
236 (DADDiu ZERO_64, imm:$in)>;
237 def : Pat<(i64 immZExt16:$in),
238 (ORi64 ZERO_64, imm:$in)>;
241 def : Pat<(i64 immSExt32:$imm),
242 (ORi64 (LUi64 (HI16 imm:$imm)), (LO16 imm:$imm))>;
244 // Arbitrary immediates
245 def : Pat<(i64 imm:$imm),
246 (ORi64 (DSLL (ORi64 (DSLL (ORi64 (LUi64 (HIGHEST imm:$imm)),
247 (HIGHER imm:$imm)), 16), (HI16 imm:$imm)), 16),
251 let Predicates = [NotN64] in {
252 def : Pat<(extloadi32_a addr:$a), (DSRL32 (DSLL32 (LW64 addr:$a), 0), 0)>;
253 def : Pat<(zextloadi32_u addr:$a), (DSRL32 (DSLL32 (ULW64 addr:$a), 0), 0)>;
255 let Predicates = [IsN64] in {
256 def : Pat<(extloadi32_a addr:$a), (DSRL32 (DSLL32 (LW64_P8 addr:$a), 0), 0)>;
257 def : Pat<(zextloadi32_u addr:$a),
258 (DSRL32 (DSLL32 (ULW64_P8 addr:$a), 0), 0)>;
262 def : Pat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
263 def : Pat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
264 def : Pat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
265 def : Pat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
266 def : Pat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
268 def : Pat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
269 def : Pat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
270 def : Pat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
271 def : Pat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
272 def : Pat<(MipsLo tglobaltlsaddr:$in), (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
274 def : Pat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
275 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
276 def : Pat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)),
277 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>;
278 def : Pat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)),
279 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
280 def : Pat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
281 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
282 def : Pat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)),
283 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>;
285 def : WrapperPat<tglobaladdr, DADDiu, GP_64>;
286 def : WrapperPat<tconstpool, DADDiu, GP_64>;
287 def : WrapperPat<texternalsym, DADDiu, GP_64>;
288 def : WrapperPat<tblockaddress, DADDiu, GP_64>;
289 def : WrapperPat<tjumptable, DADDiu, GP_64>;
290 def : WrapperPat<tglobaltlsaddr, DADDiu, GP_64>;
292 defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
296 defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
297 defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
298 defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
299 defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
300 defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
302 // select MipsDynAlloc
303 def : Pat<(MipsDynAlloc addr:$f), (DynAlloc64 addr:$f)>, Requires<[IsN64]>;
306 def : Pat<(i32 (trunc CPU64Regs:$src)),
307 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, Requires<[IsN64]>;
309 // 32-to-64-bit extension
310 def : Pat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
311 def : Pat<(i64 (zext CPURegs:$src)), (DSRL32 (DSLL64_32 CPURegs:$src), 0)>;