lib/Target/Mips/Mips64r6InstrInfo.td

   1 //=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips64r6 instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Notes about removals/changes from MIPS32r6:
  15 // Reencoded: dclo, dclz
  16 // Reencoded: lld, scd
  17 // Removed: daddi
  18
  19 //===----------------------------------------------------------------------===//
  20 //
  21 // Instruction Encodings
  22 //
  23 //===----------------------------------------------------------------------===//
  24
  25 class DALIGN_ENC  : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>;
  26 class DAUI_ENC    : DAUI_FM;
  27 class DAHI_ENC    : REGIMM_FM<OPCODE5_DAHI>;
  28 class DATI_ENC    : REGIMM_FM<OPCODE5_DATI>;
  29 class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>;
  30 class DDIV_ENC    : SPECIAL_3R_FM<0b00010, 0b011110>;
  31 class DDIVU_ENC   : SPECIAL_3R_FM<0b00010, 0b011111>;
  32 class DMOD_ENC    : SPECIAL_3R_FM<0b00011, 0b011110>;
  33 class DMODU_ENC   : SPECIAL_3R_FM<0b00011, 0b011111>;
  34 class DMUH_ENC    : SPECIAL_3R_FM<0b00011, 0b111000>;
  35 class DMUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b111001>;
  36 class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b111000>;
  37 class DMULU_ENC   : SPECIAL_3R_FM<0b00010, 0b111001>;
  38 class LDPC_ENC    : PCREL18_FM<OPCODE3_LDPC>;
  39
  40 //===----------------------------------------------------------------------===//
  41 //
  42 // Instruction Descriptions
  43 //
  44 //===----------------------------------------------------------------------===//
  45
  46 class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
  47   dag OutOperandList = (outs GPROpnd:$rs);
  48   dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
  49   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
  50   string Constraints = "$rs = $rt";
  51 }
  52
  53 class DALIGN_DESC  : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
  54 class DAHI_DESC    : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd>;
  55 class DATI_DESC    : AHI_ATI_DESC_BASE<"dati", GPR64Opnd>;
  56 class DAUI_DESC    : AUI_DESC_BASE<"daui", GPR64Opnd>;
  57 class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd>;
  58 class DDIV_DESC    : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, sdiv>;
  59 class DDIVU_DESC   : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
  60 class DMOD_DESC    : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, srem>;
  61 class DMODU_DESC   : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, urem>;
  62 class DMUH_DESC    : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, mulhs>;
  63 class DMUHU_DESC   : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, mulhu>;
  64 class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, mul>;
  65 class DMULU_DESC   : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd>;
  66 class LDPC_DESC    : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>;
  67
  68 class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
  69 class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
  70
  71 //===----------------------------------------------------------------------===//
  72 //
  73 // Instruction Definitions
  74 //
  75 //===----------------------------------------------------------------------===//
  76
  77 def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
  78 def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
  79 def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
  80 def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
  81 def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
  82 def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
  83 def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
  84 // def DLSA; // See MSA
  85 def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
  86 def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
  87 def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
  88 def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
  89 def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
  90 def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
  91 def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
  92 let DecoderNamespace = "Mips32r6_64r6_GP64" in {
  93   def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
  94   def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
  95 }
  96
  97 //===----------------------------------------------------------------------===//
  98 //
  99 // Patterns and Pseudo Instructions
 100 //
 101 //===----------------------------------------------------------------------===//
 102
 103 // i64 selects
 104 def : MipsPat<(select i64:$cond, i64:$t, i64:$f),
 105               (OR64 (SELNEZ64 i64:$t, i64:$cond),
 106                     (SELEQZ64 i64:$f, i64:$cond))>,
 107               ISA_MIPS64R6;
 108 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),
 109               (OR64 (SELNEZ64 i64:$t, i64:$cond),
 110                     (SELEQZ64 i64:$f, i64:$cond))>,
 111               ISA_MIPS64R6;
 112 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
 113               (OR64 (SELNEZ64 i64:$f, i64:$cond),
 114                     (SELEQZ64 i64:$t, i64:$cond))>,
 115               ISA_MIPS64R6;
 116 def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
 117               (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
 118                     (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
 119               ISA_MIPS64R6;
 120 def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
 121               (OR64 (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)),
 122                     (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
 123               ISA_MIPS64R6;
 124 def : MipsPat<
 125   (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
 126   (OR64 (SELNEZ64 i64:$t,
 127                   (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
 128                                  sub_32)),
 129         (SELEQZ64 i64:$f,
 130                   (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
 131                                  sub_32)))>,
 132   ISA_MIPS64R6;
 133 def : MipsPat<
 134   (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
 135   (OR64 (SELNEZ64 i64:$t,
 136                   (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
 137                                  sub_32)),
 138         (SELEQZ64 i64:$f,
 139                   (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
 140                                  sub_32)))>,
 141   ISA_MIPS64R6;
 142
 143 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),
 144               (SELNEZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
 145 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz),
 146               (SELEQZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
 147 def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),
 148               (SELEQZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
 149 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f),
 150               (SELNEZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
 151
 152 // i64 selects from an i32 comparison
 153 // One complicating factor here is that bits 32-63 of an i32 are undefined.
 154 // FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets.
 155 //        This would allow us to remove the sign-extensions here.
 156 def : MipsPat<(select i32:$cond, i64:$t, i64:$f),
 157               (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
 158                     (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
 159               ISA_MIPS64R6;
 160 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f),
 161               (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
 162                     (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
 163               ISA_MIPS64R6;
 164 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),
 165               (OR64 (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)),
 166                     (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)))>,
 167               ISA_MIPS64R6;
 168 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
 169               (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
 170                                                       immZExt16:$imm))),
 171                     (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
 172                                                       immZExt16:$imm))))>,
 173               ISA_MIPS64R6;
 174 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
 175               (OR64 (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
 176                                                       immZExt16:$imm))),
 177                     (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
 178                                                       immZExt16:$imm))))>,
 179               ISA_MIPS64R6;
 180
 181 def : MipsPat<(select i32:$cond, i64:$t, immz),
 182               (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
 183               ISA_MIPS64R6;
 184 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, immz),
 185               (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
 186               ISA_MIPS64R6;
 187 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, immz),
 188               (SELEQZ64 i64:$t, (SLL64_32 i32:$cond))>,
 189               ISA_MIPS64R6;
 190 def : MipsPat<(select i32:$cond, immz, i64:$f),
 191               (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
 192               ISA_MIPS64R6;
 193 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f),
 194               (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
 195               ISA_MIPS64R6;
 196 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),
 197               (SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,
 198               ISA_MIPS64R6;