lib/Target/Mips/Mips64r6InstrInfo.td

   1 //=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips64r6 instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Notes about removals/changes from MIPS32r6:
  15 // Reencoded: dclo, dclz
  16
  17 //===----------------------------------------------------------------------===//
  18 //
  19 // Instruction Encodings
  20 //
  21 //===----------------------------------------------------------------------===//
  22
  23 class DALIGN_ENC  : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>;
  24 class DAUI_ENC    : DAUI_FM;
  25 class DAHI_ENC    : REGIMM_FM<OPCODE5_DAHI>;
  26 class DATI_ENC    : REGIMM_FM<OPCODE5_DATI>;
  27 class DBITSWAP_ENC : SPECIAL3_2R_FM<OPCODE6_DBITSWAP>;
  28 class DCLO_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLO>;
  29 class DCLZ_R6_ENC : SPECIAL_2R_FM<OPCODE6_DCLZ>;
  30 class DDIV_ENC    : SPECIAL_3R_FM<0b00010, 0b011110>;
  31 class DDIVU_ENC   : SPECIAL_3R_FM<0b00010, 0b011111>;
  32 class DMOD_ENC    : SPECIAL_3R_FM<0b00011, 0b011110>;
  33 class DMODU_ENC   : SPECIAL_3R_FM<0b00011, 0b011111>;
  34 class DMUH_ENC    : SPECIAL_3R_FM<0b00011, 0b111000>;
  35 class DMUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b111001>;
  36 class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b111000>;
  37 class DMULU_ENC   : SPECIAL_3R_FM<0b00010, 0b111001>;
  38 class LDPC_ENC    : PCREL18_FM<OPCODE3_LDPC>;
  39 class LLD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_LLD>;
  40 class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>;
  41
  42 //===----------------------------------------------------------------------===//
  43 //
  44 // Instruction Descriptions
  45 //
  46 //===----------------------------------------------------------------------===//
  47
  48 class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
  49   dag OutOperandList = (outs GPROpnd:$rs);
  50   dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
  51   string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
  52   string Constraints = "$rs = $rt";
  53 }
  54
  55 class DALIGN_DESC  : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
  56 class DAHI_DESC    : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd>;
  57 class DATI_DESC    : AHI_ATI_DESC_BASE<"dati", GPR64Opnd>;
  58 class DAUI_DESC    : AUI_DESC_BASE<"daui", GPR64Opnd>;
  59 class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd>;
  60 class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd>;
  61 class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd>;
  62 class DDIV_DESC    : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, sdiv>;
  63 class DDIVU_DESC   : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
  64 class DMOD_DESC    : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, srem>;
  65 class DMODU_DESC   : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, urem>;
  66 class DMUH_DESC    : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, mulhs>;
  67 class DMUHU_DESC   : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, mulhu>;
  68 class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, mul>;
  69 class DMULU_DESC   : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd>;
  70 class LDPC_DESC    : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>;
  71 class LLD_R6_DESC   : LL_R6_DESC_BASE<"lld", GPR64Opnd>;
  72 class SCD_R6_DESC   : SC_R6_DESC_BASE<"scd", GPR64Opnd>;
  73 class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
  74 class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
  75
  76 //===----------------------------------------------------------------------===//
  77 //
  78 // Instruction Definitions
  79 //
  80 //===----------------------------------------------------------------------===//
  81
  82 def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
  83 def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
  84 def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
  85 def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
  86 def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
  87 def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
  88 def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
  89 def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
  90 def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
  91 // def DLSA; // See MSA
  92 def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
  93 def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
  94 def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
  95 def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
  96 def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
  97 def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
  98 def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
  99 def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6;
 100 def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
 101 let DecoderNamespace = "Mips32r6_64r6_GP64" in {
 102   def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
 103   def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
 104 }
 105
 106 //===----------------------------------------------------------------------===//
 107 //
 108 // Patterns and Pseudo Instructions
 109 //
 110 //===----------------------------------------------------------------------===//
 111
 112 // i64 selects
 113 def : MipsPat<(select i64:$cond, i64:$t, i64:$f),
 114               (OR64 (SELNEZ64 i64:$t, i64:$cond),
 115                     (SELEQZ64 i64:$f, i64:$cond))>,
 116               ISA_MIPS64R6;
 117 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),
 118               (OR64 (SELNEZ64 i64:$t, i64:$cond),
 119                     (SELEQZ64 i64:$f, i64:$cond))>,
 120               ISA_MIPS64R6;
 121 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
 122               (OR64 (SELNEZ64 i64:$f, i64:$cond),
 123                     (SELEQZ64 i64:$t, i64:$cond))>,
 124               ISA_MIPS64R6;
 125 def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
 126               (OR64 (SELNEZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)),
 127                     (SELEQZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
 128               ISA_MIPS64R6;
 129 def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
 130               (OR64 (SELNEZ64 i64:$f, (XORi64 i64:$cond, immZExt16_64:$imm)),
 131                     (SELEQZ64 i64:$t, (XORi64 i64:$cond, immZExt16_64:$imm)))>,
 132               ISA_MIPS64R6;
 133 def : MipsPat<
 134   (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
 135   (OR64 (SELNEZ64 i64:$t,
 136                   (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
 137                                  sub_32)),
 138         (SELEQZ64 i64:$f,
 139                   (SUBREG_TO_REG (i64 0), (SLTi64 i64:$cond, (Plus1 imm:$imm)),
 140                                  sub_32)))>,
 141   ISA_MIPS64R6;
 142 def : MipsPat<
 143   (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
 144   (OR64 (SELNEZ64 i64:$t,
 145                   (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
 146                                  sub_32)),
 147         (SELEQZ64 i64:$f,
 148                   (SUBREG_TO_REG (i64 0), (SLTiu64 i64:$cond, (Plus1 imm:$imm)),
 149                                  sub_32)))>,
 150   ISA_MIPS64R6;
 151
 152 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),
 153               (SELNEZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
 154 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz),
 155               (SELEQZ64 i64:$t, i64:$cond)>, ISA_MIPS64R6;
 156 def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),
 157               (SELEQZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
 158 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f),
 159               (SELNEZ64 i64:$f, i64:$cond)>, ISA_MIPS64R6;
 160
 161 // i64 selects from an i32 comparison
 162 // One complicating factor here is that bits 32-63 of an i32 are undefined.
 163 // FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets.
 164 //        This would allow us to remove the sign-extensions here.
 165 def : MipsPat<(select i32:$cond, i64:$t, i64:$f),
 166               (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
 167                     (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
 168               ISA_MIPS64R6;
 169 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, i64:$f),
 170               (OR64 (SELNEZ64 i64:$t, (SLL64_32 i32:$cond)),
 171                     (SELEQZ64 i64:$f, (SLL64_32 i32:$cond)))>,
 172               ISA_MIPS64R6;
 173 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, i64:$f),
 174               (OR64 (SELNEZ64 i64:$f, (SLL64_32 i32:$cond)),
 175                     (SELEQZ64 i64:$t, (SLL64_32 i32:$cond)))>,
 176               ISA_MIPS64R6;
 177 def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
 178               (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
 179                                                       immZExt16:$imm))),
 180                     (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
 181                                                       immZExt16:$imm))))>,
 182               ISA_MIPS64R6;
 183 def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f),
 184               (OR64 (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond,
 185                                                       immZExt16:$imm))),
 186                     (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond,
 187                                                       immZExt16:$imm))))>,
 188               ISA_MIPS64R6;
 189
 190 def : MipsPat<(select i32:$cond, i64:$t, immz),
 191               (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
 192               ISA_MIPS64R6;
 193 def : MipsPat<(select (i32 (setne i32:$cond, immz)), i64:$t, immz),
 194               (SELNEZ64 i64:$t, (SLL64_32 i32:$cond))>,
 195               ISA_MIPS64R6;
 196 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), i64:$t, immz),
 197               (SELEQZ64 i64:$t, (SLL64_32 i32:$cond))>,
 198               ISA_MIPS64R6;
 199 def : MipsPat<(select i32:$cond, immz, i64:$f),
 200               (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
 201               ISA_MIPS64R6;
 202 def : MipsPat<(select (i32 (setne i32:$cond, immz)), immz, i64:$f),
 203               (SELEQZ64 i64:$f, (SLL64_32 i32:$cond))>,
 204               ISA_MIPS64R6;
 205 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),
 206               (SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,
 207               ISA_MIPS64R6;