1 //=- Mips64r6InstrInfo.td - Mips64r6 Instruction Information -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64r6 instructions.
12 //===----------------------------------------------------------------------===//
14 // Notes about removals/changes from MIPS32r6:
15 // Reencoded: dclo, dclz
16 // Reencoded: lld, scd
18 // Removed: ddiv, ddivu, dmult, dmultu
20 // Removed: ldl, ldr, ldle, ldre, sdl, sdr, sdle, sdre
22 //===----------------------------------------------------------------------===//
24 // Instruction Encodings
26 //===----------------------------------------------------------------------===//
28 class DALIGN_ENC : SPECIAL3_DALIGN_FM<OPCODE6_DALIGN>;
29 class DAUI_ENC : DAUI_FM;
30 class DAHI_ENC : REGIMM_FM<OPCODE5_DAHI>;
31 class DATI_ENC : REGIMM_FM<OPCODE5_DATI>;
32 class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>;
33 class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>;
34 class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>;
35 class DMODU_ENC : SPECIAL_3R_FM<0b00011, 0b011111>;
36 class DMUH_ENC : SPECIAL_3R_FM<0b00011, 0b111000>;
37 class DMUHU_ENC : SPECIAL_3R_FM<0b00011, 0b111001>;
38 class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b111000>;
39 class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b111001>;
41 //===----------------------------------------------------------------------===//
43 // Instruction Descriptions
45 //===----------------------------------------------------------------------===//
47 class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
48 class DAHI_DESC : AUI_DESC_BASE<"dahi", GPR64Opnd>;
49 class DATI_DESC : AUI_DESC_BASE<"dati", GPR64Opnd>;
50 class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd>;
51 class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd>;
52 class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd>;
53 class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd>;
54 class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd>;
55 class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd>;
56 class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd>;
57 class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd>;
58 class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd>;
60 //===----------------------------------------------------------------------===//
62 // Instruction Definitions
64 //===----------------------------------------------------------------------===//
66 def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
67 def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
68 def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
69 def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
71 def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;
72 def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6;
73 // def DLSA; // See MSA
74 def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6;
75 def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6;
76 def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6;
77 def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
78 def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
79 def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;