1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-asm-printer"
16 #include "MipsAsmPrinter.h"
18 #include "MipsInstrInfo.h"
19 #include "InstPrinter/MipsInstPrinter.h"
20 #include "MCTargetDesc/MipsBaseInfo.h"
21 #include "llvm/BasicBlock.h"
22 #include "llvm/DebugInfo.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/ADT/SmallString.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/Twine.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/MC/MCStreamer.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSymbol.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/Mangler.h"
40 #include "llvm/Target/TargetData.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 #include "llvm/Target/TargetOptions.h"
46 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
47 MipsFI = MF.getInfo<MipsFunctionInfo>();
48 AsmPrinter::runOnMachineFunction(MF);
52 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
53 if (MI->isDebugValue()) {
55 raw_svector_ostream OS(Str);
57 PrintDebugValueComment(MI, OS);
61 MachineBasicBlock::const_instr_iterator I = MI;
62 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
66 MCInstLowering.Lower(I++, TmpInst0);
67 OutStreamer.EmitInstruction(TmpInst0);
68 } while ((I != E) && I->isInsideBundle());
71 //===----------------------------------------------------------------------===//
73 // Mips Asm Directives
75 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
76 // Describe the stack frame.
78 // -- Mask directives "(f)mask bitmask, offset"
79 // Tells the assembler which registers are saved and where.
80 // bitmask - contain a little endian bitset indicating which registers are
81 // saved on function prologue (e.g. with a 0x80000000 mask, the
82 // assembler knows the register 31 (RA) is saved at prologue.
83 // offset - the position before stack pointer subtraction indicating where
84 // the first saved register on prologue is located. (e.g. with a
86 // Consider the following function prologue:
89 // .mask 0xc0000000,-8
90 // addiu $sp, $sp, -48
94 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
95 // 30 (FP) are saved at prologue. As the save order on prologue is from
96 // left to right, RA is saved first. A -8 offset means that after the
97 // stack pointer subtration, the first register in the mask (RA) will be
98 // saved at address 48-8=40.
100 //===----------------------------------------------------------------------===//
102 //===----------------------------------------------------------------------===//
104 //===----------------------------------------------------------------------===//
106 // Create a bitmask with all callee saved registers for CPU or Floating Point
107 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
108 void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
109 // CPU and FPU Saved Registers Bitmasks
110 unsigned CPUBitmask = 0, FPUBitmask = 0;
111 int CPUTopSavedRegOff, FPUTopSavedRegOff;
113 // Set the CPU and FPU Bitmasks
114 const MachineFrameInfo *MFI = MF->getFrameInfo();
115 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
116 // size of stack area to which FP callee-saved regs are saved.
117 unsigned CPURegSize = Mips::CPURegsRegClass.getSize();
118 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
119 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
120 bool HasAFGR64Reg = false;
121 unsigned CSFPRegsSize = 0;
122 unsigned i, e = CSI.size();
125 for (i = 0; i != e; ++i) {
126 unsigned Reg = CSI[i].getReg();
127 if (Mips::CPURegsRegClass.contains(Reg))
130 unsigned RegNum = getMipsRegisterNumbering(Reg);
131 if (Mips::AFGR64RegClass.contains(Reg)) {
132 FPUBitmask |= (3 << RegNum);
133 CSFPRegsSize += AFGR64RegSize;
138 FPUBitmask |= (1 << RegNum);
139 CSFPRegsSize += FGR32RegSize;
143 for (; i != e; ++i) {
144 unsigned Reg = CSI[i].getReg();
145 unsigned RegNum = getMipsRegisterNumbering(Reg);
146 CPUBitmask |= (1 << RegNum);
149 // FP Regs are saved right below where the virtual frame pointer points to.
150 FPUTopSavedRegOff = FPUBitmask ?
151 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
153 // CPU Regs are saved below FP Regs.
154 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
157 O << "\t.mask \t"; printHex32(CPUBitmask, O);
158 O << ',' << CPUTopSavedRegOff << '\n';
161 O << "\t.fmask\t"; printHex32(FPUBitmask, O);
162 O << "," << FPUTopSavedRegOff << '\n';
165 // Print a 32 bit hex number with all numbers.
166 void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
168 for (int i = 7; i >= 0; i--)
169 O.write_hex((Value & (0xF << (i*4))) >> (i*4));
172 //===----------------------------------------------------------------------===//
173 // Frame and Set directives
174 //===----------------------------------------------------------------------===//
177 void MipsAsmPrinter::emitFrameDirective() {
178 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
180 unsigned stackReg = RI.getFrameRegister(*MF);
181 unsigned returnReg = RI.getRARegister();
182 unsigned stackSize = MF->getFrameInfo()->getStackSize();
184 if (OutStreamer.hasRawTextSupport())
185 OutStreamer.EmitRawText("\t.frame\t$" +
186 StringRef(MipsInstPrinter::getRegisterName(stackReg)).lower() +
187 "," + Twine(stackSize) + ",$" +
188 StringRef(MipsInstPrinter::getRegisterName(returnReg)).lower());
191 /// Emit Set directives.
192 const char *MipsAsmPrinter::getCurrentABIString() const {
193 switch (Subtarget->getTargetABI()) {
194 case MipsSubtarget::O32: return "abi32";
195 case MipsSubtarget::N32: return "abiN32";
196 case MipsSubtarget::N64: return "abi64";
197 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
198 default: llvm_unreachable("Unknown Mips ABI");;
202 void MipsAsmPrinter::EmitFunctionEntryLabel() {
203 if (OutStreamer.hasRawTextSupport()) {
204 if (Subtarget->inMips16Mode())
205 OutStreamer.EmitRawText(StringRef("\t.set\tmips16"));
207 OutStreamer.EmitRawText(StringRef("\t.set\tnomips16"));
208 // leave out until FSF available gas has micromips changes
209 // OutStreamer.EmitRawText(StringRef("\t.set\tnomicromips"));
210 OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName()));
212 OutStreamer.EmitLabel(CurrentFnSym);
215 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
216 /// the first basic block in the function.
217 void MipsAsmPrinter::EmitFunctionBodyStart() {
218 MCInstLowering.Initialize(Mang, &MF->getContext());
220 emitFrameDirective();
222 if (OutStreamer.hasRawTextSupport()) {
223 SmallString<128> Str;
224 raw_svector_ostream OS(Str);
225 printSavedRegsBitmask(OS);
226 OutStreamer.EmitRawText(OS.str());
228 OutStreamer.EmitRawText(StringRef("\t.set\tnoreorder"));
229 OutStreamer.EmitRawText(StringRef("\t.set\tnomacro"));
230 if (MipsFI->getEmitNOAT())
231 OutStreamer.EmitRawText(StringRef("\t.set\tnoat"));
235 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
236 /// the last basic block in the function.
237 void MipsAsmPrinter::EmitFunctionBodyEnd() {
238 // There are instruction for this macros, but they must
239 // always be at the function end, and we can't emit and
240 // break with BB logic.
241 if (OutStreamer.hasRawTextSupport()) {
242 if (MipsFI->getEmitNOAT())
243 OutStreamer.EmitRawText(StringRef("\t.set\tat"));
245 OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
246 OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
247 OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
251 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
252 /// exactly one predecessor and the control transfer mechanism between
253 /// the predecessor and this block is a fall-through.
254 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
256 // The predecessor has to be immediately before this block.
257 const MachineBasicBlock *Pred = *MBB->pred_begin();
259 // If the predecessor is a switch statement, assume a jump table
260 // implementation, so it is not a fall through.
261 if (const BasicBlock *bb = Pred->getBasicBlock())
262 if (isa<SwitchInst>(bb->getTerminator()))
265 // If this is a landing pad, it isn't a fall through. If it has no preds,
266 // then nothing falls through to it.
267 if (MBB->isLandingPad() || MBB->pred_empty())
270 // If there isn't exactly one predecessor, it can't be a fall through.
271 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
274 if (PI2 != MBB->pred_end())
277 // The predecessor has to be immediately before this block.
278 if (!Pred->isLayoutSuccessor(MBB))
281 // If the block is completely empty, then it definitely does fall through.
285 // Otherwise, check the last instruction.
286 // Check if the last terminator is an unconditional branch.
287 MachineBasicBlock::const_iterator I = Pred->end();
288 while (I != Pred->begin() && !(--I)->isTerminator()) ;
290 return !I->isBarrier();
293 // Print out an operand for an inline asm expression.
294 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
295 unsigned AsmVariant,const char *ExtraCode,
297 // Does this asm operand have a single letter operand modifier?
298 if (ExtraCode && ExtraCode[0]) {
299 if (ExtraCode[1] != 0) return true; // Unknown modifier.
301 const MachineOperand &MO = MI->getOperand(OpNum);
302 switch (ExtraCode[0]) {
304 // See if this is a generic print operand
305 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
306 case 'X': // hex const int
307 if ((MO.getType()) != MachineOperand::MO_Immediate)
309 O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
311 case 'x': // hex const int (low 16 bits)
312 if ((MO.getType()) != MachineOperand::MO_Immediate)
314 O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
316 case 'd': // decimal const int
317 if ((MO.getType()) != MachineOperand::MO_Immediate)
321 case 'm': // decimal const int minus 1
322 if ((MO.getType()) != MachineOperand::MO_Immediate)
324 O << MO.getImm() - 1;
327 // $0 if zero, regular printing otherwise
328 if (MO.getType() != MachineOperand::MO_Immediate)
330 int64_t Val = MO.getImm();
340 printOperand(MI, OpNum, O);
344 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
345 unsigned OpNum, unsigned AsmVariant,
346 const char *ExtraCode,
348 if (ExtraCode && ExtraCode[0])
349 return true; // Unknown modifier.
351 const MachineOperand &MO = MI->getOperand(OpNum);
352 assert(MO.isReg() && "unexpected inline asm memory operand");
353 O << "0($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
358 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
360 const MachineOperand &MO = MI->getOperand(opNum);
363 if (MO.getTargetFlags())
366 switch(MO.getTargetFlags()) {
367 case MipsII::MO_GPREL: O << "%gp_rel("; break;
368 case MipsII::MO_GOT_CALL: O << "%call16("; break;
369 case MipsII::MO_GOT: O << "%got("; break;
370 case MipsII::MO_ABS_HI: O << "%hi("; break;
371 case MipsII::MO_ABS_LO: O << "%lo("; break;
372 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
373 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
374 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
375 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
376 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
377 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
378 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
379 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
380 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
383 switch (MO.getType()) {
384 case MachineOperand::MO_Register:
386 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
389 case MachineOperand::MO_Immediate:
393 case MachineOperand::MO_MachineBasicBlock:
394 O << *MO.getMBB()->getSymbol();
397 case MachineOperand::MO_GlobalAddress:
398 O << *Mang->getSymbol(MO.getGlobal());
401 case MachineOperand::MO_BlockAddress: {
402 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
407 case MachineOperand::MO_ExternalSymbol:
408 O << *GetExternalSymbolSymbol(MO.getSymbolName());
411 case MachineOperand::MO_JumpTableIndex:
412 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
413 << '_' << MO.getIndex();
416 case MachineOperand::MO_ConstantPoolIndex:
417 O << MAI->getPrivateGlobalPrefix() << "CPI"
418 << getFunctionNumber() << "_" << MO.getIndex();
420 O << "+" << MO.getOffset();
424 llvm_unreachable("<unknown operand type>");
427 if (closeP) O << ")";
430 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
432 const MachineOperand &MO = MI->getOperand(opNum);
434 O << (unsigned short int)MO.getImm();
436 printOperand(MI, opNum, O);
439 void MipsAsmPrinter::
440 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
441 // Load/Store memory operands -- imm($reg)
442 // If PIC target the target is loaded as the
443 // pattern lw $25,%call16($28)
444 printOperand(MI, opNum+1, O);
446 printOperand(MI, opNum, O);
450 void MipsAsmPrinter::
451 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
452 // when using stack locations for not load/store instructions
453 // print the same way as all normal 3 operand instructions.
454 printOperand(MI, opNum, O);
456 printOperand(MI, opNum+1, O);
460 void MipsAsmPrinter::
461 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
462 const char *Modifier) {
463 const MachineOperand &MO = MI->getOperand(opNum);
464 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
467 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
468 // FIXME: Use SwitchSection.
470 // Tell the assembler which ABI we are using
471 if (OutStreamer.hasRawTextSupport())
472 OutStreamer.EmitRawText("\t.section .mdebug." +
473 Twine(getCurrentABIString()));
475 // TODO: handle O64 ABI
476 if (OutStreamer.hasRawTextSupport()) {
477 if (Subtarget->isABI_EABI()) {
478 if (Subtarget->isGP32bit())
479 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32"));
481 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64"));
485 // return to previous section
486 if (OutStreamer.hasRawTextSupport())
487 OutStreamer.EmitRawText(StringRef("\t.previous"));
491 MipsAsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
492 // Handles frame addresses emitted in MipsInstrInfo::emitFrameIndexDebugValue.
493 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
494 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
495 "Unexpected MachineOperand types");
496 return MachineLocation(MI->getOperand(0).getReg(),
497 MI->getOperand(1).getImm());
500 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
505 // Force static initialization.
506 extern "C" void LLVMInitializeMipsAsmPrinter() {
507 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
508 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
509 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
510 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);