1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-asm-printer"
16 #include "InstPrinter/MipsInstPrinter.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
19 #include "MipsAsmPrinter.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMCInstLower.h"
22 #include "MipsTargetStreamer.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/IR/BasicBlock.h"
32 #include "llvm/IR/DataLayout.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/Instructions.h"
35 #include "llvm/IR/Mangler.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCELFStreamer.h"
38 #include "llvm/MC/MCInst.h"
39 #include "llvm/MC/MCSymbol.h"
40 #include "llvm/Support/ELF.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include "llvm/Target/TargetLoweringObjectFile.h"
44 #include "llvm/Target/TargetOptions.h"
48 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() {
49 return static_cast<MipsTargetStreamer &>(*OutStreamer.getTargetStreamer());
52 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
53 // Initialize TargetLoweringObjectFile.
54 if (Subtarget->allowMixed16_32())
55 const_cast<TargetLoweringObjectFile&>(getObjFileLowering())
56 .Initialize(OutContext, TM);
57 MipsFI = MF.getInfo<MipsFunctionInfo>();
58 MCP = MF.getConstantPool();
59 AsmPrinter::runOnMachineFunction(MF);
63 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
64 MCOp = MCInstLowering.LowerOperand(MO);
65 return MCOp.isValid();
68 #include "MipsGenMCPseudoLowering.inc"
70 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
71 if (MI->isDebugValue()) {
73 raw_svector_ostream OS(Str);
75 PrintDebugValueComment(MI, OS);
79 // If we just ended a constant pool, mark it as such.
80 if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
81 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
82 InConstantPool = false;
84 if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
85 // CONSTPOOL_ENTRY - This instruction represents a floating
86 //constant pool in the function. The first operand is the ID#
87 // for this instruction, the second is the index into the
88 // MachineConstantPool that this is, the third is the size in
89 // bytes of this constant pool entry.
90 // The required alignment is specified on the basic block holding this MI.
92 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
93 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
95 // If this is the first entry of the pool, mark it.
96 if (!InConstantPool) {
97 OutStreamer.EmitDataRegion(MCDR_DataRegion);
98 InConstantPool = true;
101 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
103 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
104 if (MCPE.isMachineConstantPoolEntry())
105 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
107 EmitGlobalConstant(MCPE.Val.ConstVal);
112 MachineBasicBlock::const_instr_iterator I = MI;
113 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
116 // Do any auto-generated pseudo lowerings.
117 if (emitPseudoExpansionLowering(OutStreamer, &*I))
120 // The inMips16Mode() test is not permanent.
121 // Some instructions are marked as pseudo right now which
122 // would make the test fail for the wrong reason but
123 // that will be fixed soon. We need this here because we are
124 // removing another test for this situation downstream in the
127 if (I->isPseudo() && !Subtarget->inMips16Mode())
128 llvm_unreachable("Pseudo opcode found in EmitInstruction()");
131 MCInstLowering.Lower(I, TmpInst0);
132 OutStreamer.EmitInstruction(TmpInst0);
133 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
136 //===----------------------------------------------------------------------===//
138 // Mips Asm Directives
140 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
141 // Describe the stack frame.
143 // -- Mask directives "(f)mask bitmask, offset"
144 // Tells the assembler which registers are saved and where.
145 // bitmask - contain a little endian bitset indicating which registers are
146 // saved on function prologue (e.g. with a 0x80000000 mask, the
147 // assembler knows the register 31 (RA) is saved at prologue.
148 // offset - the position before stack pointer subtraction indicating where
149 // the first saved register on prologue is located. (e.g. with a
151 // Consider the following function prologue:
154 // .mask 0xc0000000,-8
155 // addiu $sp, $sp, -48
159 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
160 // 30 (FP) are saved at prologue. As the save order on prologue is from
161 // left to right, RA is saved first. A -8 offset means that after the
162 // stack pointer subtration, the first register in the mask (RA) will be
163 // saved at address 48-8=40.
165 //===----------------------------------------------------------------------===//
167 //===----------------------------------------------------------------------===//
169 //===----------------------------------------------------------------------===//
171 // Create a bitmask with all callee saved registers for CPU or Floating Point
172 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
173 void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
174 // CPU and FPU Saved Registers Bitmasks
175 unsigned CPUBitmask = 0, FPUBitmask = 0;
176 int CPUTopSavedRegOff, FPUTopSavedRegOff;
178 // Set the CPU and FPU Bitmasks
179 const MachineFrameInfo *MFI = MF->getFrameInfo();
180 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
181 // size of stack area to which FP callee-saved regs are saved.
182 unsigned CPURegSize = Mips::GPR32RegClass.getSize();
183 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
184 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
185 bool HasAFGR64Reg = false;
186 unsigned CSFPRegsSize = 0;
187 unsigned i, e = CSI.size();
190 for (i = 0; i != e; ++i) {
191 unsigned Reg = CSI[i].getReg();
192 if (Mips::GPR32RegClass.contains(Reg))
195 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
196 if (Mips::AFGR64RegClass.contains(Reg)) {
197 FPUBitmask |= (3 << RegNum);
198 CSFPRegsSize += AFGR64RegSize;
203 FPUBitmask |= (1 << RegNum);
204 CSFPRegsSize += FGR32RegSize;
208 for (; i != e; ++i) {
209 unsigned Reg = CSI[i].getReg();
210 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
211 CPUBitmask |= (1 << RegNum);
214 // FP Regs are saved right below where the virtual frame pointer points to.
215 FPUTopSavedRegOff = FPUBitmask ?
216 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
218 // CPU Regs are saved below FP Regs.
219 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
222 O << "\t.mask \t"; printHex32(CPUBitmask, O);
223 O << ',' << CPUTopSavedRegOff << '\n';
226 O << "\t.fmask\t"; printHex32(FPUBitmask, O);
227 O << "," << FPUTopSavedRegOff << '\n';
230 // Print a 32 bit hex number with all numbers.
231 void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
233 for (int i = 7; i >= 0; i--)
234 O.write_hex((Value & (0xF << (i*4))) >> (i*4));
237 //===----------------------------------------------------------------------===//
238 // Frame and Set directives
239 //===----------------------------------------------------------------------===//
242 void MipsAsmPrinter::emitFrameDirective() {
243 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
245 unsigned stackReg = RI.getFrameRegister(*MF);
246 unsigned returnReg = RI.getRARegister();
247 unsigned stackSize = MF->getFrameInfo()->getStackSize();
249 if (OutStreamer.hasRawTextSupport())
250 OutStreamer.EmitRawText("\t.frame\t$" +
251 StringRef(MipsInstPrinter::getRegisterName(stackReg)).lower() +
252 "," + Twine(stackSize) + ",$" +
253 StringRef(MipsInstPrinter::getRegisterName(returnReg)).lower());
256 /// Emit Set directives.
257 const char *MipsAsmPrinter::getCurrentABIString() const {
258 switch (Subtarget->getTargetABI()) {
259 case MipsSubtarget::O32: return "abi32";
260 case MipsSubtarget::N32: return "abiN32";
261 case MipsSubtarget::N64: return "abi64";
262 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
263 default: llvm_unreachable("Unknown Mips ABI");
267 void MipsAsmPrinter::EmitFunctionEntryLabel() {
268 MipsTargetStreamer &TS = getTargetStreamer();
269 if (Subtarget->inMicroMipsMode())
270 TS.emitDirectiveSetMicroMips();
271 // leave out until FSF available gas has micromips changes
273 // TS.emitDirectiveSetNoMicroMips();
275 if (Subtarget->inMips16Mode())
276 TS.emitDirectiveSetMips16();
278 TS.emitDirectiveSetNoMips16();
280 TS.emitDirectiveEnt(*CurrentFnSym);
281 OutStreamer.EmitLabel(CurrentFnSym);
284 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
285 /// the first basic block in the function.
286 void MipsAsmPrinter::EmitFunctionBodyStart() {
287 MCInstLowering.Initialize(&MF->getContext());
289 bool IsNakedFunction =
291 getAttributes().hasAttribute(AttributeSet::FunctionIndex,
293 if (!IsNakedFunction)
294 emitFrameDirective();
296 if (OutStreamer.hasRawTextSupport()) {
297 SmallString<128> Str;
298 raw_svector_ostream OS(Str);
299 if (!IsNakedFunction)
300 printSavedRegsBitmask(OS);
301 OutStreamer.EmitRawText(OS.str());
302 if (!Subtarget->inMips16Mode()) {
303 OutStreamer.EmitRawText(StringRef("\t.set\tnoreorder"));
304 OutStreamer.EmitRawText(StringRef("\t.set\tnomacro"));
305 OutStreamer.EmitRawText(StringRef("\t.set\tnoat"));
310 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
311 /// the last basic block in the function.
312 void MipsAsmPrinter::EmitFunctionBodyEnd() {
313 // There are instruction for this macros, but they must
314 // always be at the function end, and we can't emit and
315 // break with BB logic.
316 if (OutStreamer.hasRawTextSupport()) {
317 if (!Subtarget->inMips16Mode()) {
318 OutStreamer.EmitRawText(StringRef("\t.set\tat"));
319 OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
320 OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
322 OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
324 // Make sure to terminate any constant pools that were at the end
328 InConstantPool = false;
329 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
332 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
333 /// exactly one predecessor and the control transfer mechanism between
334 /// the predecessor and this block is a fall-through.
335 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
337 // The predecessor has to be immediately before this block.
338 const MachineBasicBlock *Pred = *MBB->pred_begin();
340 // If the predecessor is a switch statement, assume a jump table
341 // implementation, so it is not a fall through.
342 if (const BasicBlock *bb = Pred->getBasicBlock())
343 if (isa<SwitchInst>(bb->getTerminator()))
346 // If this is a landing pad, it isn't a fall through. If it has no preds,
347 // then nothing falls through to it.
348 if (MBB->isLandingPad() || MBB->pred_empty())
351 // If there isn't exactly one predecessor, it can't be a fall through.
352 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
355 if (PI2 != MBB->pred_end())
358 // The predecessor has to be immediately before this block.
359 if (!Pred->isLayoutSuccessor(MBB))
362 // If the block is completely empty, then it definitely does fall through.
366 // Otherwise, check the last instruction.
367 // Check if the last terminator is an unconditional branch.
368 MachineBasicBlock::const_iterator I = Pred->end();
369 while (I != Pred->begin() && !(--I)->isTerminator()) ;
371 return !I->isBarrier();
374 // Print out an operand for an inline asm expression.
375 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
376 unsigned AsmVariant,const char *ExtraCode,
378 // Does this asm operand have a single letter operand modifier?
379 if (ExtraCode && ExtraCode[0]) {
380 if (ExtraCode[1] != 0) return true; // Unknown modifier.
382 const MachineOperand &MO = MI->getOperand(OpNum);
383 switch (ExtraCode[0]) {
385 // See if this is a generic print operand
386 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
387 case 'X': // hex const int
388 if ((MO.getType()) != MachineOperand::MO_Immediate)
390 O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
392 case 'x': // hex const int (low 16 bits)
393 if ((MO.getType()) != MachineOperand::MO_Immediate)
395 O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
397 case 'd': // decimal const int
398 if ((MO.getType()) != MachineOperand::MO_Immediate)
402 case 'm': // decimal const int minus 1
403 if ((MO.getType()) != MachineOperand::MO_Immediate)
405 O << MO.getImm() - 1;
408 // $0 if zero, regular printing otherwise
409 if (MO.getType() != MachineOperand::MO_Immediate)
411 int64_t Val = MO.getImm();
418 case 'D': // Second part of a double word register operand
419 case 'L': // Low order register of a double word register operand
420 case 'M': // High order register of a double word register operand
424 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
425 if (!FlagsOP.isImm())
427 unsigned Flags = FlagsOP.getImm();
428 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
429 // Number of registers represented by this operand. We are looking
430 // for 2 for 32 bit mode and 1 for 64 bit mode.
432 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
433 unsigned Reg = MO.getReg();
434 O << '$' << MipsInstPrinter::getRegisterName(Reg);
440 unsigned RegOp = OpNum;
441 if (!Subtarget->isGP64bit()){
442 // Endianess reverses which register holds the high or low value
444 switch(ExtraCode[0]) {
446 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
449 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
451 case 'D': // Always the second part
454 if (RegOp >= MI->getNumOperands())
456 const MachineOperand &MO = MI->getOperand(RegOp);
459 unsigned Reg = MO.getReg();
460 O << '$' << MipsInstPrinter::getRegisterName(Reg);
465 // Print MSA registers for the 'f' constraint
466 // In LLVM, the 'w' modifier doesn't need to do anything.
467 // We can just call printOperand as normal.
472 printOperand(MI, OpNum, O);
476 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
477 unsigned OpNum, unsigned AsmVariant,
478 const char *ExtraCode,
481 // Currently we are expecting either no ExtraCode or 'D'
483 if (ExtraCode[0] == 'D')
486 return true; // Unknown modifier.
489 const MachineOperand &MO = MI->getOperand(OpNum);
490 assert(MO.isReg() && "unexpected inline asm memory operand");
491 O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
496 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
498 const DataLayout *DL = TM.getDataLayout();
499 const MachineOperand &MO = MI->getOperand(opNum);
502 if (MO.getTargetFlags())
505 switch(MO.getTargetFlags()) {
506 case MipsII::MO_GPREL: O << "%gp_rel("; break;
507 case MipsII::MO_GOT_CALL: O << "%call16("; break;
508 case MipsII::MO_GOT: O << "%got("; break;
509 case MipsII::MO_ABS_HI: O << "%hi("; break;
510 case MipsII::MO_ABS_LO: O << "%lo("; break;
511 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
512 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
513 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
514 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
515 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
516 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
517 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
518 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
519 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
522 switch (MO.getType()) {
523 case MachineOperand::MO_Register:
525 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
528 case MachineOperand::MO_Immediate:
532 case MachineOperand::MO_MachineBasicBlock:
533 O << *MO.getMBB()->getSymbol();
536 case MachineOperand::MO_GlobalAddress:
537 O << *getSymbol(MO.getGlobal());
540 case MachineOperand::MO_BlockAddress: {
541 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
546 case MachineOperand::MO_ConstantPoolIndex:
547 O << DL->getPrivateGlobalPrefix() << "CPI"
548 << getFunctionNumber() << "_" << MO.getIndex();
550 O << "+" << MO.getOffset();
554 llvm_unreachable("<unknown operand type>");
557 if (closeP) O << ")";
560 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
562 const MachineOperand &MO = MI->getOperand(opNum);
564 O << (unsigned short int)MO.getImm();
566 printOperand(MI, opNum, O);
569 void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum,
571 const MachineOperand &MO = MI->getOperand(opNum);
573 O << (unsigned short int)(unsigned char)MO.getImm();
575 printOperand(MI, opNum, O);
578 void MipsAsmPrinter::
579 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
580 // Load/Store memory operands -- imm($reg)
581 // If PIC target the target is loaded as the
582 // pattern lw $25,%call16($28)
583 printOperand(MI, opNum+1, O);
585 printOperand(MI, opNum, O);
589 void MipsAsmPrinter::
590 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
591 // when using stack locations for not load/store instructions
592 // print the same way as all normal 3 operand instructions.
593 printOperand(MI, opNum, O);
595 printOperand(MI, opNum+1, O);
599 void MipsAsmPrinter::
600 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
601 const char *Modifier) {
602 const MachineOperand &MO = MI->getOperand(opNum);
603 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
606 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
607 // FIXME: Use SwitchSection.
609 // TODO: Need to add -mabicalls and -mno-abicalls flags.
610 // Currently we assume that -mabicalls is the default.
611 getTargetStreamer().emitDirectiveAbiCalls();
612 Reloc::Model RM = Subtarget->getRelocationModel();
613 if (RM == Reloc::Static && !Subtarget->hasMips64())
614 getTargetStreamer().emitDirectiveOptionPic0();
616 // Tell the assembler which ABI we are using
617 if (OutStreamer.hasRawTextSupport())
618 OutStreamer.EmitRawText("\t.section .mdebug." +
619 Twine(getCurrentABIString()));
621 // TODO: handle O64 ABI
622 if (OutStreamer.hasRawTextSupport()) {
623 if (Subtarget->isABI_EABI()) {
624 if (Subtarget->isGP32bit())
625 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32"));
627 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64"));
631 // return to previous section
632 if (OutStreamer.hasRawTextSupport())
633 OutStreamer.EmitRawText(StringRef("\t.previous"));
637 static void emitELFHeaderFlagsCG(MipsTargetStreamer &TargetStreamer,
638 const MipsSubtarget &Subtarget) {
639 // Update e_header flags
642 // TODO: Need to add -mabicalls and -mno-abicalls flags.
643 // Currently we assume that -mabicalls is the default.
644 EFlags |= ELF::EF_MIPS_CPIC;
646 if (Subtarget.inMips16Mode())
647 EFlags |= ELF::EF_MIPS_ARCH_ASE_M16;
649 EFlags |= ELF::EF_MIPS_NOREORDER;
652 if (Subtarget.hasMips64r2())
653 EFlags |= ELF::EF_MIPS_ARCH_64R2;
654 else if (Subtarget.hasMips64())
655 EFlags |= ELF::EF_MIPS_ARCH_64;
656 else if (Subtarget.hasMips32r2())
657 EFlags |= ELF::EF_MIPS_ARCH_32R2;
659 EFlags |= ELF::EF_MIPS_ARCH_32;
661 if (Subtarget.inMicroMipsMode())
662 EFlags |= ELF::EF_MIPS_MICROMIPS;
665 if (Subtarget.isABI_O32())
666 EFlags |= ELF::EF_MIPS_ABI_O32;
669 Reloc::Model RM = Subtarget.getRelocationModel();
670 if (RM == Reloc::PIC_ || RM == Reloc::Default)
671 EFlags |= ELF::EF_MIPS_PIC;
672 else if (RM == Reloc::Static)
673 ; // Do nothing for Reloc::Static
675 llvm_unreachable("Unsupported relocation model for e_flags");
677 TargetStreamer.emitMipsHackELFFlags(EFlags);
680 void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
681 // Emit Mips ELF register info
682 Subtarget->getMReginfo().emitMipsReginfoSectionCG(
683 OutStreamer, getObjFileLowering(), *Subtarget);
684 emitELFHeaderFlagsCG(getTargetStreamer(), *Subtarget);
687 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
692 // Force static initialization.
693 extern "C" void LLVMInitializeMipsAsmPrinter() {
694 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
695 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
696 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
697 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);