1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-asm-printer"
16 #include "InstPrinter/MipsInstPrinter.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MCTargetDesc/MipsMCNaCl.h"
20 #include "MipsAsmPrinter.h"
21 #include "MipsInstrInfo.h"
22 #include "MipsMCInstLower.h"
23 #include "MipsTargetStreamer.h"
24 #include "llvm/ADT/SmallString.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/Twine.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/IR/BasicBlock.h"
34 #include "llvm/IR/DataLayout.h"
35 #include "llvm/IR/InlineAsm.h"
36 #include "llvm/IR/Instructions.h"
37 #include "llvm/IR/Mangler.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCELFStreamer.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCInst.h"
43 #include "llvm/MC/MCSection.h"
44 #include "llvm/MC/MCSectionELF.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/ELF.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetLoweringObjectFile.h"
50 #include "llvm/Target/TargetOptions.h"
55 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() {
56 return static_cast<MipsTargetStreamer &>(*OutStreamer.getTargetStreamer());
59 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
60 // Initialize TargetLoweringObjectFile.
61 if (Subtarget->allowMixed16_32())
62 const_cast<TargetLoweringObjectFile&>(getObjFileLowering())
63 .Initialize(OutContext, TM);
64 MipsFI = MF.getInfo<MipsFunctionInfo>();
65 if (Subtarget->inMips16Mode())
68 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
69 it = MipsFI->StubsNeeded.begin();
70 it != MipsFI->StubsNeeded.end(); ++it) {
71 const char *Symbol = it->first;
72 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
73 if (StubsNeeded.find(Symbol) == StubsNeeded.end())
74 StubsNeeded[Symbol] = Signature;
76 MCP = MF.getConstantPool();
78 // In NaCl, all indirect jump targets must be aligned to bundle size.
79 if (Subtarget->isTargetNaCl())
80 NaClAlignIndirectJumpTargets(MF);
82 AsmPrinter::runOnMachineFunction(MF);
86 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
87 MCOp = MCInstLowering.LowerOperand(MO);
88 return MCOp.isValid();
91 #include "MipsGenMCPseudoLowering.inc"
93 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
94 if (MI->isDebugValue()) {
96 raw_svector_ostream OS(Str);
98 PrintDebugValueComment(MI, OS);
102 // If we just ended a constant pool, mark it as such.
103 if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
104 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
105 InConstantPool = false;
107 if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
108 // CONSTPOOL_ENTRY - This instruction represents a floating
109 //constant pool in the function. The first operand is the ID#
110 // for this instruction, the second is the index into the
111 // MachineConstantPool that this is, the third is the size in
112 // bytes of this constant pool entry.
113 // The required alignment is specified on the basic block holding this MI.
115 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
116 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
118 // If this is the first entry of the pool, mark it.
119 if (!InConstantPool) {
120 OutStreamer.EmitDataRegion(MCDR_DataRegion);
121 InConstantPool = true;
124 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
126 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
127 if (MCPE.isMachineConstantPoolEntry())
128 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
130 EmitGlobalConstant(MCPE.Val.ConstVal);
135 MachineBasicBlock::const_instr_iterator I = MI;
136 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
139 // Do any auto-generated pseudo lowerings.
140 if (emitPseudoExpansionLowering(OutStreamer, &*I))
143 // The inMips16Mode() test is not permanent.
144 // Some instructions are marked as pseudo right now which
145 // would make the test fail for the wrong reason but
146 // that will be fixed soon. We need this here because we are
147 // removing another test for this situation downstream in the
150 if (I->isPseudo() && !Subtarget->inMips16Mode())
151 llvm_unreachable("Pseudo opcode found in EmitInstruction()");
154 MCInstLowering.Lower(I, TmpInst0);
155 EmitToStreamer(OutStreamer, TmpInst0);
156 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
159 //===----------------------------------------------------------------------===//
161 // Mips Asm Directives
163 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
164 // Describe the stack frame.
166 // -- Mask directives "(f)mask bitmask, offset"
167 // Tells the assembler which registers are saved and where.
168 // bitmask - contain a little endian bitset indicating which registers are
169 // saved on function prologue (e.g. with a 0x80000000 mask, the
170 // assembler knows the register 31 (RA) is saved at prologue.
171 // offset - the position before stack pointer subtraction indicating where
172 // the first saved register on prologue is located. (e.g. with a
174 // Consider the following function prologue:
177 // .mask 0xc0000000,-8
178 // addiu $sp, $sp, -48
182 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
183 // 30 (FP) are saved at prologue. As the save order on prologue is from
184 // left to right, RA is saved first. A -8 offset means that after the
185 // stack pointer subtration, the first register in the mask (RA) will be
186 // saved at address 48-8=40.
188 //===----------------------------------------------------------------------===//
190 //===----------------------------------------------------------------------===//
192 //===----------------------------------------------------------------------===//
194 // Create a bitmask with all callee saved registers for CPU or Floating Point
195 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
196 void MipsAsmPrinter::printSavedRegsBitmask() {
197 // CPU and FPU Saved Registers Bitmasks
198 unsigned CPUBitmask = 0, FPUBitmask = 0;
199 int CPUTopSavedRegOff, FPUTopSavedRegOff;
201 // Set the CPU and FPU Bitmasks
202 const MachineFrameInfo *MFI = MF->getFrameInfo();
203 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
204 // size of stack area to which FP callee-saved regs are saved.
205 unsigned CPURegSize = Mips::GPR32RegClass.getSize();
206 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
207 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
208 bool HasAFGR64Reg = false;
209 unsigned CSFPRegsSize = 0;
210 unsigned i, e = CSI.size();
213 for (i = 0; i != e; ++i) {
214 unsigned Reg = CSI[i].getReg();
215 if (Mips::GPR32RegClass.contains(Reg))
218 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
219 if (Mips::AFGR64RegClass.contains(Reg)) {
220 FPUBitmask |= (3 << RegNum);
221 CSFPRegsSize += AFGR64RegSize;
226 FPUBitmask |= (1 << RegNum);
227 CSFPRegsSize += FGR32RegSize;
231 for (; i != e; ++i) {
232 unsigned Reg = CSI[i].getReg();
233 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
234 CPUBitmask |= (1 << RegNum);
237 // FP Regs are saved right below where the virtual frame pointer points to.
238 FPUTopSavedRegOff = FPUBitmask ?
239 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
241 // CPU Regs are saved below FP Regs.
242 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
244 MipsTargetStreamer &TS = getTargetStreamer();
246 TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
249 TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
252 //===----------------------------------------------------------------------===//
253 // Frame and Set directives
254 //===----------------------------------------------------------------------===//
257 void MipsAsmPrinter::emitFrameDirective() {
258 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
260 unsigned stackReg = RI.getFrameRegister(*MF);
261 unsigned returnReg = RI.getRARegister();
262 unsigned stackSize = MF->getFrameInfo()->getStackSize();
264 getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
267 /// Emit Set directives.
268 const char *MipsAsmPrinter::getCurrentABIString() const {
269 switch (Subtarget->getTargetABI()) {
270 case MipsSubtarget::O32: return "abi32";
271 case MipsSubtarget::N32: return "abiN32";
272 case MipsSubtarget::N64: return "abi64";
273 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
274 default: llvm_unreachable("Unknown Mips ABI");
278 void MipsAsmPrinter::EmitFunctionEntryLabel() {
279 MipsTargetStreamer &TS = getTargetStreamer();
281 // NaCl sandboxing requires that indirect call instructions are masked.
282 // This means that function entry points should be bundle-aligned.
283 if (Subtarget->isTargetNaCl())
284 EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN));
286 if (Subtarget->inMicroMipsMode())
287 TS.emitDirectiveSetMicroMips();
289 TS.emitDirectiveSetNoMicroMips();
291 if (Subtarget->inMips16Mode())
292 TS.emitDirectiveSetMips16();
294 TS.emitDirectiveSetNoMips16();
296 TS.emitDirectiveEnt(*CurrentFnSym);
297 OutStreamer.EmitLabel(CurrentFnSym);
300 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
301 /// the first basic block in the function.
302 void MipsAsmPrinter::EmitFunctionBodyStart() {
303 MipsTargetStreamer &TS = getTargetStreamer();
305 MCInstLowering.Initialize(&MF->getContext());
307 bool IsNakedFunction =
309 getAttributes().hasAttribute(AttributeSet::FunctionIndex,
311 if (!IsNakedFunction)
312 emitFrameDirective();
314 if (!IsNakedFunction)
315 printSavedRegsBitmask();
317 if (!Subtarget->inMips16Mode()) {
318 TS.emitDirectiveSetNoReorder();
319 TS.emitDirectiveSetNoMacro();
320 TS.emitDirectiveSetNoAt();
324 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
325 /// the last basic block in the function.
326 void MipsAsmPrinter::EmitFunctionBodyEnd() {
327 MipsTargetStreamer &TS = getTargetStreamer();
329 // There are instruction for this macros, but they must
330 // always be at the function end, and we can't emit and
331 // break with BB logic.
332 if (!Subtarget->inMips16Mode()) {
333 TS.emitDirectiveSetAt();
334 TS.emitDirectiveSetMacro();
335 TS.emitDirectiveSetReorder();
337 TS.emitDirectiveEnd(CurrentFnSym->getName());
338 // Make sure to terminate any constant pools that were at the end
342 InConstantPool = false;
343 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
346 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
347 /// exactly one predecessor and the control transfer mechanism between
348 /// the predecessor and this block is a fall-through.
349 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
351 // The predecessor has to be immediately before this block.
352 const MachineBasicBlock *Pred = *MBB->pred_begin();
354 // If the predecessor is a switch statement, assume a jump table
355 // implementation, so it is not a fall through.
356 if (const BasicBlock *bb = Pred->getBasicBlock())
357 if (isa<SwitchInst>(bb->getTerminator()))
360 // If this is a landing pad, it isn't a fall through. If it has no preds,
361 // then nothing falls through to it.
362 if (MBB->isLandingPad() || MBB->pred_empty())
365 // If there isn't exactly one predecessor, it can't be a fall through.
366 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
369 if (PI2 != MBB->pred_end())
372 // The predecessor has to be immediately before this block.
373 if (!Pred->isLayoutSuccessor(MBB))
376 // If the block is completely empty, then it definitely does fall through.
380 // Otherwise, check the last instruction.
381 // Check if the last terminator is an unconditional branch.
382 MachineBasicBlock::const_iterator I = Pred->end();
383 while (I != Pred->begin() && !(--I)->isTerminator()) ;
385 return !I->isBarrier();
388 // Print out an operand for an inline asm expression.
389 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
390 unsigned AsmVariant,const char *ExtraCode,
392 // Does this asm operand have a single letter operand modifier?
393 if (ExtraCode && ExtraCode[0]) {
394 if (ExtraCode[1] != 0) return true; // Unknown modifier.
396 const MachineOperand &MO = MI->getOperand(OpNum);
397 switch (ExtraCode[0]) {
399 // See if this is a generic print operand
400 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
401 case 'X': // hex const int
402 if ((MO.getType()) != MachineOperand::MO_Immediate)
404 O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
406 case 'x': // hex const int (low 16 bits)
407 if ((MO.getType()) != MachineOperand::MO_Immediate)
409 O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
411 case 'd': // decimal const int
412 if ((MO.getType()) != MachineOperand::MO_Immediate)
416 case 'm': // decimal const int minus 1
417 if ((MO.getType()) != MachineOperand::MO_Immediate)
419 O << MO.getImm() - 1;
422 // $0 if zero, regular printing otherwise
423 if (MO.getType() != MachineOperand::MO_Immediate)
425 int64_t Val = MO.getImm();
432 case 'D': // Second part of a double word register operand
433 case 'L': // Low order register of a double word register operand
434 case 'M': // High order register of a double word register operand
438 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
439 if (!FlagsOP.isImm())
441 unsigned Flags = FlagsOP.getImm();
442 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
443 // Number of registers represented by this operand. We are looking
444 // for 2 for 32 bit mode and 1 for 64 bit mode.
446 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
447 unsigned Reg = MO.getReg();
448 O << '$' << MipsInstPrinter::getRegisterName(Reg);
454 unsigned RegOp = OpNum;
455 if (!Subtarget->isGP64bit()){
456 // Endianess reverses which register holds the high or low value
458 switch(ExtraCode[0]) {
460 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
463 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
465 case 'D': // Always the second part
468 if (RegOp >= MI->getNumOperands())
470 const MachineOperand &MO = MI->getOperand(RegOp);
473 unsigned Reg = MO.getReg();
474 O << '$' << MipsInstPrinter::getRegisterName(Reg);
479 // Print MSA registers for the 'f' constraint
480 // In LLVM, the 'w' modifier doesn't need to do anything.
481 // We can just call printOperand as normal.
486 printOperand(MI, OpNum, O);
490 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
491 unsigned OpNum, unsigned AsmVariant,
492 const char *ExtraCode,
495 // Currently we are expecting either no ExtraCode or 'D'
497 if (ExtraCode[0] == 'D')
500 return true; // Unknown modifier.
503 const MachineOperand &MO = MI->getOperand(OpNum);
504 assert(MO.isReg() && "unexpected inline asm memory operand");
505 O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
510 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
512 const DataLayout *DL = TM.getDataLayout();
513 const MachineOperand &MO = MI->getOperand(opNum);
516 if (MO.getTargetFlags())
519 switch(MO.getTargetFlags()) {
520 case MipsII::MO_GPREL: O << "%gp_rel("; break;
521 case MipsII::MO_GOT_CALL: O << "%call16("; break;
522 case MipsII::MO_GOT: O << "%got("; break;
523 case MipsII::MO_ABS_HI: O << "%hi("; break;
524 case MipsII::MO_ABS_LO: O << "%lo("; break;
525 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
526 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
527 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
528 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
529 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
530 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
531 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
532 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
533 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
536 switch (MO.getType()) {
537 case MachineOperand::MO_Register:
539 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
542 case MachineOperand::MO_Immediate:
546 case MachineOperand::MO_MachineBasicBlock:
547 O << *MO.getMBB()->getSymbol();
550 case MachineOperand::MO_GlobalAddress:
551 O << *getSymbol(MO.getGlobal());
554 case MachineOperand::MO_BlockAddress: {
555 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
560 case MachineOperand::MO_ConstantPoolIndex:
561 O << DL->getPrivateGlobalPrefix() << "CPI"
562 << getFunctionNumber() << "_" << MO.getIndex();
564 O << "+" << MO.getOffset();
568 llvm_unreachable("<unknown operand type>");
571 if (closeP) O << ")";
574 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
576 const MachineOperand &MO = MI->getOperand(opNum);
578 O << (unsigned short int)MO.getImm();
580 printOperand(MI, opNum, O);
583 void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum,
585 const MachineOperand &MO = MI->getOperand(opNum);
587 O << (unsigned short int)(unsigned char)MO.getImm();
589 printOperand(MI, opNum, O);
592 void MipsAsmPrinter::
593 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
594 // Load/Store memory operands -- imm($reg)
595 // If PIC target the target is loaded as the
596 // pattern lw $25,%call16($28)
597 printOperand(MI, opNum+1, O);
599 printOperand(MI, opNum, O);
603 void MipsAsmPrinter::
604 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
605 // when using stack locations for not load/store instructions
606 // print the same way as all normal 3 operand instructions.
607 printOperand(MI, opNum, O);
609 printOperand(MI, opNum+1, O);
613 void MipsAsmPrinter::
614 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
615 const char *Modifier) {
616 const MachineOperand &MO = MI->getOperand(opNum);
617 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
620 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
621 // TODO: Need to add -mabicalls and -mno-abicalls flags.
622 // Currently we assume that -mabicalls is the default.
623 getTargetStreamer().emitDirectiveAbiCalls();
624 Reloc::Model RM = Subtarget->getRelocationModel();
625 if (RM == Reloc::Static && !Subtarget->hasMips64())
626 getTargetStreamer().emitDirectiveOptionPic0();
628 // Tell the assembler which ABI we are using
629 std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
630 OutStreamer.SwitchSection(OutContext.getELFSection(
631 SectionName, ELF::SHT_PROGBITS, 0, SectionKind::getDataRel()));
633 // TODO: handle O64 ABI
635 if (Subtarget->isABI_EABI()) {
636 if (Subtarget->isGP32bit())
637 OutStreamer.SwitchSection(
638 OutContext.getELFSection(".gcc_compiled_long32", ELF::SHT_PROGBITS, 0,
639 SectionKind::getDataRel()));
641 OutStreamer.SwitchSection(
642 OutContext.getELFSection(".gcc_compiled_long64", ELF::SHT_PROGBITS, 0,
643 SectionKind::getDataRel()));
647 void MipsAsmPrinter::EmitJal(MCSymbol *Symbol) {
649 I.setOpcode(Mips::JAL);
651 MCOperand::CreateExpr(MCSymbolRefExpr::Create(Symbol, OutContext)));
652 OutStreamer.EmitInstruction(I, getSubtargetInfo());
655 void MipsAsmPrinter::EmitInstrReg(unsigned Opcode, unsigned Reg) {
658 I.addOperand(MCOperand::CreateReg(Reg));
659 OutStreamer.EmitInstruction(I, getSubtargetInfo());
662 void MipsAsmPrinter::EmitInstrRegReg(unsigned Opcode, unsigned Reg1,
666 // Because of the current td files for Mips32, the operands for MTC1
667 // appear backwards from their normal assembly order. It's not a trivial
668 // change to fix this in the td file so we adjust for it here.
670 if (Opcode == Mips::MTC1) {
671 unsigned Temp = Reg1;
676 I.addOperand(MCOperand::CreateReg(Reg1));
677 I.addOperand(MCOperand::CreateReg(Reg2));
678 OutStreamer.EmitInstruction(I, getSubtargetInfo());
681 void MipsAsmPrinter::EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1,
682 unsigned Reg2, unsigned Reg3) {
685 I.addOperand(MCOperand::CreateReg(Reg1));
686 I.addOperand(MCOperand::CreateReg(Reg2));
687 I.addOperand(MCOperand::CreateReg(Reg3));
688 OutStreamer.EmitInstruction(I, getSubtargetInfo());
691 void MipsAsmPrinter::EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1,
692 unsigned Reg2, unsigned FPReg1,
693 unsigned FPReg2, bool LE) {
695 unsigned temp = Reg1;
699 EmitInstrRegReg(MovOpc, Reg1, FPReg1);
700 EmitInstrRegReg(MovOpc, Reg2, FPReg2);
703 void MipsAsmPrinter::EmitSwapFPIntParams(Mips16HardFloatInfo::FPParamVariant PV,
704 bool LE, bool ToFP) {
705 using namespace Mips16HardFloatInfo;
706 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
709 EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
712 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
715 EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
716 EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
719 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
722 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
723 EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
726 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
727 EmitInstrRegReg(MovOpc, Mips::A2, Mips::F14);
735 MipsAsmPrinter::EmitSwapFPIntRetval(Mips16HardFloatInfo::FPReturnVariant RV,
737 using namespace Mips16HardFloatInfo;
738 unsigned MovOpc = Mips::MFC1;
741 EmitInstrRegReg(MovOpc, Mips::V0, Mips::F0);
744 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
747 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
750 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
751 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
758 void MipsAsmPrinter::EmitFPCallStub(
759 const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
760 MCSymbol *MSymbol = OutContext.GetOrCreateSymbol(StringRef(Symbol));
761 using namespace Mips16HardFloatInfo;
762 bool LE = Subtarget->isLittle();
766 OutStreamer.EmitSymbolAttribute(MSymbol, MCSA_Global);
769 // make the comment field identifying the return and parameter
770 // types of the floating point stub
771 // # Stub function to call rettype xxxx (params)
773 switch (Signature->RetSig) {
784 RetType = "double complex";
791 switch (Signature->ParamSig) {
796 Parms = "float, float";
799 Parms = "float, double";
805 Parms = "double, double";
808 Parms = "double, float";
814 OutStreamer.AddComment("\t# Stub function to call " + Twine(RetType) + " " +
815 Twine(Symbol) + " (" + Twine(Parms) + ")");
817 // probably not necessary but we save and restore the current section state
819 OutStreamer.PushSection();
821 // .section mips16.call.fpxxxx,"ax",@progbits
823 const MCSectionELF *M = OutContext.getELFSection(
824 ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
825 ELF::SHF_ALLOC | ELF::SHF_EXECINSTR, SectionKind::getText());
826 OutStreamer.SwitchSection(M, 0);
830 OutStreamer.EmitValueToAlignment(4);
831 MipsTargetStreamer &TS = getTargetStreamer();
836 TS.emitDirectiveSetNoMips16();
837 TS.emitDirectiveSetNoMicroMips();
839 // .ent __call_stub_fp_xxxx
840 // .type __call_stub_fp_xxxx,@function
841 // __call_stub_fp_xxxx:
843 std::string x = "__call_stub_fp_" + std::string(Symbol);
844 MCSymbol *Stub = OutContext.GetOrCreateSymbol(StringRef(x));
845 TS.emitDirectiveEnt(*Stub);
847 OutContext.GetOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
848 OutStreamer.EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
849 OutStreamer.EmitLabel(Stub);
851 // we just handle non pic for now. these function will not be
852 // called otherwise. when the full stub generation is moved here
853 // we need to deal with pic.
855 if (Subtarget->getRelocationModel() == Reloc::PIC_)
856 llvm_unreachable("should not be here if we are compiling pic");
857 TS.emitDirectiveSetReorder();
859 // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
860 // stubs without raw text but this current patch is for compiler generated
861 // functions and they all return some value.
862 // The calling sequence for non pic is different in that case and we need
863 // to implement %lo and %hi in order to handle the case of no return value
864 // See the corresponding method in Mips16HardFloat for details.
866 // mov the return address to S2.
867 // we have no stack space to store it and we are about to make another call.
868 // We need to make sure that the enclosing function knows to save S2
869 // This should have already been handled.
873 EmitInstrRegRegReg(Mips::ADDu, Mips::S2, Mips::RA, Mips::ZERO);
875 EmitSwapFPIntParams(Signature->ParamSig, LE, true);
882 EmitSwapFPIntRetval(Signature->RetSig, LE);
885 // if (Signature->RetSig == NoFPRet)
886 // llvm_unreachable("should not be any stubs here with no return value");
888 EmitInstrReg(Mips::JR, Mips::S2);
890 MCSymbol *Tmp = OutContext.CreateTempSymbol();
891 OutStreamer.EmitLabel(Tmp);
892 const MCSymbolRefExpr *E = MCSymbolRefExpr::Create(Stub, OutContext);
893 const MCSymbolRefExpr *T = MCSymbolRefExpr::Create(Tmp, OutContext);
894 const MCExpr *T_min_E = MCBinaryExpr::CreateSub(T, E, OutContext);
895 OutStreamer.EmitELFSize(Stub, T_min_E);
896 TS.emitDirectiveEnd(x);
897 OutStreamer.PopSection();
900 void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
905 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
906 it = StubsNeeded.begin();
907 it != StubsNeeded.end(); ++it) {
908 const char *Symbol = it->first;
909 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
910 EmitFPCallStub(Symbol, Signature);
912 // return to the text section
913 OutStreamer.SwitchSection(OutContext.getObjectFileInfo()->getTextSection());
916 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
921 // Align all targets of indirect branches on bundle size. Used only if target
923 void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
924 // Align all blocks that are jumped to through jump table.
925 if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
926 const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
927 for (unsigned I = 0; I < JT.size(); ++I) {
928 const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
930 for (unsigned J = 0; J < MBBs.size(); ++J)
931 MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
935 // If basic block address is taken, block can be target of indirect branch.
936 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
938 if (MBB->hasAddressTaken())
939 MBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
943 // Force static initialization.
944 extern "C" void LLVMInitializeMipsAsmPrinter() {
945 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
946 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
947 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
948 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);