1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MCTargetDesc/MipsMCNaCl.h"
19 #include "MipsAsmPrinter.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMCInstLower.h"
22 #include "MipsTargetMachine.h"
23 #include "MipsTargetStreamer.h"
24 #include "llvm/ADT/SmallString.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/Twine.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/IR/BasicBlock.h"
34 #include "llvm/IR/DataLayout.h"
35 #include "llvm/IR/InlineAsm.h"
36 #include "llvm/IR/Instructions.h"
37 #include "llvm/IR/Mangler.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCELFStreamer.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCInst.h"
43 #include "llvm/MC/MCSection.h"
44 #include "llvm/MC/MCSectionELF.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/ELF.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetLoweringObjectFile.h"
50 #include "llvm/Target/TargetOptions.h"
55 #define DEBUG_TYPE "mips-asm-printer"
57 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() const {
58 return static_cast<MipsTargetStreamer &>(*OutStreamer.getTargetStreamer());
61 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
62 Subtarget = &MF.getSubtarget<MipsSubtarget>();
64 // Initialize TargetLoweringObjectFile.
65 const_cast<TargetLoweringObjectFile &>(getObjFileLowering())
66 .Initialize(OutContext, TM);
68 MipsFI = MF.getInfo<MipsFunctionInfo>();
69 if (Subtarget->inMips16Mode())
72 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
73 it = MipsFI->StubsNeeded.begin();
74 it != MipsFI->StubsNeeded.end(); ++it) {
75 const char *Symbol = it->first;
76 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
77 if (StubsNeeded.find(Symbol) == StubsNeeded.end())
78 StubsNeeded[Symbol] = Signature;
80 MCP = MF.getConstantPool();
82 // In NaCl, all indirect jump targets must be aligned to bundle size.
83 if (Subtarget->isTargetNaCl())
84 NaClAlignIndirectJumpTargets(MF);
86 AsmPrinter::runOnMachineFunction(MF);
90 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
91 MCOp = MCInstLowering.LowerOperand(MO);
92 return MCOp.isValid();
95 #include "MipsGenMCPseudoLowering.inc"
97 // Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
98 // JALR, or JALR64 as appropriate for the target
99 void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
100 const MachineInstr *MI) {
101 bool HasLinkReg = false;
104 if (Subtarget->hasMips64r6()) {
105 // MIPS64r6 should use (JALR64 ZERO_64, $rs)
106 TmpInst0.setOpcode(Mips::JALR64);
108 } else if (Subtarget->hasMips32r6()) {
109 // MIPS32r6 should use (JALR ZERO, $rs)
110 TmpInst0.setOpcode(Mips::JALR);
112 } else if (Subtarget->inMicroMipsMode())
113 // microMIPS should use (JR_MM $rs)
114 TmpInst0.setOpcode(Mips::JR_MM);
116 // Everything else should use (JR $rs)
117 TmpInst0.setOpcode(Mips::JR);
123 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
124 TmpInst0.addOperand(MCOperand::CreateReg(ZeroReg));
127 lowerOperand(MI->getOperand(0), MCOp);
128 TmpInst0.addOperand(MCOp);
130 EmitToStreamer(OutStreamer, TmpInst0);
133 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
134 MipsTargetStreamer &TS = getTargetStreamer();
135 TS.forbidModuleDirective();
137 if (MI->isDebugValue()) {
138 SmallString<128> Str;
139 raw_svector_ostream OS(Str);
141 PrintDebugValueComment(MI, OS);
145 // If we just ended a constant pool, mark it as such.
146 if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
147 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
148 InConstantPool = false;
150 if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
151 // CONSTPOOL_ENTRY - This instruction represents a floating
152 //constant pool in the function. The first operand is the ID#
153 // for this instruction, the second is the index into the
154 // MachineConstantPool that this is, the third is the size in
155 // bytes of this constant pool entry.
156 // The required alignment is specified on the basic block holding this MI.
158 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
159 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
161 // If this is the first entry of the pool, mark it.
162 if (!InConstantPool) {
163 OutStreamer.EmitDataRegion(MCDR_DataRegion);
164 InConstantPool = true;
167 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
169 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
170 if (MCPE.isMachineConstantPoolEntry())
171 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
173 EmitGlobalConstant(MCPE.Val.ConstVal);
178 MachineBasicBlock::const_instr_iterator I = MI;
179 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
182 // Do any auto-generated pseudo lowerings.
183 if (emitPseudoExpansionLowering(OutStreamer, &*I))
186 if (I->getOpcode() == Mips::PseudoReturn ||
187 I->getOpcode() == Mips::PseudoReturn64 ||
188 I->getOpcode() == Mips::PseudoIndirectBranch ||
189 I->getOpcode() == Mips::PseudoIndirectBranch64) {
190 emitPseudoIndirectBranch(OutStreamer, &*I);
194 // The inMips16Mode() test is not permanent.
195 // Some instructions are marked as pseudo right now which
196 // would make the test fail for the wrong reason but
197 // that will be fixed soon. We need this here because we are
198 // removing another test for this situation downstream in the
201 if (I->isPseudo() && !Subtarget->inMips16Mode()
202 && !isLongBranchPseudo(I->getOpcode()))
203 llvm_unreachable("Pseudo opcode found in EmitInstruction()");
206 MCInstLowering.Lower(I, TmpInst0);
207 EmitToStreamer(OutStreamer, TmpInst0);
208 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
211 //===----------------------------------------------------------------------===//
213 // Mips Asm Directives
215 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
216 // Describe the stack frame.
218 // -- Mask directives "(f)mask bitmask, offset"
219 // Tells the assembler which registers are saved and where.
220 // bitmask - contain a little endian bitset indicating which registers are
221 // saved on function prologue (e.g. with a 0x80000000 mask, the
222 // assembler knows the register 31 (RA) is saved at prologue.
223 // offset - the position before stack pointer subtraction indicating where
224 // the first saved register on prologue is located. (e.g. with a
226 // Consider the following function prologue:
229 // .mask 0xc0000000,-8
230 // addiu $sp, $sp, -48
234 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
235 // 30 (FP) are saved at prologue. As the save order on prologue is from
236 // left to right, RA is saved first. A -8 offset means that after the
237 // stack pointer subtration, the first register in the mask (RA) will be
238 // saved at address 48-8=40.
240 //===----------------------------------------------------------------------===//
242 //===----------------------------------------------------------------------===//
244 //===----------------------------------------------------------------------===//
246 // Create a bitmask with all callee saved registers for CPU or Floating Point
247 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
248 void MipsAsmPrinter::printSavedRegsBitmask() {
249 // CPU and FPU Saved Registers Bitmasks
250 unsigned CPUBitmask = 0, FPUBitmask = 0;
251 int CPUTopSavedRegOff, FPUTopSavedRegOff;
253 // Set the CPU and FPU Bitmasks
254 const MachineFrameInfo *MFI = MF->getFrameInfo();
255 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
256 // size of stack area to which FP callee-saved regs are saved.
257 unsigned CPURegSize = Mips::GPR32RegClass.getSize();
258 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
259 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
260 bool HasAFGR64Reg = false;
261 unsigned CSFPRegsSize = 0;
262 unsigned i, e = CSI.size();
265 for (i = 0; i != e; ++i) {
266 unsigned Reg = CSI[i].getReg();
267 if (Mips::GPR32RegClass.contains(Reg))
271 TM.getSubtargetImpl()->getRegisterInfo()->getEncodingValue(Reg);
272 if (Mips::AFGR64RegClass.contains(Reg)) {
273 FPUBitmask |= (3 << RegNum);
274 CSFPRegsSize += AFGR64RegSize;
279 FPUBitmask |= (1 << RegNum);
280 CSFPRegsSize += FGR32RegSize;
284 for (; i != e; ++i) {
285 unsigned Reg = CSI[i].getReg();
287 TM.getSubtargetImpl()->getRegisterInfo()->getEncodingValue(Reg);
288 CPUBitmask |= (1 << RegNum);
291 // FP Regs are saved right below where the virtual frame pointer points to.
292 FPUTopSavedRegOff = FPUBitmask ?
293 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
295 // CPU Regs are saved below FP Regs.
296 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
298 MipsTargetStreamer &TS = getTargetStreamer();
300 TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
303 TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
306 //===----------------------------------------------------------------------===//
307 // Frame and Set directives
308 //===----------------------------------------------------------------------===//
311 void MipsAsmPrinter::emitFrameDirective() {
312 const TargetRegisterInfo &RI = *TM.getSubtargetImpl()->getRegisterInfo();
314 unsigned stackReg = RI.getFrameRegister(*MF);
315 unsigned returnReg = RI.getRARegister();
316 unsigned stackSize = MF->getFrameInfo()->getStackSize();
318 getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
321 /// Emit Set directives.
322 const char *MipsAsmPrinter::getCurrentABIString() const {
323 switch (static_cast<MipsTargetMachine &>(TM).getABI().GetEnumValue()) {
324 case MipsABIInfo::ABI::O32: return "abi32";
325 case MipsABIInfo::ABI::N32: return "abiN32";
326 case MipsABIInfo::ABI::N64: return "abi64";
327 case MipsABIInfo::ABI::EABI: return "eabi32"; // TODO: handle eabi64
328 default: llvm_unreachable("Unknown Mips ABI");
332 void MipsAsmPrinter::EmitFunctionEntryLabel() {
333 MipsTargetStreamer &TS = getTargetStreamer();
335 // NaCl sandboxing requires that indirect call instructions are masked.
336 // This means that function entry points should be bundle-aligned.
337 if (Subtarget->isTargetNaCl())
338 EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN));
340 if (Subtarget->inMicroMipsMode())
341 TS.emitDirectiveSetMicroMips();
343 TS.emitDirectiveSetNoMicroMips();
345 if (Subtarget->inMips16Mode())
346 TS.emitDirectiveSetMips16();
348 TS.emitDirectiveSetNoMips16();
350 TS.emitDirectiveEnt(*CurrentFnSym);
351 OutStreamer.EmitLabel(CurrentFnSym);
354 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
355 /// the first basic block in the function.
356 void MipsAsmPrinter::EmitFunctionBodyStart() {
357 MipsTargetStreamer &TS = getTargetStreamer();
359 MCInstLowering.Initialize(&MF->getContext());
361 bool IsNakedFunction = MF->getFunction()->hasFnAttribute(Attribute::Naked);
362 if (!IsNakedFunction)
363 emitFrameDirective();
365 if (!IsNakedFunction)
366 printSavedRegsBitmask();
368 if (!Subtarget->inMips16Mode()) {
369 TS.emitDirectiveSetNoReorder();
370 TS.emitDirectiveSetNoMacro();
371 TS.emitDirectiveSetNoAt();
375 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
376 /// the last basic block in the function.
377 void MipsAsmPrinter::EmitFunctionBodyEnd() {
378 MipsTargetStreamer &TS = getTargetStreamer();
380 // There are instruction for this macros, but they must
381 // always be at the function end, and we can't emit and
382 // break with BB logic.
383 if (!Subtarget->inMips16Mode()) {
384 TS.emitDirectiveSetAt();
385 TS.emitDirectiveSetMacro();
386 TS.emitDirectiveSetReorder();
388 TS.emitDirectiveEnd(CurrentFnSym->getName());
389 // Make sure to terminate any constant pools that were at the end
393 InConstantPool = false;
394 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
397 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
398 /// exactly one predecessor and the control transfer mechanism between
399 /// the predecessor and this block is a fall-through.
400 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
402 // The predecessor has to be immediately before this block.
403 const MachineBasicBlock *Pred = *MBB->pred_begin();
405 // If the predecessor is a switch statement, assume a jump table
406 // implementation, so it is not a fall through.
407 if (const BasicBlock *bb = Pred->getBasicBlock())
408 if (isa<SwitchInst>(bb->getTerminator()))
411 // If this is a landing pad, it isn't a fall through. If it has no preds,
412 // then nothing falls through to it.
413 if (MBB->isLandingPad() || MBB->pred_empty())
416 // If there isn't exactly one predecessor, it can't be a fall through.
417 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
420 if (PI2 != MBB->pred_end())
423 // The predecessor has to be immediately before this block.
424 if (!Pred->isLayoutSuccessor(MBB))
427 // If the block is completely empty, then it definitely does fall through.
431 // Otherwise, check the last instruction.
432 // Check if the last terminator is an unconditional branch.
433 MachineBasicBlock::const_iterator I = Pred->end();
434 while (I != Pred->begin() && !(--I)->isTerminator()) ;
436 return !I->isBarrier();
439 // Print out an operand for an inline asm expression.
440 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
441 unsigned AsmVariant,const char *ExtraCode,
443 // Does this asm operand have a single letter operand modifier?
444 if (ExtraCode && ExtraCode[0]) {
445 if (ExtraCode[1] != 0) return true; // Unknown modifier.
447 const MachineOperand &MO = MI->getOperand(OpNum);
448 switch (ExtraCode[0]) {
450 // See if this is a generic print operand
451 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
452 case 'X': // hex const int
453 if ((MO.getType()) != MachineOperand::MO_Immediate)
455 O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
457 case 'x': // hex const int (low 16 bits)
458 if ((MO.getType()) != MachineOperand::MO_Immediate)
460 O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
462 case 'd': // decimal const int
463 if ((MO.getType()) != MachineOperand::MO_Immediate)
467 case 'm': // decimal const int minus 1
468 if ((MO.getType()) != MachineOperand::MO_Immediate)
470 O << MO.getImm() - 1;
473 // $0 if zero, regular printing otherwise
474 if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
478 // If not, call printOperand as normal.
481 case 'D': // Second part of a double word register operand
482 case 'L': // Low order register of a double word register operand
483 case 'M': // High order register of a double word register operand
487 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
488 if (!FlagsOP.isImm())
490 unsigned Flags = FlagsOP.getImm();
491 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
492 // Number of registers represented by this operand. We are looking
493 // for 2 for 32 bit mode and 1 for 64 bit mode.
495 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
496 unsigned Reg = MO.getReg();
497 O << '$' << MipsInstPrinter::getRegisterName(Reg);
503 unsigned RegOp = OpNum;
504 if (!Subtarget->isGP64bit()){
505 // Endianess reverses which register holds the high or low value
507 switch(ExtraCode[0]) {
509 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
512 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
514 case 'D': // Always the second part
517 if (RegOp >= MI->getNumOperands())
519 const MachineOperand &MO = MI->getOperand(RegOp);
522 unsigned Reg = MO.getReg();
523 O << '$' << MipsInstPrinter::getRegisterName(Reg);
528 // Print MSA registers for the 'f' constraint
529 // In LLVM, the 'w' modifier doesn't need to do anything.
530 // We can just call printOperand as normal.
535 printOperand(MI, OpNum, O);
539 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
540 unsigned OpNum, unsigned AsmVariant,
541 const char *ExtraCode,
544 // Currently we are expecting either no ExtraCode or 'D'
546 if (ExtraCode[0] == 'D')
549 return true; // Unknown modifier.
552 const MachineOperand &MO = MI->getOperand(OpNum);
553 assert(MO.isReg() && "unexpected inline asm memory operand");
554 O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
559 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
561 const DataLayout *DL = TM.getDataLayout();
562 const MachineOperand &MO = MI->getOperand(opNum);
565 if (MO.getTargetFlags())
568 switch(MO.getTargetFlags()) {
569 case MipsII::MO_GPREL: O << "%gp_rel("; break;
570 case MipsII::MO_GOT_CALL: O << "%call16("; break;
571 case MipsII::MO_GOT: O << "%got("; break;
572 case MipsII::MO_ABS_HI: O << "%hi("; break;
573 case MipsII::MO_ABS_LO: O << "%lo("; break;
574 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
575 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
576 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
577 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
578 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
579 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
580 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
581 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
582 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
585 switch (MO.getType()) {
586 case MachineOperand::MO_Register:
588 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
591 case MachineOperand::MO_Immediate:
595 case MachineOperand::MO_MachineBasicBlock:
596 O << *MO.getMBB()->getSymbol();
599 case MachineOperand::MO_GlobalAddress:
600 O << *getSymbol(MO.getGlobal());
603 case MachineOperand::MO_BlockAddress: {
604 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
609 case MachineOperand::MO_ConstantPoolIndex:
610 O << DL->getPrivateGlobalPrefix() << "CPI"
611 << getFunctionNumber() << "_" << MO.getIndex();
613 O << "+" << MO.getOffset();
617 llvm_unreachable("<unknown operand type>");
620 if (closeP) O << ")";
623 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
625 const MachineOperand &MO = MI->getOperand(opNum);
627 O << (unsigned short int)MO.getImm();
629 printOperand(MI, opNum, O);
632 void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum,
634 const MachineOperand &MO = MI->getOperand(opNum);
636 O << (unsigned short int)(unsigned char)MO.getImm();
638 printOperand(MI, opNum, O);
641 void MipsAsmPrinter::
642 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
643 // Load/Store memory operands -- imm($reg)
644 // If PIC target the target is loaded as the
645 // pattern lw $25,%call16($28)
647 // opNum can be invalid if instruction has reglist as operand.
648 // MemOperand is always last operand of instruction (base + offset).
649 switch (MI->getOpcode()) {
654 opNum = MI->getNumOperands() - 2;
658 printOperand(MI, opNum+1, O);
660 printOperand(MI, opNum, O);
664 void MipsAsmPrinter::
665 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
666 // when using stack locations for not load/store instructions
667 // print the same way as all normal 3 operand instructions.
668 printOperand(MI, opNum, O);
670 printOperand(MI, opNum+1, O);
674 void MipsAsmPrinter::
675 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
676 const char *Modifier) {
677 const MachineOperand &MO = MI->getOperand(opNum);
678 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
681 void MipsAsmPrinter::
682 printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) {
683 for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) {
684 if (i != opNum) O << ", ";
685 printOperand(MI, i, O);
689 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
691 // Compute MIPS architecture attributes based on the default subtarget
692 // that we'd have constructed. Module level directives aren't LTO
694 // FIXME: For ifunc related functions we could iterate over and look
695 // for a feature string that doesn't match the default one.
696 StringRef TT = TM.getTargetTriple();
698 MIPS_MC::selectMipsCPU(TM.getTargetTriple(), TM.getTargetCPU());
699 StringRef FS = TM.getTargetFeatureString();
700 const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
701 const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM);
703 bool IsABICalls = STI.isABICalls();
704 const MipsABIInfo &ABI = MTM.getABI();
706 getTargetStreamer().emitDirectiveAbiCalls();
707 Reloc::Model RM = TM.getRelocationModel();
708 // FIXME: This condition should be a lot more complicated that it is here.
709 // Ideally it should test for properties of the ABI and not the ABI
711 // For the moment, I'm only correcting enough to make MIPS-IV work.
712 if (RM == Reloc::Static && !ABI.IsN64())
713 getTargetStreamer().emitDirectiveOptionPic0();
716 // Tell the assembler which ABI we are using
717 std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
718 OutStreamer.SwitchSection(
719 OutContext.getELFSection(SectionName, ELF::SHT_PROGBITS, 0));
721 // NaN: At the moment we only support:
722 // 1. .nan legacy (default)
724 STI.isNaN2008() ? getTargetStreamer().emitDirectiveNaN2008()
725 : getTargetStreamer().emitDirectiveNaNLegacy();
727 // TODO: handle O64 ABI
731 OutStreamer.SwitchSection(OutContext.getELFSection(".gcc_compiled_long32",
732 ELF::SHT_PROGBITS, 0));
734 OutStreamer.SwitchSection(OutContext.getELFSection(".gcc_compiled_long64",
735 ELF::SHT_PROGBITS, 0));
738 getTargetStreamer().updateABIInfo(STI);
740 // We should always emit a '.module fp=...' but binutils 2.24 does not accept
741 // it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or
742 // -mfp64) and omit it otherwise.
743 if (ABI.IsO32() && (STI.isABI_FPXX() || STI.isFP64bit()))
744 getTargetStreamer().emitDirectiveModuleFP();
746 // We should always emit a '.module [no]oddspreg' but binutils 2.24 does not
747 // accept it. We therefore emit it when it contradicts the default or an
748 // option has changed the default (i.e. FPXX) and omit it otherwise.
749 if (ABI.IsO32() && (!STI.useOddSPReg() || STI.isABI_FPXX()))
750 getTargetStreamer().emitDirectiveModuleOddSPReg(STI.useOddSPReg(),
754 void MipsAsmPrinter::emitInlineAsmStart() const {
755 MipsTargetStreamer &TS = getTargetStreamer();
757 // GCC's choice of assembler options for inline assembly code ('at', 'macro'
758 // and 'reorder') is different from LLVM's choice for generated code ('noat',
759 // 'nomacro' and 'noreorder').
760 // In order to maintain compatibility with inline assembly code which depends
761 // on GCC's assembler options being used, we have to switch to those options
762 // for the duration of the inline assembly block and then switch back.
763 TS.emitDirectiveSetPush();
764 TS.emitDirectiveSetAt();
765 TS.emitDirectiveSetMacro();
766 TS.emitDirectiveSetReorder();
767 OutStreamer.AddBlankLine();
770 void MipsAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
771 const MCSubtargetInfo *EndInfo) const {
772 OutStreamer.AddBlankLine();
773 getTargetStreamer().emitDirectiveSetPop();
776 void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) {
778 I.setOpcode(Mips::JAL);
780 MCOperand::CreateExpr(MCSymbolRefExpr::Create(Symbol, OutContext)));
781 OutStreamer.EmitInstruction(I, STI);
784 void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode,
788 I.addOperand(MCOperand::CreateReg(Reg));
789 OutStreamer.EmitInstruction(I, STI);
792 void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo &STI,
793 unsigned Opcode, unsigned Reg1,
797 // Because of the current td files for Mips32, the operands for MTC1
798 // appear backwards from their normal assembly order. It's not a trivial
799 // change to fix this in the td file so we adjust for it here.
801 if (Opcode == Mips::MTC1) {
802 unsigned Temp = Reg1;
807 I.addOperand(MCOperand::CreateReg(Reg1));
808 I.addOperand(MCOperand::CreateReg(Reg2));
809 OutStreamer.EmitInstruction(I, STI);
812 void MipsAsmPrinter::EmitInstrRegRegReg(const MCSubtargetInfo &STI,
813 unsigned Opcode, unsigned Reg1,
814 unsigned Reg2, unsigned Reg3) {
817 I.addOperand(MCOperand::CreateReg(Reg1));
818 I.addOperand(MCOperand::CreateReg(Reg2));
819 I.addOperand(MCOperand::CreateReg(Reg3));
820 OutStreamer.EmitInstruction(I, STI);
823 void MipsAsmPrinter::EmitMovFPIntPair(const MCSubtargetInfo &STI,
824 unsigned MovOpc, unsigned Reg1,
825 unsigned Reg2, unsigned FPReg1,
826 unsigned FPReg2, bool LE) {
828 unsigned temp = Reg1;
832 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1);
833 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2);
836 void MipsAsmPrinter::EmitSwapFPIntParams(const MCSubtargetInfo &STI,
837 Mips16HardFloatInfo::FPParamVariant PV,
838 bool LE, bool ToFP) {
839 using namespace Mips16HardFloatInfo;
840 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
843 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
846 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
849 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
850 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
853 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
856 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
857 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
860 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
861 EmitInstrRegReg(STI, MovOpc, Mips::A2, Mips::F14);
868 void MipsAsmPrinter::EmitSwapFPIntRetval(
869 const MCSubtargetInfo &STI, Mips16HardFloatInfo::FPReturnVariant RV,
871 using namespace Mips16HardFloatInfo;
872 unsigned MovOpc = Mips::MFC1;
875 EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);
878 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
881 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
884 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
885 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
892 void MipsAsmPrinter::EmitFPCallStub(
893 const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
894 MCSymbol *MSymbol = OutContext.GetOrCreateSymbol(StringRef(Symbol));
895 using namespace Mips16HardFloatInfo;
896 bool LE = getDataLayout().isLittleEndian();
897 // Construct a local MCSubtargetInfo here.
898 // This is because the MachineFunction won't exist (but have not yet been
899 // freed) and since we're at the global level we can use the default
900 // constructed subtarget.
901 std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
902 TM.getTargetTriple(), TM.getTargetCPU(), TM.getTargetFeatureString()));
907 OutStreamer.EmitSymbolAttribute(MSymbol, MCSA_Global);
910 // make the comment field identifying the return and parameter
911 // types of the floating point stub
912 // # Stub function to call rettype xxxx (params)
914 switch (Signature->RetSig) {
925 RetType = "double complex";
932 switch (Signature->ParamSig) {
937 Parms = "float, float";
940 Parms = "float, double";
946 Parms = "double, double";
949 Parms = "double, float";
955 OutStreamer.AddComment("\t# Stub function to call " + Twine(RetType) + " " +
956 Twine(Symbol) + " (" + Twine(Parms) + ")");
958 // probably not necessary but we save and restore the current section state
960 OutStreamer.PushSection();
962 // .section mips16.call.fpxxxx,"ax",@progbits
964 const MCSectionELF *M = OutContext.getELFSection(
965 ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
966 ELF::SHF_ALLOC | ELF::SHF_EXECINSTR);
967 OutStreamer.SwitchSection(M, nullptr);
971 OutStreamer.EmitValueToAlignment(4);
972 MipsTargetStreamer &TS = getTargetStreamer();
977 TS.emitDirectiveSetNoMips16();
978 TS.emitDirectiveSetNoMicroMips();
980 // .ent __call_stub_fp_xxxx
981 // .type __call_stub_fp_xxxx,@function
982 // __call_stub_fp_xxxx:
984 std::string x = "__call_stub_fp_" + std::string(Symbol);
985 MCSymbol *Stub = OutContext.GetOrCreateSymbol(StringRef(x));
986 TS.emitDirectiveEnt(*Stub);
988 OutContext.GetOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
989 OutStreamer.EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
990 OutStreamer.EmitLabel(Stub);
992 // Only handle non-pic for now.
993 assert(TM.getRelocationModel() != Reloc::PIC_ &&
994 "should not be here if we are compiling pic");
995 TS.emitDirectiveSetReorder();
997 // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
998 // stubs without raw text but this current patch is for compiler generated
999 // functions and they all return some value.
1000 // The calling sequence for non pic is different in that case and we need
1001 // to implement %lo and %hi in order to handle the case of no return value
1002 // See the corresponding method in Mips16HardFloat for details.
1004 // mov the return address to S2.
1005 // we have no stack space to store it and we are about to make another call.
1006 // We need to make sure that the enclosing function knows to save S2
1007 // This should have already been handled.
1011 EmitInstrRegRegReg(*STI, Mips::ADDu, Mips::S2, Mips::RA, Mips::ZERO);
1013 EmitSwapFPIntParams(*STI, Signature->ParamSig, LE, true);
1017 EmitJal(*STI, MSymbol);
1019 // fix return values
1020 EmitSwapFPIntRetval(*STI, Signature->RetSig, LE);
1023 // if (Signature->RetSig == NoFPRet)
1024 // llvm_unreachable("should not be any stubs here with no return value");
1026 EmitInstrReg(*STI, Mips::JR, Mips::S2);
1028 MCSymbol *Tmp = OutContext.CreateTempSymbol();
1029 OutStreamer.EmitLabel(Tmp);
1030 const MCSymbolRefExpr *E = MCSymbolRefExpr::Create(Stub, OutContext);
1031 const MCSymbolRefExpr *T = MCSymbolRefExpr::Create(Tmp, OutContext);
1032 const MCExpr *T_min_E = MCBinaryExpr::CreateSub(T, E, OutContext);
1033 OutStreamer.EmitELFSize(Stub, T_min_E);
1034 TS.emitDirectiveEnd(x);
1035 OutStreamer.PopSection();
1038 void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
1039 // Emit needed stubs
1043 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
1044 it = StubsNeeded.begin();
1045 it != StubsNeeded.end(); ++it) {
1046 const char *Symbol = it->first;
1047 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
1048 EmitFPCallStub(Symbol, Signature);
1050 // return to the text section
1051 OutStreamer.SwitchSection(OutContext.getObjectFileInfo()->getTextSection());
1054 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1059 // Align all targets of indirect branches on bundle size. Used only if target
1061 void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
1062 // Align all blocks that are jumped to through jump table.
1063 if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
1064 const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
1065 for (unsigned I = 0; I < JT.size(); ++I) {
1066 const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
1068 for (unsigned J = 0; J < MBBs.size(); ++J)
1069 MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1073 // If basic block address is taken, block can be target of indirect branch.
1074 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
1076 if (MBB->hasAddressTaken())
1077 MBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1081 bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
1082 return (Opcode == Mips::LONG_BRANCH_LUi
1083 || Opcode == Mips::LONG_BRANCH_ADDiu
1084 || Opcode == Mips::LONG_BRANCH_DADDiu);
1087 // Force static initialization.
1088 extern "C" void LLVMInitializeMipsAsmPrinter() {
1089 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
1090 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
1091 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
1092 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);