1 //===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-asm-printer"
17 #include "MipsAsmPrinter.h"
18 #include "MipsInstrInfo.h"
19 #include "MipsMachineFunction.h"
20 #include "MipsMCInstLower.h"
21 #include "InstPrinter/MipsInstPrinter.h"
22 #include "MCTargetDesc/MipsBaseInfo.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/Analysis/DebugInfo.h"
27 #include "llvm/BasicBlock.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineConstantPool.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineInstr.h"
33 #include "llvm/CodeGen/MachineMemOperand.h"
34 #include "llvm/Instructions.h"
35 #include "llvm/MC/MCStreamer.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Support/TargetRegistry.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/Mangler.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetLoweringObjectFile.h"
44 #include "llvm/Target/TargetOptions.h"
48 static bool isUnalignedLoadStore(unsigned Opc) {
49 return Opc == Mips::ULW || Opc == Mips::ULH || Opc == Mips::ULHu ||
50 Opc == Mips::USW || Opc == Mips::USH ||
51 Opc == Mips::ULW_P8 || Opc == Mips::ULH_P8 || Opc == Mips::ULHu_P8 ||
52 Opc == Mips::USW_P8 || Opc == Mips::USH_P8 ||
53 Opc == Mips::ULD || Opc == Mips::ULW64 || Opc == Mips::ULH64 ||
54 Opc == Mips::ULHu64 || Opc == Mips::USD || Opc == Mips::USW64 ||
56 Opc == Mips::ULD_P8 || Opc == Mips::ULW64_P8 ||
57 Opc == Mips::ULH64_P8 || Opc == Mips::ULHu64_P8 ||
58 Opc == Mips::USD_P8 || Opc == Mips::USW64_P8 ||
59 Opc == Mips::USH64_P8;
62 static bool isDirective(unsigned Opc) {
63 return Opc == Mips::MACRO || Opc == Mips::NOMACRO ||
64 Opc == Mips::REORDER || Opc == Mips::NOREORDER ||
65 Opc == Mips::ATMACRO || Opc == Mips::NOAT;
68 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
69 if (MI->isDebugValue()) {
71 raw_svector_ostream OS(Str);
73 PrintDebugValueComment(MI, OS);
77 MipsMCInstLower MCInstLowering(Mang, *MF, *this);
78 unsigned Opc = MI->getOpcode();
80 SmallVector<MCInst, 4> MCInsts;
81 MCInstLowering.Lower(MI, TmpInst0);
83 if (!OutStreamer.hasRawTextSupport() && isDirective(Opc))
86 // Enclose unaligned load or store with .macro & .nomacro directives.
87 if (isUnalignedLoadStore(Opc)) {
88 if (OutStreamer.hasRawTextSupport()) {
90 Directive.setOpcode(Mips::MACRO);
91 OutStreamer.EmitInstruction(Directive);
92 OutStreamer.EmitInstruction(TmpInst0);
93 Directive.setOpcode(Mips::NOMACRO);
94 OutStreamer.EmitInstruction(Directive);
96 MCInstLowering.LowerUnalignedLoadStore(MI, MCInsts);
97 for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin(); I
98 != MCInsts.end(); ++I)
99 OutStreamer.EmitInstruction(*I);
104 if (!OutStreamer.hasRawTextSupport()) {
105 // Lower CPLOAD and CPRESTORE
106 if (Opc == Mips::CPLOAD)
107 MCInstLowering.LowerCPLOAD(MI, MCInsts);
108 else if (Opc == Mips::CPRESTORE)
109 MCInstLowering.LowerCPRESTORE(MI, MCInsts);
111 if (!MCInsts.empty()) {
112 for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
113 I != MCInsts.end(); ++I)
114 OutStreamer.EmitInstruction(*I);
119 OutStreamer.EmitInstruction(TmpInst0);
122 //===----------------------------------------------------------------------===//
124 // Mips Asm Directives
126 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
127 // Describe the stack frame.
129 // -- Mask directives "(f)mask bitmask, offset"
130 // Tells the assembler which registers are saved and where.
131 // bitmask - contain a little endian bitset indicating which registers are
132 // saved on function prologue (e.g. with a 0x80000000 mask, the
133 // assembler knows the register 31 (RA) is saved at prologue.
134 // offset - the position before stack pointer subtraction indicating where
135 // the first saved register on prologue is located. (e.g. with a
137 // Consider the following function prologue:
140 // .mask 0xc0000000,-8
141 // addiu $sp, $sp, -48
145 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
146 // 30 (FP) are saved at prologue. As the save order on prologue is from
147 // left to right, RA is saved first. A -8 offset means that after the
148 // stack pointer subtration, the first register in the mask (RA) will be
149 // saved at address 48-8=40.
151 //===----------------------------------------------------------------------===//
153 //===----------------------------------------------------------------------===//
155 //===----------------------------------------------------------------------===//
157 // Create a bitmask with all callee saved registers for CPU or Floating Point
158 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
159 void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
160 // CPU and FPU Saved Registers Bitmasks
161 unsigned CPUBitmask = 0, FPUBitmask = 0;
162 int CPUTopSavedRegOff, FPUTopSavedRegOff;
164 // Set the CPU and FPU Bitmasks
165 const MachineFrameInfo *MFI = MF->getFrameInfo();
166 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
167 // size of stack area to which FP callee-saved regs are saved.
168 unsigned CPURegSize = Mips::CPURegsRegisterClass->getSize();
169 unsigned FGR32RegSize = Mips::FGR32RegisterClass->getSize();
170 unsigned AFGR64RegSize = Mips::AFGR64RegisterClass->getSize();
171 bool HasAFGR64Reg = false;
172 unsigned CSFPRegsSize = 0;
173 unsigned i, e = CSI.size();
176 for (i = 0; i != e; ++i) {
177 unsigned Reg = CSI[i].getReg();
178 if (Mips::CPURegsRegisterClass->contains(Reg))
181 unsigned RegNum = getMipsRegisterNumbering(Reg);
182 if (Mips::AFGR64RegisterClass->contains(Reg)) {
183 FPUBitmask |= (3 << RegNum);
184 CSFPRegsSize += AFGR64RegSize;
189 FPUBitmask |= (1 << RegNum);
190 CSFPRegsSize += FGR32RegSize;
194 for (; i != e; ++i) {
195 unsigned Reg = CSI[i].getReg();
196 unsigned RegNum = getMipsRegisterNumbering(Reg);
197 CPUBitmask |= (1 << RegNum);
200 // FP Regs are saved right below where the virtual frame pointer points to.
201 FPUTopSavedRegOff = FPUBitmask ?
202 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
204 // CPU Regs are saved below FP Regs.
205 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
208 O << "\t.mask \t"; printHex32(CPUBitmask, O);
209 O << ',' << CPUTopSavedRegOff << '\n';
212 O << "\t.fmask\t"; printHex32(FPUBitmask, O);
213 O << "," << FPUTopSavedRegOff << '\n';
216 // Print a 32 bit hex number with all numbers.
217 void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
219 for (int i = 7; i >= 0; i--)
220 O.write_hex((Value & (0xF << (i*4))) >> (i*4));
223 //===----------------------------------------------------------------------===//
224 // Frame and Set directives
225 //===----------------------------------------------------------------------===//
228 void MipsAsmPrinter::emitFrameDirective() {
229 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
231 unsigned stackReg = RI.getFrameRegister(*MF);
232 unsigned returnReg = RI.getRARegister();
233 unsigned stackSize = MF->getFrameInfo()->getStackSize();
235 if (OutStreamer.hasRawTextSupport())
236 OutStreamer.EmitRawText("\t.frame\t$" +
237 StringRef(MipsInstPrinter::getRegisterName(stackReg)).lower() +
238 "," + Twine(stackSize) + ",$" +
239 StringRef(MipsInstPrinter::getRegisterName(returnReg)).lower());
242 /// Emit Set directives.
243 const char *MipsAsmPrinter::getCurrentABIString() const {
244 switch (Subtarget->getTargetABI()) {
245 case MipsSubtarget::O32: return "abi32";
246 case MipsSubtarget::N32: return "abiN32";
247 case MipsSubtarget::N64: return "abi64";
248 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
252 llvm_unreachable("Unknown Mips ABI");
256 void MipsAsmPrinter::EmitFunctionEntryLabel() {
257 if (OutStreamer.hasRawTextSupport())
258 OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName()));
259 OutStreamer.EmitLabel(CurrentFnSym);
262 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
263 /// the first basic block in the function.
264 void MipsAsmPrinter::EmitFunctionBodyStart() {
265 emitFrameDirective();
267 if (OutStreamer.hasRawTextSupport()) {
268 SmallString<128> Str;
269 raw_svector_ostream OS(Str);
270 printSavedRegsBitmask(OS);
271 OutStreamer.EmitRawText(OS.str());
275 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
276 /// the last basic block in the function.
277 void MipsAsmPrinter::EmitFunctionBodyEnd() {
278 // There are instruction for this macros, but they must
279 // always be at the function end, and we can't emit and
280 // break with BB logic.
281 if (OutStreamer.hasRawTextSupport()) {
282 OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
283 OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
284 OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
288 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
289 /// exactly one predecessor and the control transfer mechanism between
290 /// the predecessor and this block is a fall-through.
291 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
293 // The predecessor has to be immediately before this block.
294 const MachineBasicBlock *Pred = *MBB->pred_begin();
296 // If the predecessor is a switch statement, assume a jump table
297 // implementation, so it is not a fall through.
298 if (const BasicBlock *bb = Pred->getBasicBlock())
299 if (isa<SwitchInst>(bb->getTerminator()))
302 // If this is a landing pad, it isn't a fall through. If it has no preds,
303 // then nothing falls through to it.
304 if (MBB->isLandingPad() || MBB->pred_empty())
307 // If there isn't exactly one predecessor, it can't be a fall through.
308 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
311 if (PI2 != MBB->pred_end())
314 // The predecessor has to be immediately before this block.
315 if (!Pred->isLayoutSuccessor(MBB))
318 // If the block is completely empty, then it definitely does fall through.
322 // Otherwise, check the last instruction.
323 // Check if the last terminator is an unconditional branch.
324 MachineBasicBlock::const_iterator I = Pred->end();
325 while (I != Pred->begin() && !(--I)->isTerminator()) ;
327 return !I->isBarrier();
330 // Print out an operand for an inline asm expression.
331 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
332 unsigned AsmVariant,const char *ExtraCode,
334 // Does this asm operand have a single letter operand modifier?
335 if (ExtraCode && ExtraCode[0])
336 return true; // Unknown modifier.
338 printOperand(MI, OpNo, O);
342 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
343 unsigned OpNum, unsigned AsmVariant,
344 const char *ExtraCode,
346 if (ExtraCode && ExtraCode[0])
347 return true; // Unknown modifier.
349 const MachineOperand &MO = MI->getOperand(OpNum);
350 assert(MO.isReg() && "unexpected inline asm memory operand");
351 O << "0($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
355 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
357 const MachineOperand &MO = MI->getOperand(opNum);
360 if (MO.getTargetFlags())
363 switch(MO.getTargetFlags()) {
364 case MipsII::MO_GPREL: O << "%gp_rel("; break;
365 case MipsII::MO_GOT_CALL: O << "%call16("; break;
366 case MipsII::MO_GOT: O << "%got("; break;
367 case MipsII::MO_ABS_HI: O << "%hi("; break;
368 case MipsII::MO_ABS_LO: O << "%lo("; break;
369 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
370 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
371 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
372 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
373 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
374 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
375 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
376 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
377 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
380 switch (MO.getType()) {
381 case MachineOperand::MO_Register:
383 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
386 case MachineOperand::MO_Immediate:
390 case MachineOperand::MO_MachineBasicBlock:
391 O << *MO.getMBB()->getSymbol();
394 case MachineOperand::MO_GlobalAddress:
395 O << *Mang->getSymbol(MO.getGlobal());
398 case MachineOperand::MO_BlockAddress: {
399 MCSymbol* BA = GetBlockAddressSymbol(MO.getBlockAddress());
404 case MachineOperand::MO_ExternalSymbol:
405 O << *GetExternalSymbolSymbol(MO.getSymbolName());
408 case MachineOperand::MO_JumpTableIndex:
409 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
410 << '_' << MO.getIndex();
413 case MachineOperand::MO_ConstantPoolIndex:
414 O << MAI->getPrivateGlobalPrefix() << "CPI"
415 << getFunctionNumber() << "_" << MO.getIndex();
417 O << "+" << MO.getOffset();
421 llvm_unreachable("<unknown operand type>");
424 if (closeP) O << ")";
427 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
429 const MachineOperand &MO = MI->getOperand(opNum);
431 O << (unsigned short int)MO.getImm();
433 printOperand(MI, opNum, O);
436 void MipsAsmPrinter::
437 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
438 // Load/Store memory operands -- imm($reg)
439 // If PIC target the target is loaded as the
440 // pattern lw $25,%call16($28)
441 printOperand(MI, opNum+1, O);
443 printOperand(MI, opNum, O);
447 void MipsAsmPrinter::
448 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
449 // when using stack locations for not load/store instructions
450 // print the same way as all normal 3 operand instructions.
451 printOperand(MI, opNum, O);
453 printOperand(MI, opNum+1, O);
457 void MipsAsmPrinter::
458 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
459 const char *Modifier) {
460 const MachineOperand& MO = MI->getOperand(opNum);
461 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
464 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
465 // FIXME: Use SwitchSection.
467 // Tell the assembler which ABI we are using
468 if (OutStreamer.hasRawTextSupport())
469 OutStreamer.EmitRawText("\t.section .mdebug." +
470 Twine(getCurrentABIString()));
472 // TODO: handle O64 ABI
473 if (OutStreamer.hasRawTextSupport()) {
474 if (Subtarget->isABI_EABI()) {
475 if (Subtarget->isGP32bit())
476 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32"));
478 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64"));
482 // return to previous section
483 if (OutStreamer.hasRawTextSupport())
484 OutStreamer.EmitRawText(StringRef("\t.previous"));
488 MipsAsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
489 // Handles frame addresses emitted in MipsInstrInfo::emitFrameIndexDebugValue.
490 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
491 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
492 "Unexpected MachineOperand types");
493 return MachineLocation(MI->getOperand(0).getReg(),
494 MI->getOperand(1).getImm());
497 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
502 // Force static initialization.
503 extern "C" void LLVMInitializeMipsAsmPrinter() {
504 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
505 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
506 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
507 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);