1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-asm-printer"
16 #include "InstPrinter/MipsInstPrinter.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
19 #include "MipsAsmPrinter.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMCInstLower.h"
22 #include "MipsTargetStreamer.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/IR/BasicBlock.h"
32 #include "llvm/IR/DataLayout.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/Instructions.h"
35 #include "llvm/IR/Mangler.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCELFStreamer.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionELF.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/Support/ELF.h"
43 #include "llvm/Support/TargetRegistry.h"
44 #include "llvm/Support/raw_ostream.h"
45 #include "llvm/Target/TargetLoweringObjectFile.h"
46 #include "llvm/Target/TargetOptions.h"
50 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() {
51 return static_cast<MipsTargetStreamer &>(*OutStreamer.getTargetStreamer());
54 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
55 // Initialize TargetLoweringObjectFile.
56 if (Subtarget->allowMixed16_32())
57 const_cast<TargetLoweringObjectFile&>(getObjFileLowering())
58 .Initialize(OutContext, TM);
59 MipsFI = MF.getInfo<MipsFunctionInfo>();
60 MCP = MF.getConstantPool();
61 AsmPrinter::runOnMachineFunction(MF);
65 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
66 MCOp = MCInstLowering.LowerOperand(MO);
67 return MCOp.isValid();
70 #include "MipsGenMCPseudoLowering.inc"
72 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
73 if (MI->isDebugValue()) {
75 raw_svector_ostream OS(Str);
77 PrintDebugValueComment(MI, OS);
81 // If we just ended a constant pool, mark it as such.
82 if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
83 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
84 InConstantPool = false;
86 if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
87 // CONSTPOOL_ENTRY - This instruction represents a floating
88 //constant pool in the function. The first operand is the ID#
89 // for this instruction, the second is the index into the
90 // MachineConstantPool that this is, the third is the size in
91 // bytes of this constant pool entry.
92 // The required alignment is specified on the basic block holding this MI.
94 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
95 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
97 // If this is the first entry of the pool, mark it.
98 if (!InConstantPool) {
99 OutStreamer.EmitDataRegion(MCDR_DataRegion);
100 InConstantPool = true;
103 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
105 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
106 if (MCPE.isMachineConstantPoolEntry())
107 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
109 EmitGlobalConstant(MCPE.Val.ConstVal);
114 MachineBasicBlock::const_instr_iterator I = MI;
115 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
118 // Do any auto-generated pseudo lowerings.
119 if (emitPseudoExpansionLowering(OutStreamer, &*I))
122 // The inMips16Mode() test is not permanent.
123 // Some instructions are marked as pseudo right now which
124 // would make the test fail for the wrong reason but
125 // that will be fixed soon. We need this here because we are
126 // removing another test for this situation downstream in the
129 if (I->isPseudo() && !Subtarget->inMips16Mode())
130 llvm_unreachable("Pseudo opcode found in EmitInstruction()");
133 MCInstLowering.Lower(I, TmpInst0);
134 OutStreamer.EmitInstruction(TmpInst0);
135 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
138 //===----------------------------------------------------------------------===//
140 // Mips Asm Directives
142 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
143 // Describe the stack frame.
145 // -- Mask directives "(f)mask bitmask, offset"
146 // Tells the assembler which registers are saved and where.
147 // bitmask - contain a little endian bitset indicating which registers are
148 // saved on function prologue (e.g. with a 0x80000000 mask, the
149 // assembler knows the register 31 (RA) is saved at prologue.
150 // offset - the position before stack pointer subtraction indicating where
151 // the first saved register on prologue is located. (e.g. with a
153 // Consider the following function prologue:
156 // .mask 0xc0000000,-8
157 // addiu $sp, $sp, -48
161 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
162 // 30 (FP) are saved at prologue. As the save order on prologue is from
163 // left to right, RA is saved first. A -8 offset means that after the
164 // stack pointer subtration, the first register in the mask (RA) will be
165 // saved at address 48-8=40.
167 //===----------------------------------------------------------------------===//
169 //===----------------------------------------------------------------------===//
171 //===----------------------------------------------------------------------===//
173 // Create a bitmask with all callee saved registers for CPU or Floating Point
174 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
175 void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
176 // CPU and FPU Saved Registers Bitmasks
177 unsigned CPUBitmask = 0, FPUBitmask = 0;
178 int CPUTopSavedRegOff, FPUTopSavedRegOff;
180 // Set the CPU and FPU Bitmasks
181 const MachineFrameInfo *MFI = MF->getFrameInfo();
182 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
183 // size of stack area to which FP callee-saved regs are saved.
184 unsigned CPURegSize = Mips::GPR32RegClass.getSize();
185 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
186 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
187 bool HasAFGR64Reg = false;
188 unsigned CSFPRegsSize = 0;
189 unsigned i, e = CSI.size();
192 for (i = 0; i != e; ++i) {
193 unsigned Reg = CSI[i].getReg();
194 if (Mips::GPR32RegClass.contains(Reg))
197 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
198 if (Mips::AFGR64RegClass.contains(Reg)) {
199 FPUBitmask |= (3 << RegNum);
200 CSFPRegsSize += AFGR64RegSize;
205 FPUBitmask |= (1 << RegNum);
206 CSFPRegsSize += FGR32RegSize;
210 for (; i != e; ++i) {
211 unsigned Reg = CSI[i].getReg();
212 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
213 CPUBitmask |= (1 << RegNum);
216 // FP Regs are saved right below where the virtual frame pointer points to.
217 FPUTopSavedRegOff = FPUBitmask ?
218 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
220 // CPU Regs are saved below FP Regs.
221 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
224 O << "\t.mask \t"; printHex32(CPUBitmask, O);
225 O << ',' << CPUTopSavedRegOff << '\n';
228 O << "\t.fmask\t"; printHex32(FPUBitmask, O);
229 O << "," << FPUTopSavedRegOff << '\n';
232 // Print a 32 bit hex number with all numbers.
233 void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
235 for (int i = 7; i >= 0; i--)
236 O.write_hex((Value & (0xF << (i*4))) >> (i*4));
239 //===----------------------------------------------------------------------===//
240 // Frame and Set directives
241 //===----------------------------------------------------------------------===//
244 void MipsAsmPrinter::emitFrameDirective() {
245 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
247 unsigned stackReg = RI.getFrameRegister(*MF);
248 unsigned returnReg = RI.getRARegister();
249 unsigned stackSize = MF->getFrameInfo()->getStackSize();
251 getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
254 /// Emit Set directives.
255 const char *MipsAsmPrinter::getCurrentABIString() const {
256 switch (Subtarget->getTargetABI()) {
257 case MipsSubtarget::O32: return "abi32";
258 case MipsSubtarget::N32: return "abiN32";
259 case MipsSubtarget::N64: return "abi64";
260 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
261 default: llvm_unreachable("Unknown Mips ABI");
265 void MipsAsmPrinter::EmitFunctionEntryLabel() {
266 MipsTargetStreamer &TS = getTargetStreamer();
267 if (Subtarget->inMicroMipsMode())
268 TS.emitDirectiveSetMicroMips();
269 // leave out until FSF available gas has micromips changes
271 // TS.emitDirectiveSetNoMicroMips();
273 if (Subtarget->inMips16Mode())
274 TS.emitDirectiveSetMips16();
276 TS.emitDirectiveSetNoMips16();
278 TS.emitDirectiveEnt(*CurrentFnSym);
279 OutStreamer.EmitLabel(CurrentFnSym);
282 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
283 /// the first basic block in the function.
284 void MipsAsmPrinter::EmitFunctionBodyStart() {
285 MipsTargetStreamer &TS = getTargetStreamer();
287 MCInstLowering.Initialize(&MF->getContext());
289 bool IsNakedFunction =
291 getAttributes().hasAttribute(AttributeSet::FunctionIndex,
293 if (!IsNakedFunction)
294 emitFrameDirective();
296 if (OutStreamer.hasRawTextSupport()) {
297 SmallString<128> Str;
298 raw_svector_ostream OS(Str);
299 if (!IsNakedFunction)
300 printSavedRegsBitmask(OS);
301 OutStreamer.EmitRawText(OS.str());
303 if (!Subtarget->inMips16Mode()) {
304 TS.emitDirectiveSetNoReorder();
305 TS.emitDirectiveSetNoMacro();
306 TS.emitDirectiveSetNoAt();
310 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
311 /// the last basic block in the function.
312 void MipsAsmPrinter::EmitFunctionBodyEnd() {
313 MipsTargetStreamer &TS = getTargetStreamer();
315 // There are instruction for this macros, but they must
316 // always be at the function end, and we can't emit and
317 // break with BB logic.
318 if (!Subtarget->inMips16Mode()) {
319 TS.emitDirectiveSetAt();
320 TS.emitDirectiveSetMacro();
321 TS.emitDirectiveSetReorder();
323 TS.emitDirectiveEnd(CurrentFnSym->getName());
324 // Make sure to terminate any constant pools that were at the end
328 InConstantPool = false;
329 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
332 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
333 /// exactly one predecessor and the control transfer mechanism between
334 /// the predecessor and this block is a fall-through.
335 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
337 // The predecessor has to be immediately before this block.
338 const MachineBasicBlock *Pred = *MBB->pred_begin();
340 // If the predecessor is a switch statement, assume a jump table
341 // implementation, so it is not a fall through.
342 if (const BasicBlock *bb = Pred->getBasicBlock())
343 if (isa<SwitchInst>(bb->getTerminator()))
346 // If this is a landing pad, it isn't a fall through. If it has no preds,
347 // then nothing falls through to it.
348 if (MBB->isLandingPad() || MBB->pred_empty())
351 // If there isn't exactly one predecessor, it can't be a fall through.
352 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
355 if (PI2 != MBB->pred_end())
358 // The predecessor has to be immediately before this block.
359 if (!Pred->isLayoutSuccessor(MBB))
362 // If the block is completely empty, then it definitely does fall through.
366 // Otherwise, check the last instruction.
367 // Check if the last terminator is an unconditional branch.
368 MachineBasicBlock::const_iterator I = Pred->end();
369 while (I != Pred->begin() && !(--I)->isTerminator()) ;
371 return !I->isBarrier();
374 // Print out an operand for an inline asm expression.
375 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
376 unsigned AsmVariant,const char *ExtraCode,
378 // Does this asm operand have a single letter operand modifier?
379 if (ExtraCode && ExtraCode[0]) {
380 if (ExtraCode[1] != 0) return true; // Unknown modifier.
382 const MachineOperand &MO = MI->getOperand(OpNum);
383 switch (ExtraCode[0]) {
385 // See if this is a generic print operand
386 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
387 case 'X': // hex const int
388 if ((MO.getType()) != MachineOperand::MO_Immediate)
390 O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
392 case 'x': // hex const int (low 16 bits)
393 if ((MO.getType()) != MachineOperand::MO_Immediate)
395 O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
397 case 'd': // decimal const int
398 if ((MO.getType()) != MachineOperand::MO_Immediate)
402 case 'm': // decimal const int minus 1
403 if ((MO.getType()) != MachineOperand::MO_Immediate)
405 O << MO.getImm() - 1;
408 // $0 if zero, regular printing otherwise
409 if (MO.getType() != MachineOperand::MO_Immediate)
411 int64_t Val = MO.getImm();
418 case 'D': // Second part of a double word register operand
419 case 'L': // Low order register of a double word register operand
420 case 'M': // High order register of a double word register operand
424 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
425 if (!FlagsOP.isImm())
427 unsigned Flags = FlagsOP.getImm();
428 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
429 // Number of registers represented by this operand. We are looking
430 // for 2 for 32 bit mode and 1 for 64 bit mode.
432 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
433 unsigned Reg = MO.getReg();
434 O << '$' << MipsInstPrinter::getRegisterName(Reg);
440 unsigned RegOp = OpNum;
441 if (!Subtarget->isGP64bit()){
442 // Endianess reverses which register holds the high or low value
444 switch(ExtraCode[0]) {
446 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
449 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
451 case 'D': // Always the second part
454 if (RegOp >= MI->getNumOperands())
456 const MachineOperand &MO = MI->getOperand(RegOp);
459 unsigned Reg = MO.getReg();
460 O << '$' << MipsInstPrinter::getRegisterName(Reg);
465 // Print MSA registers for the 'f' constraint
466 // In LLVM, the 'w' modifier doesn't need to do anything.
467 // We can just call printOperand as normal.
472 printOperand(MI, OpNum, O);
476 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
477 unsigned OpNum, unsigned AsmVariant,
478 const char *ExtraCode,
481 // Currently we are expecting either no ExtraCode or 'D'
483 if (ExtraCode[0] == 'D')
486 return true; // Unknown modifier.
489 const MachineOperand &MO = MI->getOperand(OpNum);
490 assert(MO.isReg() && "unexpected inline asm memory operand");
491 O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
496 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
498 const DataLayout *DL = TM.getDataLayout();
499 const MachineOperand &MO = MI->getOperand(opNum);
502 if (MO.getTargetFlags())
505 switch(MO.getTargetFlags()) {
506 case MipsII::MO_GPREL: O << "%gp_rel("; break;
507 case MipsII::MO_GOT_CALL: O << "%call16("; break;
508 case MipsII::MO_GOT: O << "%got("; break;
509 case MipsII::MO_ABS_HI: O << "%hi("; break;
510 case MipsII::MO_ABS_LO: O << "%lo("; break;
511 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
512 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
513 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
514 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
515 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
516 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
517 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
518 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
519 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
522 switch (MO.getType()) {
523 case MachineOperand::MO_Register:
525 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
528 case MachineOperand::MO_Immediate:
532 case MachineOperand::MO_MachineBasicBlock:
533 O << *MO.getMBB()->getSymbol();
536 case MachineOperand::MO_GlobalAddress:
537 O << *getSymbol(MO.getGlobal());
540 case MachineOperand::MO_BlockAddress: {
541 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
546 case MachineOperand::MO_ConstantPoolIndex:
547 O << DL->getPrivateGlobalPrefix() << "CPI"
548 << getFunctionNumber() << "_" << MO.getIndex();
550 O << "+" << MO.getOffset();
554 llvm_unreachable("<unknown operand type>");
557 if (closeP) O << ")";
560 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
562 const MachineOperand &MO = MI->getOperand(opNum);
564 O << (unsigned short int)MO.getImm();
566 printOperand(MI, opNum, O);
569 void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum,
571 const MachineOperand &MO = MI->getOperand(opNum);
573 O << (unsigned short int)(unsigned char)MO.getImm();
575 printOperand(MI, opNum, O);
578 void MipsAsmPrinter::
579 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
580 // Load/Store memory operands -- imm($reg)
581 // If PIC target the target is loaded as the
582 // pattern lw $25,%call16($28)
583 printOperand(MI, opNum+1, O);
585 printOperand(MI, opNum, O);
589 void MipsAsmPrinter::
590 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
591 // when using stack locations for not load/store instructions
592 // print the same way as all normal 3 operand instructions.
593 printOperand(MI, opNum, O);
595 printOperand(MI, opNum+1, O);
599 void MipsAsmPrinter::
600 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
601 const char *Modifier) {
602 const MachineOperand &MO = MI->getOperand(opNum);
603 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
606 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
607 // TODO: Need to add -mabicalls and -mno-abicalls flags.
608 // Currently we assume that -mabicalls is the default.
609 getTargetStreamer().emitDirectiveAbiCalls();
610 Reloc::Model RM = Subtarget->getRelocationModel();
611 if (RM == Reloc::Static && !Subtarget->hasMips64())
612 getTargetStreamer().emitDirectiveOptionPic0();
614 // Tell the assembler which ABI we are using
615 std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
616 OutStreamer.SwitchSection(OutContext.getELFSection(
617 SectionName, ELF::SHT_PROGBITS, 0, SectionKind::getDataRel()));
619 // TODO: handle O64 ABI
621 if (Subtarget->isABI_EABI()) {
622 if (Subtarget->isGP32bit())
623 OutStreamer.SwitchSection(
624 OutContext.getELFSection(".gcc_compiled_long32", ELF::SHT_PROGBITS, 0,
625 SectionKind::getDataRel()));
627 OutStreamer.SwitchSection(
628 OutContext.getELFSection(".gcc_compiled_long64", ELF::SHT_PROGBITS, 0,
629 SectionKind::getDataRel()));
632 // return to the text section
633 OutStreamer.SwitchSection(OutContext.getObjectFileInfo()->getTextSection());
636 void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
637 // Emit Mips ELF register info
638 Subtarget->getMReginfo().emitMipsReginfoSectionCG(
639 OutStreamer, getObjFileLowering(), *Subtarget);
642 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
647 // Force static initialization.
648 extern "C" void LLVMInitializeMipsAsmPrinter() {
649 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
650 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
651 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
652 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);