1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-asm-printer"
16 #include "MipsAsmPrinter.h"
18 #include "MipsInstrInfo.h"
19 #include "InstPrinter/MipsInstPrinter.h"
20 #include "MCTargetDesc/MipsBaseInfo.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/StringExtras.h"
23 #include "llvm/ADT/Twine.h"
24 #include "llvm/Analysis/DebugInfo.h"
25 #include "llvm/BasicBlock.h"
26 #include "llvm/Instructions.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/MC/MCStreamer.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSymbol.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/Mangler.h"
40 #include "llvm/Target/TargetData.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 #include "llvm/Target/TargetOptions.h"
46 void MipsAsmPrinter::EmitInstrWithMacroNoAT(const MachineInstr *MI) {
49 MCInstLowering.Lower(MI, TmpInst);
50 OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
51 if (MipsFI->getEmitNOAT())
52 OutStreamer.EmitRawText(StringRef("\t.set\tat"));
53 OutStreamer.EmitInstruction(TmpInst);
54 if (MipsFI->getEmitNOAT())
55 OutStreamer.EmitRawText(StringRef("\t.set\tnoat"));
56 OutStreamer.EmitRawText(StringRef("\t.set\tnomacro"));
59 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
60 MipsFI = MF.getInfo<MipsFunctionInfo>();
61 AsmPrinter::runOnMachineFunction(MF);
65 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
66 if (MI->isDebugValue()) {
68 raw_svector_ostream OS(Str);
70 PrintDebugValueComment(MI, OS);
74 unsigned Opc = MI->getOpcode();
76 SmallVector<MCInst, 4> MCInsts;
102 case Mips::USH64_P8: {
103 if (OutStreamer.hasRawTextSupport()) {
104 EmitInstrWithMacroNoAT(MI);
108 MCInstLowering.LowerUnalignedLoadStore(MI, MCInsts);
109 for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin(); I
110 != MCInsts.end(); ++I)
111 OutStreamer.EmitInstruction(*I);
115 case Mips::CPRESTORE: {
116 const MachineOperand &MO = MI->getOperand(0);
117 assert(MO.isImm() && "CPRESTORE's operand must be an immediate.");
118 int64_t Offset = MO.getImm();
120 if (OutStreamer.hasRawTextSupport()) {
121 if (!isInt<16>(Offset)) {
122 EmitInstrWithMacroNoAT(MI);
126 MCInstLowering.LowerCPRESTORE(Offset, MCInsts);
128 for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
129 I != MCInsts.end(); ++I)
130 OutStreamer.EmitInstruction(*I);
141 MCInstLowering.Lower(MI, TmpInst0);
142 OutStreamer.EmitInstruction(TmpInst0);
145 //===----------------------------------------------------------------------===//
147 // Mips Asm Directives
149 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
150 // Describe the stack frame.
152 // -- Mask directives "(f)mask bitmask, offset"
153 // Tells the assembler which registers are saved and where.
154 // bitmask - contain a little endian bitset indicating which registers are
155 // saved on function prologue (e.g. with a 0x80000000 mask, the
156 // assembler knows the register 31 (RA) is saved at prologue.
157 // offset - the position before stack pointer subtraction indicating where
158 // the first saved register on prologue is located. (e.g. with a
160 // Consider the following function prologue:
163 // .mask 0xc0000000,-8
164 // addiu $sp, $sp, -48
168 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
169 // 30 (FP) are saved at prologue. As the save order on prologue is from
170 // left to right, RA is saved first. A -8 offset means that after the
171 // stack pointer subtration, the first register in the mask (RA) will be
172 // saved at address 48-8=40.
174 //===----------------------------------------------------------------------===//
176 //===----------------------------------------------------------------------===//
178 //===----------------------------------------------------------------------===//
180 // Create a bitmask with all callee saved registers for CPU or Floating Point
181 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
182 void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
183 // CPU and FPU Saved Registers Bitmasks
184 unsigned CPUBitmask = 0, FPUBitmask = 0;
185 int CPUTopSavedRegOff, FPUTopSavedRegOff;
187 // Set the CPU and FPU Bitmasks
188 const MachineFrameInfo *MFI = MF->getFrameInfo();
189 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
190 // size of stack area to which FP callee-saved regs are saved.
191 unsigned CPURegSize = Mips::CPURegsRegClass.getSize();
192 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
193 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
194 bool HasAFGR64Reg = false;
195 unsigned CSFPRegsSize = 0;
196 unsigned i, e = CSI.size();
199 for (i = 0; i != e; ++i) {
200 unsigned Reg = CSI[i].getReg();
201 if (Mips::CPURegsRegClass.contains(Reg))
204 unsigned RegNum = getMipsRegisterNumbering(Reg);
205 if (Mips::AFGR64RegClass.contains(Reg)) {
206 FPUBitmask |= (3 << RegNum);
207 CSFPRegsSize += AFGR64RegSize;
212 FPUBitmask |= (1 << RegNum);
213 CSFPRegsSize += FGR32RegSize;
217 for (; i != e; ++i) {
218 unsigned Reg = CSI[i].getReg();
219 unsigned RegNum = getMipsRegisterNumbering(Reg);
220 CPUBitmask |= (1 << RegNum);
223 // FP Regs are saved right below where the virtual frame pointer points to.
224 FPUTopSavedRegOff = FPUBitmask ?
225 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
227 // CPU Regs are saved below FP Regs.
228 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
231 O << "\t.mask \t"; printHex32(CPUBitmask, O);
232 O << ',' << CPUTopSavedRegOff << '\n';
235 O << "\t.fmask\t"; printHex32(FPUBitmask, O);
236 O << "," << FPUTopSavedRegOff << '\n';
239 // Print a 32 bit hex number with all numbers.
240 void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
242 for (int i = 7; i >= 0; i--)
243 O.write_hex((Value & (0xF << (i*4))) >> (i*4));
246 //===----------------------------------------------------------------------===//
247 // Frame and Set directives
248 //===----------------------------------------------------------------------===//
251 void MipsAsmPrinter::emitFrameDirective() {
252 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
254 unsigned stackReg = RI.getFrameRegister(*MF);
255 unsigned returnReg = RI.getRARegister();
256 unsigned stackSize = MF->getFrameInfo()->getStackSize();
258 if (OutStreamer.hasRawTextSupport())
259 OutStreamer.EmitRawText("\t.frame\t$" +
260 StringRef(MipsInstPrinter::getRegisterName(stackReg)).lower() +
261 "," + Twine(stackSize) + ",$" +
262 StringRef(MipsInstPrinter::getRegisterName(returnReg)).lower());
265 /// Emit Set directives.
266 const char *MipsAsmPrinter::getCurrentABIString() const {
267 switch (Subtarget->getTargetABI()) {
268 case MipsSubtarget::O32: return "abi32";
269 case MipsSubtarget::N32: return "abiN32";
270 case MipsSubtarget::N64: return "abi64";
271 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
272 default: llvm_unreachable("Unknown Mips ABI");;
276 void MipsAsmPrinter::EmitFunctionEntryLabel() {
277 if (OutStreamer.hasRawTextSupport())
278 OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName()));
279 OutStreamer.EmitLabel(CurrentFnSym);
282 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
283 /// the first basic block in the function.
284 void MipsAsmPrinter::EmitFunctionBodyStart() {
285 MCInstLowering.Initialize(Mang, &MF->getContext());
287 emitFrameDirective();
289 if (OutStreamer.hasRawTextSupport()) {
290 SmallString<128> Str;
291 raw_svector_ostream OS(Str);
292 printSavedRegsBitmask(OS);
293 OutStreamer.EmitRawText(OS.str());
295 OutStreamer.EmitRawText(StringRef("\t.set\tnoreorder"));
296 OutStreamer.EmitRawText(StringRef("\t.set\tnomacro"));
297 if (MipsFI->getEmitNOAT())
298 OutStreamer.EmitRawText(StringRef("\t.set\tnoat"));
301 if ((MF->getTarget().getRelocationModel() == Reloc::PIC_) &&
302 Subtarget->isABI_O32() && MipsFI->globalBaseRegSet()) {
303 SmallVector<MCInst, 4> MCInsts;
304 MCInstLowering.LowerSETGP01(MCInsts);
305 for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
306 I != MCInsts.end(); ++I)
307 OutStreamer.EmitInstruction(*I);
311 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
312 /// the last basic block in the function.
313 void MipsAsmPrinter::EmitFunctionBodyEnd() {
314 // There are instruction for this macros, but they must
315 // always be at the function end, and we can't emit and
316 // break with BB logic.
317 if (OutStreamer.hasRawTextSupport()) {
318 if (MipsFI->getEmitNOAT())
319 OutStreamer.EmitRawText(StringRef("\t.set\tat"));
321 OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
322 OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
323 OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
327 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
328 /// exactly one predecessor and the control transfer mechanism between
329 /// the predecessor and this block is a fall-through.
330 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
332 // The predecessor has to be immediately before this block.
333 const MachineBasicBlock *Pred = *MBB->pred_begin();
335 // If the predecessor is a switch statement, assume a jump table
336 // implementation, so it is not a fall through.
337 if (const BasicBlock *bb = Pred->getBasicBlock())
338 if (isa<SwitchInst>(bb->getTerminator()))
341 // If this is a landing pad, it isn't a fall through. If it has no preds,
342 // then nothing falls through to it.
343 if (MBB->isLandingPad() || MBB->pred_empty())
346 // If there isn't exactly one predecessor, it can't be a fall through.
347 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
350 if (PI2 != MBB->pred_end())
353 // The predecessor has to be immediately before this block.
354 if (!Pred->isLayoutSuccessor(MBB))
357 // If the block is completely empty, then it definitely does fall through.
361 // Otherwise, check the last instruction.
362 // Check if the last terminator is an unconditional branch.
363 MachineBasicBlock::const_iterator I = Pred->end();
364 while (I != Pred->begin() && !(--I)->isTerminator()) ;
366 return !I->isBarrier();
369 // Print out an operand for an inline asm expression.
370 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
371 unsigned AsmVariant,const char *ExtraCode,
373 // Does this asm operand have a single letter operand modifier?
374 if (ExtraCode && ExtraCode[0]) {
375 if (ExtraCode[1] != 0) return true; // Unknown modifier.
377 const MachineOperand &MO = MI->getOperand(OpNum);
378 switch (ExtraCode[0]) {
380 return true; // Unknown modifier.
381 case 'X': // hex const int
382 if ((MO.getType()) != MachineOperand::MO_Immediate)
384 O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
389 printOperand(MI, OpNum, O);
393 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
394 unsigned OpNum, unsigned AsmVariant,
395 const char *ExtraCode,
397 if (ExtraCode && ExtraCode[0])
398 return true; // Unknown modifier.
400 const MachineOperand &MO = MI->getOperand(OpNum);
401 assert(MO.isReg() && "unexpected inline asm memory operand");
402 O << "0($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
406 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
408 const MachineOperand &MO = MI->getOperand(opNum);
411 if (MO.getTargetFlags())
414 switch(MO.getTargetFlags()) {
415 case MipsII::MO_GPREL: O << "%gp_rel("; break;
416 case MipsII::MO_GOT_CALL: O << "%call16("; break;
417 case MipsII::MO_GOT: O << "%got("; break;
418 case MipsII::MO_ABS_HI: O << "%hi("; break;
419 case MipsII::MO_ABS_LO: O << "%lo("; break;
420 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
421 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
422 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
423 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
424 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
425 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
426 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
427 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
428 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
431 switch (MO.getType()) {
432 case MachineOperand::MO_Register:
434 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
437 case MachineOperand::MO_Immediate:
441 case MachineOperand::MO_MachineBasicBlock:
442 O << *MO.getMBB()->getSymbol();
445 case MachineOperand::MO_GlobalAddress:
446 O << *Mang->getSymbol(MO.getGlobal());
449 case MachineOperand::MO_BlockAddress: {
450 MCSymbol* BA = GetBlockAddressSymbol(MO.getBlockAddress());
455 case MachineOperand::MO_ExternalSymbol:
456 O << *GetExternalSymbolSymbol(MO.getSymbolName());
459 case MachineOperand::MO_JumpTableIndex:
460 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
461 << '_' << MO.getIndex();
464 case MachineOperand::MO_ConstantPoolIndex:
465 O << MAI->getPrivateGlobalPrefix() << "CPI"
466 << getFunctionNumber() << "_" << MO.getIndex();
468 O << "+" << MO.getOffset();
472 llvm_unreachable("<unknown operand type>");
475 if (closeP) O << ")";
478 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
480 const MachineOperand &MO = MI->getOperand(opNum);
482 O << (unsigned short int)MO.getImm();
484 printOperand(MI, opNum, O);
487 void MipsAsmPrinter::
488 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
489 // Load/Store memory operands -- imm($reg)
490 // If PIC target the target is loaded as the
491 // pattern lw $25,%call16($28)
492 printOperand(MI, opNum+1, O);
494 printOperand(MI, opNum, O);
498 void MipsAsmPrinter::
499 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
500 // when using stack locations for not load/store instructions
501 // print the same way as all normal 3 operand instructions.
502 printOperand(MI, opNum, O);
504 printOperand(MI, opNum+1, O);
508 void MipsAsmPrinter::
509 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
510 const char *Modifier) {
511 const MachineOperand& MO = MI->getOperand(opNum);
512 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
515 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
516 // FIXME: Use SwitchSection.
518 // Tell the assembler which ABI we are using
519 if (OutStreamer.hasRawTextSupport())
520 OutStreamer.EmitRawText("\t.section .mdebug." +
521 Twine(getCurrentABIString()));
523 // TODO: handle O64 ABI
524 if (OutStreamer.hasRawTextSupport()) {
525 if (Subtarget->isABI_EABI()) {
526 if (Subtarget->isGP32bit())
527 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32"));
529 OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64"));
533 // return to previous section
534 if (OutStreamer.hasRawTextSupport())
535 OutStreamer.EmitRawText(StringRef("\t.previous"));
539 MipsAsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
540 // Handles frame addresses emitted in MipsInstrInfo::emitFrameIndexDebugValue.
541 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
542 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
543 "Unexpected MachineOperand types");
544 return MachineLocation(MI->getOperand(0).getReg(),
545 MI->getOperand(1).getImm());
548 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
553 // Force static initialization.
554 extern "C" void LLVMInitializeMipsAsmPrinter() {
555 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
556 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
557 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
558 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);