1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for Mips architecture.
10 //===----------------------------------------------------------------------===//
12 /// CCIfSubtarget - Match if the current subtarget has a feature F.
13 class CCIfSubtarget<string F, CCAction A>
14 : CCIf<!strconcat("static_cast<const MipsSubtarget&>"
15 "(State.getMachineFunction().getSubtarget()).",
19 //===----------------------------------------------------------------------===//
20 // Mips O32 Calling Convention
21 //===----------------------------------------------------------------------===//
23 // Only the return rules are defined here for O32. The rules for argument
24 // passing are defined in MipsISelLowering.cpp.
25 def RetCC_MipsO32 : CallingConv<[
26 // i32 are returned in registers V0, V1, A0, A1
27 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>,
29 // f32 are returned in registers F0, F2
30 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
32 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
33 // in D0 and D1 in FP32bit mode.
34 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>,
35 CCIfType<[f64], CCIfSubtarget<"isNotFP64bit()", CCAssignToReg<[D0, D1]>>>
38 //===----------------------------------------------------------------------===//
39 // Mips N32/64 Calling Convention
40 //===----------------------------------------------------------------------===//
42 def CC_MipsN : CallingConv<[
43 // Promote i8/i16 arguments to i32.
44 CCIfType<[i8, i16], CCPromoteToType<i32>>,
46 // Integer arguments are passed in integer registers.
47 CCIfType<[i32], CCAssignToRegWithShadow<[A0, A1, A2, A3,
50 F16, F17, F18, F19]>>,
52 CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
53 T0_64, T1_64, T2_64, T3_64],
54 [D12_64, D13_64, D14_64, D15_64,
55 D16_64, D17_64, D18_64, D19_64]>>,
57 // f32 arguments are passed in single precision FP registers.
58 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,
60 [A0_64, A1_64, A2_64, A3_64,
61 T0_64, T1_64, T2_64, T3_64]>>,
63 // f64 arguments are passed in double precision FP registers.
64 CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64,
65 D16_64, D17_64, D18_64, D19_64],
66 [A0_64, A1_64, A2_64, A3_64,
67 T0_64, T1_64, T2_64, T3_64]>>,
69 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
70 CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
71 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
74 // N32/64 variable arguments.
75 // All arguments are passed in integer registers.
76 def CC_MipsN_VarArg : CallingConv<[
77 // Promote i8/i16 arguments to i32.
78 CCIfType<[i8, i16], CCPromoteToType<i32>>,
80 CCIfType<[i32, f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
82 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
83 T0_64, T1_64, T2_64, T3_64]>>,
85 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
86 CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
87 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
90 def RetCC_MipsN : CallingConv<[
91 // i32 are returned in registers V0, V1
92 CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
94 // i64 are returned in registers V0_64, V1_64
95 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>,
97 // f32 are returned in registers F0, F2
98 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
100 // f64 are returned in registers D0, D2
101 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>
104 // In soft-mode, register A0_64, instead of V1_64, is used to return a long
106 def RetCC_F128Soft : CallingConv<[
107 CCIfType<[i64], CCAssignToReg<[V0_64, A0_64]>>
110 //===----------------------------------------------------------------------===//
111 // Mips EABI Calling Convention
112 //===----------------------------------------------------------------------===//
114 def CC_MipsEABI : CallingConv<[
115 // Promote i8/i16 arguments to i32.
116 CCIfType<[i8, i16], CCPromoteToType<i32>>,
118 // Integer arguments are passed in integer registers.
119 CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
121 // Single fp arguments are passed in pairs within 32-bit mode
122 CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
123 CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>,
125 CCIfType<[f32], CCIfSubtarget<"isNotSingleFloat()",
126 CCAssignToReg<[F12, F14, F16, F18]>>>,
128 // The first 4 double fp arguments are passed in single fp registers.
129 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()",
130 CCAssignToReg<[D6, D7, D8, D9]>>>,
132 // Integer values get stored in stack slots that are 4 bytes in
133 // size and 4-byte aligned.
134 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
136 // Integer values get stored in stack slots that are 8 bytes in
137 // size and 8-byte aligned.
138 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToStack<8, 8>>>
141 def RetCC_MipsEABI : CallingConv<[
142 // i32 are returned in registers V0, V1
143 CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
145 // f32 are returned in registers F0, F1
146 CCIfType<[f32], CCAssignToReg<[F0, F1]>>,
148 // f64 are returned in register D0
149 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0]>>>
152 //===----------------------------------------------------------------------===//
153 // Mips FastCC Calling Convention
154 //===----------------------------------------------------------------------===//
155 def CC_MipsO32_FastCC : CallingConv<[
156 // f64 arguments are passed in double-precision floating pointer registers.
157 CCIfType<[f64], CCIfSubtarget<"isNotFP64bit()",
158 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7,
160 CCIfType<[f64], CCIfSubtarget<"isFP64bit()",
161 CCAssignToReg<[D0_64, D1_64, D2_64, D3_64,
162 D4_64, D5_64, D6_64, D7_64,
163 D8_64, D9_64, D10_64, D11_64,
164 D12_64, D13_64, D14_64, D15_64,
165 D16_64, D17_64, D18_64,
168 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned.
169 CCIfType<[f64], CCAssignToStack<8, 8>>
172 def CC_MipsN_FastCC : CallingConv<[
173 // Integer arguments are passed in integer registers.
174 CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64,
175 T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
178 // f64 arguments are passed in double-precision floating pointer registers.
179 CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64,
180 D6_64, D7_64, D8_64, D9_64, D10_64, D11_64,
181 D12_64, D13_64, D14_64, D15_64, D16_64, D17_64,
184 // Stack parameter slots for i64 and f64 are 64-bit doublewords and
186 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
189 def CC_Mips_FastCC : CallingConv<[
190 // Handles byval parameters.
191 CCIfByVal<CCPassByVal<4, 4>>,
193 // Promote i8/i16 arguments to i32.
194 CCIfType<[i8, i16], CCPromoteToType<i32>>,
196 // Integer arguments are passed in integer registers. All scratch registers,
197 // except for AT, V0 and T9, are available to be used as argument registers.
198 CCIfType<[i32], CCIfSubtarget<"isNotTargetNaCl()",
199 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>,
201 // In NaCl, T6, T7 and T8 are reserved and not available as argument
202 // registers for fastcc. T6 contains the mask for sandboxing control flow
203 // (indirect jumps and calls). T7 contains the mask for sandboxing memory
204 // accesses (loads and stores). T8 contains the thread pointer.
205 CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()",
206 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>,
208 // f32 arguments are passed in single-precision floating pointer registers.
209 CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",
210 CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13,
211 F14, F15, F16, F17, F18, F19]>>>,
213 // Don't use odd numbered single-precision registers for -mno-odd-spreg.
214 CCIfType<[f32], CCIfSubtarget<"noOddSPReg()",
215 CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>,
217 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
218 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
220 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
221 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,
222 CCDelegateTo<CC_MipsN_FastCC>
227 def CC_Mips16RetHelper : CallingConv<[
228 // Integer arguments are passed in integer registers.
229 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
232 //===----------------------------------------------------------------------===//
233 // Mips Calling Convention Dispatch
234 //===----------------------------------------------------------------------===//
236 def RetCC_Mips : CallingConv<[
237 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>,
238 CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
239 CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
240 CCDelegateTo<RetCC_MipsO32>
243 //===----------------------------------------------------------------------===//
244 // Callee-saved register lists.
245 //===----------------------------------------------------------------------===//
247 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
248 (sequence "S%u", 7, 0))>;
250 def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
251 (sequence "S%u", 7, 0))> {
252 let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2));
255 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
256 (sequence "S%u", 7, 0))>;
259 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
260 (sequence "S%u", 7, 0))>;
262 def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64,
263 D30_64, RA_64, FP_64, GP_64,
264 (sequence "S%u_64", 7, 0))>;
266 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
267 GP_64, (sequence "S%u_64", 7, 0))>;
269 def CSR_Mips16RetHelper :
270 CalleeSavedRegs<(add V0, V1, FP,
271 (sequence "A%u", 3, 0), (sequence "S%u", 7, 0),
272 (sequence "D%u", 15, 10))>;