1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for Mips architecture.
10 //===----------------------------------------------------------------------===//
12 /// CCIfSubtarget - Match if the current subtarget has a feature F.
13 class CCIfSubtarget<string F, CCAction A, string Invert = "">
14 : CCIf<!strconcat(Invert,
15 "static_cast<const MipsSubtarget&>"
16 "(State.getMachineFunction().getSubtarget()).",
20 // The inverse of CCIfSubtarget
21 class CCIfSubtargetNot<string F, CCAction A> : CCIfSubtarget<F, A, "!">;
23 // For soft-float, f128 values are returned in A0_64 rather than V1_64.
24 def RetCC_F128SoftFloat : CallingConv<[
25 CCAssignToReg<[V0_64, A0_64]>
28 // For hard-float, f128 values are returned as a pair of f64's rather than a
30 def RetCC_F128HardFloat : CallingConv<[
31 CCBitConvertToType<f64>,
33 // Contrary to the ABI documentation, a struct containing a long double is
34 // returned in $f0, and $f1 instead of the usual $f0, and $f2. This is to
35 // match the de facto ABI as implemented by GCC.
36 CCIfInReg<CCAssignToReg<[D0_64, D1_64]>>,
38 CCAssignToReg<[D0_64, D2_64]>
41 // Handle F128 specially since we can't identify the original type during the
42 // tablegen-erated code.
43 def RetCC_F128 : CallingConv<[
44 CCIfSubtarget<"abiUsesSoftFloat()",
45 CCIfType<[i64], CCDelegateTo<RetCC_F128SoftFloat>>>,
46 CCIfSubtargetNot<"abiUsesSoftFloat()",
47 CCIfType<[i64], CCDelegateTo<RetCC_F128HardFloat>>>
50 //===----------------------------------------------------------------------===//
51 // Mips O32 Calling Convention
52 //===----------------------------------------------------------------------===//
54 def CC_MipsO32 : CallingConv<[
55 // Promote i8/i16 arguments to i32.
56 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
58 // Integer values get stored in stack slots that are 4 bytes in
59 // size and 4-byte aligned.
60 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
62 // Integer values get stored in stack slots that are 8 bytes in
63 // size and 8-byte aligned.
64 CCIfType<[f64], CCAssignToStack<8, 8>>
67 // Only the return rules are defined here for O32. The rules for argument
68 // passing are defined in MipsISelLowering.cpp.
69 def RetCC_MipsO32 : CallingConv<[
70 // i32 are returned in registers V0, V1, A0, A1
71 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>,
73 // f32 are returned in registers F0, F2
74 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
76 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
77 // in D0 and D1 in FP32bit mode.
78 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>,
79 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", CCAssignToReg<[D0, D1]>>>
82 def CC_MipsO32_FP32 : CustomCallingConv;
83 def CC_MipsO32_FP64 : CustomCallingConv;
85 def CC_MipsO32_FP : CallingConv<[
86 CCIfSubtargetNot<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP32>>,
87 CCIfSubtarget<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP64>>
90 //===----------------------------------------------------------------------===//
91 // Mips N32/64 Calling Convention
92 //===----------------------------------------------------------------------===//
94 def CC_MipsN_SoftFloat : CallingConv<[
95 CCAssignToRegWithShadow<[A0, A1, A2, A3,
97 [D12_64, D13_64, D14_64, D15_64,
98 D16_64, D17_64, D18_64, D19_64]>,
102 def CC_MipsN : CallingConv<[
103 CCIfType<[i8, i16, i32],
104 CCIfSubtargetNot<"isLittle()",
105 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,
107 // All integers (except soft-float integers) are promoted to 64-bit.
108 CCIfType<[i8, i16, i32],
109 CCIf<"!static_cast<MipsCCState *>(&State)->WasOriginalArgFloat(ValNo)",
110 CCPromoteToType<i64>>>,
112 // The only i32's we have left are soft-float arguments.
113 CCIfSubtarget<"abiUsesSoftFloat()", CCIfType<[i32], CCDelegateTo<CC_MipsN_SoftFloat>>>,
115 // Integer arguments are passed in integer registers.
116 CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
117 T0_64, T1_64, T2_64, T3_64],
118 [D12_64, D13_64, D14_64, D15_64,
119 D16_64, D17_64, D18_64, D19_64]>>,
121 // f32 arguments are passed in single precision FP registers.
122 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,
124 [A0_64, A1_64, A2_64, A3_64,
125 T0_64, T1_64, T2_64, T3_64]>>,
127 // f64 arguments are passed in double precision FP registers.
128 CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64,
129 D16_64, D17_64, D18_64, D19_64],
130 [A0_64, A1_64, A2_64, A3_64,
131 T0_64, T1_64, T2_64, T3_64]>>,
133 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
134 CCIfType<[f32], CCAssignToStack<4, 8>>,
135 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
138 // N32/64 variable arguments.
139 // All arguments are passed in integer registers.
140 def CC_MipsN_VarArg : CallingConv<[
141 // All integers are promoted to 64-bit.
142 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
144 CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
146 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
147 T0_64, T1_64, T2_64, T3_64]>>,
149 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
150 CCIfType<[f32], CCAssignToStack<4, 8>>,
151 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
154 def RetCC_MipsN : CallingConv<[
155 // f128 needs to be handled similarly to f32 and f64. However, f128 is not
156 // legal and is lowered to i128 which is further lowered to a pair of i64's.
157 // This presents us with a problem for the calling convention since hard-float
158 // still needs to pass them in FPU registers, and soft-float needs to use $v0,
159 // and $a0 instead of the usual $v0, and $v1. We therefore resort to a
160 // pre-analyze (see PreAnalyzeReturnForF128()) step to pass information on
161 // whether the result was originally an f128 into the tablegen-erated code.
163 // f128 should only occur for the N64 ABI where long double is 128-bit. On
164 // N32, long double is equivalent to double.
166 CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)",
167 CCDelegateTo<RetCC_F128>>>,
169 // Aggregate returns are positioned at the lowest address in the slot for
170 // both little and big-endian targets. When passing in registers, this
171 // requires that big-endian targets shift the value into the upper bits.
172 CCIfSubtarget<"isLittle()",
173 CCIfType<[i8, i16, i32, i64], CCIfInReg<CCPromoteToType<i64>>>>,
174 CCIfSubtargetNot<"isLittle()",
175 CCIfType<[i8, i16, i32, i64],
176 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,
178 // i64 are returned in registers V0_64, V1_64
179 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>,
181 // f32 are returned in registers F0, F2
182 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
184 // f64 are returned in registers D0, D2
185 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>
188 //===----------------------------------------------------------------------===//
189 // Mips EABI Calling Convention
190 //===----------------------------------------------------------------------===//
192 def CC_MipsEABI : CallingConv<[
193 // Promote i8/i16 arguments to i32.
194 CCIfType<[i8, i16], CCPromoteToType<i32>>,
196 // Integer arguments are passed in integer registers.
197 CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
199 // Single fp arguments are passed in pairs within 32-bit mode
200 CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
201 CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>,
203 CCIfType<[f32], CCIfSubtargetNot<"isSingleFloat()",
204 CCAssignToReg<[F12, F14, F16, F18]>>>,
206 // The first 4 double fp arguments are passed in single fp registers.
207 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()",
208 CCAssignToReg<[D6, D7, D8, D9]>>>,
210 // Integer values get stored in stack slots that are 4 bytes in
211 // size and 4-byte aligned.
212 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
214 // Integer values get stored in stack slots that are 8 bytes in
215 // size and 8-byte aligned.
216 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToStack<8, 8>>>
219 def RetCC_MipsEABI : CallingConv<[
220 // i32 are returned in registers V0, V1
221 CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
223 // f32 are returned in registers F0, F1
224 CCIfType<[f32], CCAssignToReg<[F0, F1]>>,
226 // f64 are returned in register D0
227 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToReg<[D0]>>>
230 //===----------------------------------------------------------------------===//
231 // Mips FastCC Calling Convention
232 //===----------------------------------------------------------------------===//
233 def CC_MipsO32_FastCC : CallingConv<[
234 // f64 arguments are passed in double-precision floating pointer registers.
235 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()",
236 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6,
238 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"useOddSPReg()",
239 CCAssignToReg<[D0_64, D1_64, D2_64, D3_64,
240 D4_64, D5_64, D6_64, D7_64,
241 D8_64, D9_64, D10_64, D11_64,
242 D12_64, D13_64, D14_64, D15_64,
243 D16_64, D17_64, D18_64,
245 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"noOddSPReg()",
246 CCAssignToReg<[D0_64, D2_64, D4_64, D6_64,
247 D8_64, D10_64, D12_64, D14_64,
250 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned.
251 CCIfType<[f64], CCAssignToStack<8, 8>>
254 def CC_MipsN_FastCC : CallingConv<[
255 // Integer arguments are passed in integer registers.
256 CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64,
257 T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
260 // f64 arguments are passed in double-precision floating pointer registers.
261 CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64,
262 D6_64, D7_64, D8_64, D9_64, D10_64, D11_64,
263 D12_64, D13_64, D14_64, D15_64, D16_64, D17_64,
266 // Stack parameter slots for i64 and f64 are 64-bit doublewords and
268 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
271 def CC_Mips_FastCC : CallingConv<[
272 // Handles byval parameters.
273 CCIfByVal<CCPassByVal<4, 4>>,
275 // Promote i8/i16 arguments to i32.
276 CCIfType<[i8, i16], CCPromoteToType<i32>>,
278 // Integer arguments are passed in integer registers. All scratch registers,
279 // except for AT, V0 and T9, are available to be used as argument registers.
280 CCIfType<[i32], CCIfSubtargetNot<"isTargetNaCl()",
281 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>,
283 // In NaCl, T6, T7 and T8 are reserved and not available as argument
284 // registers for fastcc. T6 contains the mask for sandboxing control flow
285 // (indirect jumps and calls). T7 contains the mask for sandboxing memory
286 // accesses (loads and stores). T8 contains the thread pointer.
287 CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()",
288 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>,
290 // f32 arguments are passed in single-precision floating pointer registers.
291 CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",
292 CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13,
293 F14, F15, F16, F17, F18, F19]>>>,
295 // Don't use odd numbered single-precision registers for -mno-odd-spreg.
296 CCIfType<[f32], CCIfSubtarget<"noOddSPReg()",
297 CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>,
299 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
300 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
302 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
303 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,
304 CCDelegateTo<CC_MipsN_FastCC>
307 //===----------------------------------------------------------------------===//
308 // Mips Calling Convention Dispatch
309 //===----------------------------------------------------------------------===//
311 def RetCC_Mips : CallingConv<[
312 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>,
313 CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
314 CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
315 CCDelegateTo<RetCC_MipsO32>
318 def CC_Mips_ByVal : CallingConv<[
319 CCIfSubtarget<"isABI_O32()", CCIfByVal<CCPassByVal<4, 4>>>,
320 CCIfByVal<CCPassByVal<8, 8>>
323 def CC_Mips16RetHelper : CallingConv<[
324 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
326 // Integer arguments are passed in integer registers.
327 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
330 def CC_Mips_FixedArg : CallingConv<[
331 // Mips16 needs special handling on some functions.
332 CCIf<"State.getCallingConv() != CallingConv::Fast",
333 CCIf<"static_cast<MipsCCState *>(&State)->getSpecialCallingConv() == "
334 "MipsCCState::Mips16RetHelperConv",
335 CCDelegateTo<CC_Mips16RetHelper>>>,
337 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
339 // f128 needs to be handled similarly to f32 and f64 on hard-float. However,
340 // f128 is not legal and is lowered to i128 which is further lowered to a pair
342 // This presents us with a problem for the calling convention since hard-float
343 // still needs to pass them in FPU registers. We therefore resort to a
344 // pre-analyze (see PreAnalyzeFormalArgsForF128()) step to pass information on
345 // whether the argument was originally an f128 into the tablegen-erated code.
347 // f128 should only occur for the N64 ABI where long double is 128-bit. On
348 // N32, long double is equivalent to double.
350 CCIfSubtargetNot<"abiUsesSoftFloat()",
351 CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)",
352 CCBitConvertToType<f64>>>>,
354 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>,
356 // FIXME: There wasn't an EABI case in the original code and it seems unlikely
357 // that it's the same as CC_MipsN
358 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
359 CCDelegateTo<CC_MipsN>
362 def CC_Mips_VarArg : CallingConv<[
363 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
365 // FIXME: There wasn't an EABI case in the original code and it seems unlikely
366 // that it's the same as CC_MipsN_VarArg
367 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
368 CCDelegateTo<CC_MipsN_VarArg>
371 def CC_Mips : CallingConv<[
373 CCIf<"!static_cast<MipsCCState *>(&State)->IsCallOperandFixed(ValNo)",
374 CCDelegateTo<CC_Mips_VarArg>>>,
375 CCDelegateTo<CC_Mips_FixedArg>
378 //===----------------------------------------------------------------------===//
379 // Callee-saved register lists.
380 //===----------------------------------------------------------------------===//
382 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
383 (sequence "S%u", 7, 0))>;
385 def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
386 (sequence "S%u", 7, 0))> {
387 let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2));
390 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
391 (sequence "S%u", 7, 0))>;
394 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
395 (sequence "S%u", 7, 0))>;
397 def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64,
398 D30_64, RA_64, FP_64, GP_64,
399 (sequence "S%u_64", 7, 0))>;
401 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
402 GP_64, (sequence "S%u_64", 7, 0))>;
404 def CSR_Mips16RetHelper :
405 CalleeSavedRegs<(add V0, V1, FP,
406 (sequence "A%u", 3, 0), (sequence "S%u", 7, 0),
407 (sequence "D%u", 15, 10))>;