1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for Mips architecture.
10 //===----------------------------------------------------------------------===//
12 /// CCIfSubtarget - Match if the current subtarget has a feature F.
13 class CCIfSubtarget<string F, CCAction A>:
14 CCIf<!strconcat("State.getTarget().getSubtarget<MipsSubtarget>().", F), A>;
16 //===----------------------------------------------------------------------===//
17 // Mips O32 Calling Convention
18 //===----------------------------------------------------------------------===//
20 // Only the return rules are defined here for O32. The rules for argument
21 // passing are defined in MipsISelLowering.cpp.
22 def RetCC_MipsO32 : CallingConv<[
23 // i32 are returned in registers V0, V1, A0, A1
24 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>,
26 // f32 are returned in registers F0, F2
27 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
29 // f64 are returned in register D0, D1
30 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0, D1]>>>
33 //===----------------------------------------------------------------------===//
34 // Mips N32/64 Calling Convention
35 //===----------------------------------------------------------------------===//
37 def CC_MipsN : CallingConv<[
38 // Promote i8/i16 arguments to i32.
39 CCIfType<[i8, i16], CCPromoteToType<i32>>,
41 // Integer arguments are passed in integer registers.
42 CCIfType<[i32], CCAssignToRegWithShadow<[A0, A1, A2, A3,
45 F16, F17, F18, F19]>>,
47 CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
48 T0_64, T1_64, T2_64, T3_64],
49 [D12_64, D13_64, D14_64, D15_64,
50 D16_64, D17_64, D18_64, D19_64]>>,
52 // f32 arguments are passed in single precision FP registers.
53 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,
55 [A0_64, A1_64, A2_64, A3_64,
56 T0_64, T1_64, T2_64, T3_64]>>,
58 // f64 arguments are passed in double precision FP registers.
59 CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64,
60 D16_64, D17_64, D18_64, D19_64],
61 [A0_64, A1_64, A2_64, A3_64,
62 T0_64, T1_64, T2_64, T3_64]>>,
64 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
65 CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
66 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
69 // N32/64 variable arguments.
70 // All arguments are passed in integer registers.
71 def CC_MipsN_VarArg : CallingConv<[
72 // Promote i8/i16 arguments to i32.
73 CCIfType<[i8, i16], CCPromoteToType<i32>>,
75 CCIfType<[i32, f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
77 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
78 T0_64, T1_64, T2_64, T3_64]>>,
80 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
81 CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
82 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
85 def RetCC_MipsN : CallingConv<[
86 // i32 are returned in registers V0, V1
87 CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
89 // i64 are returned in registers V0_64, V1_64
90 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>,
92 // f32 are returned in registers F0, F2
93 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
95 // f64 are returned in registers D0, D2
96 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>
99 //===----------------------------------------------------------------------===//
100 // Mips EABI Calling Convention
101 //===----------------------------------------------------------------------===//
103 def CC_MipsEABI : CallingConv<[
104 // Promote i8/i16 arguments to i32.
105 CCIfType<[i8, i16], CCPromoteToType<i32>>,
107 // Integer arguments are passed in integer registers.
108 CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
110 // Single fp arguments are passed in pairs within 32-bit mode
111 CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
112 CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>,
114 CCIfType<[f32], CCIfSubtarget<"isNotSingleFloat()",
115 CCAssignToReg<[F12, F14, F16, F18]>>>,
117 // The first 4 double fp arguments are passed in single fp registers.
118 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()",
119 CCAssignToReg<[D6, D7, D8, D9]>>>,
121 // Integer values get stored in stack slots that are 4 bytes in
122 // size and 4-byte aligned.
123 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
125 // Integer values get stored in stack slots that are 8 bytes in
126 // size and 8-byte aligned.
127 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToStack<8, 8>>>
130 def RetCC_MipsEABI : CallingConv<[
131 // i32 are returned in registers V0, V1
132 CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
134 // f32 are returned in registers F0, F1
135 CCIfType<[f32], CCAssignToReg<[F0, F1]>>,
137 // f64 are returned in register D0
138 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0]>>>
141 //===----------------------------------------------------------------------===//
142 // Mips Android Calling Convention
143 //===----------------------------------------------------------------------===//
145 def RetCC_MipsAndroid : CallingConv<[
146 // f32 are returned in registers F0, F2, F1, F3
147 CCIfType<[f32], CCAssignToReg<[F0, F2, F1, F3]>>,
149 CCDelegateTo<RetCC_MipsO32>
152 //===----------------------------------------------------------------------===//
153 // Mips FastCC Calling Convention
154 //===----------------------------------------------------------------------===//
155 def CC_MipsO32_FastCC : CallingConv<[
156 // f64 arguments are passed in double-precision floating pointer registers.
157 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7, D8, D9]>>,
159 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned.
160 CCIfType<[f64], CCAssignToStack<8, 8>>
163 def CC_MipsN_FastCC : CallingConv<[
164 // Integer arguments are passed in integer registers.
165 CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64,
166 T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
169 // f64 arguments are passed in double-precision floating pointer registers.
170 CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64,
171 D6_64, D7_64, D8_64, D9_64, D10_64, D11_64,
172 D12_64, D13_64, D14_64, D15_64, D16_64, D17_64,
175 // Stack parameter slots for i64 and f64 are 64-bit doublewords and
177 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
180 def CC_Mips_FastCC : CallingConv<[
181 // Handles byval parameters.
182 CCIfByVal<CCPassByVal<4, 4>>,
184 // Promote i8/i16 arguments to i32.
185 CCIfType<[i8, i16], CCPromoteToType<i32>>,
187 // Integer arguments are passed in integer registers. All scratch registers,
188 // except for AT, V0 and T9, are available to be used as argument registers.
189 CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6,
192 // f32 arguments are passed in single-precision floating pointer registers.
193 CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10,
194 F11, F12, F13, F14, F15, F16, F17, F18, F19]>>,
196 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
197 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
199 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
200 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,
201 CCDelegateTo<CC_MipsN_FastCC>
204 //===----------------------------------------------------------------------===//
205 // Mips Calling Convention Dispatch
206 //===----------------------------------------------------------------------===//
208 def RetCC_Mips : CallingConv<[
209 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>,
210 CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
211 CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
212 CCIfSubtarget<"isAndroid()", CCDelegateTo<RetCC_MipsAndroid>>,
213 CCDelegateTo<RetCC_MipsO32>
216 //===----------------------------------------------------------------------===//
217 // Callee-saved register lists.
218 //===----------------------------------------------------------------------===//
220 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
221 (sequence "S%u", 7, 0))>;
223 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
224 (sequence "S%u", 7, 0))>;
226 def CSR_N32 : CalleeSavedRegs<(add D31_64, D29_64, D27_64, D25_64, D24_64,
227 D23_64, D22_64, D21_64, RA_64, FP_64, GP_64,
228 (sequence "S%u_64", 7, 0))>;
230 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
231 GP_64, (sequence "S%u_64", 7, 0))>;