1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for Mips architecture.
10 //===----------------------------------------------------------------------===//
12 /// CCIfSubtarget - Match if the current subtarget has a feature F.
13 class CCIfSubtarget<string F, CCAction A>:
14 CCIf<!strconcat("State.getTarget().getSubtarget<MipsSubtarget>().", F), A>;
16 //===----------------------------------------------------------------------===//
17 // Mips O32 Calling Convention
18 //===----------------------------------------------------------------------===//
20 // Only the return rules are defined here for O32. The rules for argument
21 // passing are defined in MipsISelLowering.cpp.
22 def RetCC_MipsO32 : CallingConv<[
23 // i32 are returned in registers V0, V1, A0, A1
24 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>,
26 // f32 are returned in registers F0, F2
27 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
29 // f64 are returned in register D0, D1
30 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0, D1]>>>
33 //===----------------------------------------------------------------------===//
34 // Mips N32/64 Calling Convention
35 //===----------------------------------------------------------------------===//
37 def CC_MipsN : CallingConv<[
38 // Handles byval parameters.
39 CCIfByVal<CCCustom<"CC_Mips64Byval">>,
41 // Promote i8/i16 arguments to i32.
42 CCIfType<[i8, i16], CCPromoteToType<i32>>,
44 // Integer arguments are passed in integer registers.
45 CCIfType<[i32], CCAssignToRegWithShadow<[A0, A1, A2, A3,
48 F16, F17, F18, F19]>>,
50 CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
51 T0_64, T1_64, T2_64, T3_64],
52 [D12_64, D13_64, D14_64, D15_64,
53 D16_64, D17_64, D18_64, D19_64]>>,
55 // f32 arguments are passed in single precision FP registers.
56 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,
58 [A0_64, A1_64, A2_64, A3_64,
59 T0_64, T1_64, T2_64, T3_64]>>,
61 // f64 arguments are passed in double precision FP registers.
62 CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64,
63 D16_64, D17_64, D18_64, D19_64],
64 [A0_64, A1_64, A2_64, A3_64,
65 T0_64, T1_64, T2_64, T3_64]>>,
67 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
68 CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
69 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
72 // N32/64 variable arguments.
73 // All arguments are passed in integer registers.
74 def CC_MipsN_VarArg : CallingConv<[
75 // Handles byval parameters.
76 CCIfByVal<CCCustom<"CC_Mips64Byval">>,
78 // Promote i8/i16 arguments to i32.
79 CCIfType<[i8, i16], CCPromoteToType<i32>>,
81 CCIfType<[i32, f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
83 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
84 T0_64, T1_64, T2_64, T3_64]>>,
86 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
87 CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
88 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
91 def RetCC_MipsN : CallingConv<[
92 // i32 are returned in registers V0, V1
93 CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
95 // i64 are returned in registers V0_64, V1_64
96 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>,
98 // f32 are returned in registers F0, F2
99 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
101 // f64 are returned in registers D0, D2
102 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>
105 //===----------------------------------------------------------------------===//
106 // Mips EABI Calling Convention
107 //===----------------------------------------------------------------------===//
109 def CC_MipsEABI : CallingConv<[
110 // Promote i8/i16 arguments to i32.
111 CCIfType<[i8, i16], CCPromoteToType<i32>>,
113 // Integer arguments are passed in integer registers.
114 CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
116 // Single fp arguments are passed in pairs within 32-bit mode
117 CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
118 CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>,
120 CCIfType<[f32], CCIfSubtarget<"isNotSingleFloat()",
121 CCAssignToReg<[F12, F14, F16, F18]>>>,
123 // The first 4 double fp arguments are passed in single fp registers.
124 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()",
125 CCAssignToReg<[D6, D7, D8, D9]>>>,
127 // Integer values get stored in stack slots that are 4 bytes in
128 // size and 4-byte aligned.
129 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
131 // Integer values get stored in stack slots that are 8 bytes in
132 // size and 8-byte aligned.
133 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToStack<8, 8>>>
136 def RetCC_MipsEABI : CallingConv<[
137 // i32 are returned in registers V0, V1
138 CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
140 // f32 are returned in registers F0, F1
141 CCIfType<[f32], CCAssignToReg<[F0, F1]>>,
143 // f64 are returned in register D0
144 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0]>>>
147 //===----------------------------------------------------------------------===//
148 // Mips FastCC Calling Convention
149 //===----------------------------------------------------------------------===//
150 def CC_MipsO32_FastCC : CallingConv<[
151 // f64 arguments are passed in double-precision floating pointer registers.
152 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7, D8, D9]>>,
154 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned.
155 CCIfType<[f64], CCAssignToStack<8, 8>>
158 def CC_MipsN_FastCC : CallingConv<[
159 // Integer arguments are passed in integer registers.
160 CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64,
161 T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
164 // f64 arguments are passed in double-precision floating pointer registers.
165 CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64,
166 D6_64, D7_64, D8_64, D9_64, D10_64, D11_64,
167 D12_64, D13_64, D14_64, D15_64, D16_64, D17_64,
170 // Stack parameter slots for i64 and f64 are 64-bit doublewords and
172 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
175 def CC_Mips_FastCC : CallingConv<[
176 // Handles byval parameters.
177 CCIfByVal<CCPassByVal<4, 4>>,
179 // Promote i8/i16 arguments to i32.
180 CCIfType<[i8, i16], CCPromoteToType<i32>>,
182 // Integer arguments are passed in integer registers. All scratch registers,
183 // except for AT, V0 and T9, are available to be used as argument registers.
184 CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6,
187 // f32 arguments are passed in single-precision floating pointer registers.
188 CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10,
189 F11, F12, F13, F14, F15, F16, F17, F18, F19]>>,
191 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
192 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
194 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
195 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,
196 CCDelegateTo<CC_MipsN_FastCC>
199 //===----------------------------------------------------------------------===//
200 // Mips Calling Convention Dispatch
201 //===----------------------------------------------------------------------===//
203 def CC_Mips : CallingConv<[
204 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
205 CCIfSubtarget<"isABI_N32()", CCDelegateTo<CC_MipsN>>,
206 CCIfSubtarget<"isABI_N64()", CCDelegateTo<CC_MipsN>>
209 def RetCC_Mips : CallingConv<[
210 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>,
211 CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
212 CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
213 CCDelegateTo<RetCC_MipsO32>
216 //===----------------------------------------------------------------------===//
217 // Callee-saved register lists.
218 //===----------------------------------------------------------------------===//
220 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
221 (sequence "S%u", 7, 0))>;
223 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
224 (sequence "S%u", 7, 0))>;
226 def CSR_N32 : CalleeSavedRegs<(add D31_64, D29_64, D27_64, D25_64, D24_64,
227 D23_64, D22_64, D21_64, RA_64, FP_64, GP_64,
228 (sequence "S%u_64", 7, 0))>;
230 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
231 GP_64, (sequence "S%u_64", 7, 0))>;