1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for Mips architecture.
10 //===----------------------------------------------------------------------===//
12 /// CCIfSubtarget - Match if the current subtarget has a feature F.
13 class CCIfSubtarget<string F, CCAction A, string Invert = "">
14 : CCIf<!strconcat(Invert,
15 "static_cast<const MipsSubtarget&>"
16 "(State.getMachineFunction().getSubtarget()).",
20 // The inverse of CCIfSubtarget
21 class CCIfSubtargetNot<string F, CCAction A> : CCIfSubtarget<F, A, "!">;
23 // For soft-float, f128 values are returned in A0_64 rather than V1_64.
24 def RetCC_F128SoftFloat : CallingConv<[
25 CCAssignToReg<[V0_64, A0_64]>
28 // For hard-float, f128 values are returned as a pair of f64's rather than a
30 def RetCC_F128HardFloat : CallingConv<[
31 CCBitConvertToType<f64>,
33 // Contrary to the ABI documentation, a struct containing a long double is
34 // returned in $f0, and $f1 instead of the usual $f0, and $f2. This is to
35 // match the de facto ABI as implemented by GCC.
36 CCIfInReg<CCAssignToReg<[D0_64, D1_64]>>,
38 CCAssignToReg<[D0_64, D2_64]>
41 // Handle F128 specially since we can't identify the original type during the
42 // tablegen-erated code.
43 def RetCC_F128 : CallingConv<[
44 CCIfSubtarget<"abiUsesSoftFloat()",
45 CCIfType<[i64], CCDelegateTo<RetCC_F128SoftFloat>>>,
46 CCIfSubtargetNot<"abiUsesSoftFloat()",
47 CCIfType<[i64], CCDelegateTo<RetCC_F128HardFloat>>>
50 //===----------------------------------------------------------------------===//
51 // Mips O32 Calling Convention
52 //===----------------------------------------------------------------------===//
54 // Only the return rules are defined here for O32. The rules for argument
55 // passing are defined in MipsISelLowering.cpp.
56 def RetCC_MipsO32 : CallingConv<[
57 // i32 are returned in registers V0, V1, A0, A1
58 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>,
60 // f32 are returned in registers F0, F2
61 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
63 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
64 // in D0 and D1 in FP32bit mode.
65 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>,
66 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", CCAssignToReg<[D0, D1]>>>
69 //===----------------------------------------------------------------------===//
70 // Mips N32/64 Calling Convention
71 //===----------------------------------------------------------------------===//
73 def CC_MipsN : CallingConv<[
74 // Promote i8/i16 arguments to i32.
75 CCIfType<[i8, i16], CCPromoteToType<i32>>,
77 // Integer arguments are passed in integer registers.
78 CCIfType<[i32], CCAssignToRegWithShadow<[A0, A1, A2, A3,
81 F16, F17, F18, F19]>>,
83 CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
84 T0_64, T1_64, T2_64, T3_64],
85 [D12_64, D13_64, D14_64, D15_64,
86 D16_64, D17_64, D18_64, D19_64]>>,
88 // f32 arguments are passed in single precision FP registers.
89 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,
91 [A0_64, A1_64, A2_64, A3_64,
92 T0_64, T1_64, T2_64, T3_64]>>,
94 // f64 arguments are passed in double precision FP registers.
95 CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64,
96 D16_64, D17_64, D18_64, D19_64],
97 [A0_64, A1_64, A2_64, A3_64,
98 T0_64, T1_64, T2_64, T3_64]>>,
100 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
101 CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
102 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
105 // N32/64 variable arguments.
106 // All arguments are passed in integer registers.
107 def CC_MipsN_VarArg : CallingConv<[
108 // Promote i8/i16 arguments to i32.
109 CCIfType<[i8, i16], CCPromoteToType<i32>>,
111 CCIfType<[i32, f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
113 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
114 T0_64, T1_64, T2_64, T3_64]>>,
116 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
117 CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
118 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
121 def RetCC_MipsN : CallingConv<[
122 // f128 needs to be handled similarly to f32 and f64. However, f128 is not
123 // legal and is lowered to i128 which is further lowered to a pair of i64's.
124 // This presents us with a problem for the calling convention since hard-float
125 // still needs to pass them in FPU registers, and soft-float needs to use $v0,
126 // and $a0 instead of the usual $v0, and $v1. We therefore resort to a
127 // pre-analyze (see PreAnalyzeReturnForF128()) step to pass information on
128 // whether the result was originally an f128 into the tablegen-erated code.
130 // f128 should only occur for the N64 ABI where long double is 128-bit. On
131 // N32, long double is equivalent to double.
133 CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)",
134 CCDelegateTo<RetCC_F128>>>,
136 // Aggregate returns are positioned at the lowest address in the slot for
137 // both little and big-endian targets. When passing in registers, this
138 // requires that big-endian targets shift the value into the upper bits.
139 CCIfSubtarget<"isLittle()",
140 CCIfType<[i8, i16, i32], CCIfInReg<CCPromoteToType<i64>>>>,
141 CCIfSubtargetNot<"isLittle()",
142 CCIfType<[i8, i16, i32], CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,
144 // i32 are returned in registers V0, V1
145 CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
147 // i64 are returned in registers V0_64, V1_64
148 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>,
150 // f32 are returned in registers F0, F2
151 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
153 // f64 are returned in registers D0, D2
154 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>
157 //===----------------------------------------------------------------------===//
158 // Mips EABI Calling Convention
159 //===----------------------------------------------------------------------===//
161 def CC_MipsEABI : CallingConv<[
162 // Promote i8/i16 arguments to i32.
163 CCIfType<[i8, i16], CCPromoteToType<i32>>,
165 // Integer arguments are passed in integer registers.
166 CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
168 // Single fp arguments are passed in pairs within 32-bit mode
169 CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
170 CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>,
172 CCIfType<[f32], CCIfSubtargetNot<"isSingleFloat()",
173 CCAssignToReg<[F12, F14, F16, F18]>>>,
175 // The first 4 double fp arguments are passed in single fp registers.
176 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()",
177 CCAssignToReg<[D6, D7, D8, D9]>>>,
179 // Integer values get stored in stack slots that are 4 bytes in
180 // size and 4-byte aligned.
181 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
183 // Integer values get stored in stack slots that are 8 bytes in
184 // size and 8-byte aligned.
185 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToStack<8, 8>>>
188 def RetCC_MipsEABI : CallingConv<[
189 // i32 are returned in registers V0, V1
190 CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
192 // f32 are returned in registers F0, F1
193 CCIfType<[f32], CCAssignToReg<[F0, F1]>>,
195 // f64 are returned in register D0
196 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToReg<[D0]>>>
199 //===----------------------------------------------------------------------===//
200 // Mips FastCC Calling Convention
201 //===----------------------------------------------------------------------===//
202 def CC_MipsO32_FastCC : CallingConv<[
203 // f64 arguments are passed in double-precision floating pointer registers.
204 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()",
205 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6,
207 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"useOddSPReg()",
208 CCAssignToReg<[D0_64, D1_64, D2_64, D3_64,
209 D4_64, D5_64, D6_64, D7_64,
210 D8_64, D9_64, D10_64, D11_64,
211 D12_64, D13_64, D14_64, D15_64,
212 D16_64, D17_64, D18_64,
214 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"noOddSPReg()",
215 CCAssignToReg<[D0_64, D2_64, D4_64, D6_64,
216 D8_64, D10_64, D12_64, D14_64,
219 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned.
220 CCIfType<[f64], CCAssignToStack<8, 8>>
223 def CC_MipsN_FastCC : CallingConv<[
224 // Integer arguments are passed in integer registers.
225 CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64,
226 T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
229 // f64 arguments are passed in double-precision floating pointer registers.
230 CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64,
231 D6_64, D7_64, D8_64, D9_64, D10_64, D11_64,
232 D12_64, D13_64, D14_64, D15_64, D16_64, D17_64,
235 // Stack parameter slots for i64 and f64 are 64-bit doublewords and
237 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
240 def CC_Mips_FastCC : CallingConv<[
241 // Handles byval parameters.
242 CCIfByVal<CCPassByVal<4, 4>>,
244 // Promote i8/i16 arguments to i32.
245 CCIfType<[i8, i16], CCPromoteToType<i32>>,
247 // Integer arguments are passed in integer registers. All scratch registers,
248 // except for AT, V0 and T9, are available to be used as argument registers.
249 CCIfType<[i32], CCIfSubtargetNot<"isTargetNaCl()",
250 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>,
252 // In NaCl, T6, T7 and T8 are reserved and not available as argument
253 // registers for fastcc. T6 contains the mask for sandboxing control flow
254 // (indirect jumps and calls). T7 contains the mask for sandboxing memory
255 // accesses (loads and stores). T8 contains the thread pointer.
256 CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()",
257 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>,
259 // f32 arguments are passed in single-precision floating pointer registers.
260 CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",
261 CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13,
262 F14, F15, F16, F17, F18, F19]>>>,
264 // Don't use odd numbered single-precision registers for -mno-odd-spreg.
265 CCIfType<[f32], CCIfSubtarget<"noOddSPReg()",
266 CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>,
268 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
269 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
271 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
272 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,
273 CCDelegateTo<CC_MipsN_FastCC>
278 def CC_Mips16RetHelper : CallingConv<[
279 // Integer arguments are passed in integer registers.
280 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
283 //===----------------------------------------------------------------------===//
284 // Mips Calling Convention Dispatch
285 //===----------------------------------------------------------------------===//
287 def RetCC_Mips : CallingConv<[
288 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>,
289 CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
290 CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
291 CCDelegateTo<RetCC_MipsO32>
294 //===----------------------------------------------------------------------===//
295 // Callee-saved register lists.
296 //===----------------------------------------------------------------------===//
298 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
299 (sequence "S%u", 7, 0))>;
301 def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
302 (sequence "S%u", 7, 0))> {
303 let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2));
306 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
307 (sequence "S%u", 7, 0))>;
310 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
311 (sequence "S%u", 7, 0))>;
313 def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64,
314 D30_64, RA_64, FP_64, GP_64,
315 (sequence "S%u_64", 7, 0))>;
317 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
318 GP_64, (sequence "S%u_64", 7, 0))>;
320 def CSR_Mips16RetHelper :
321 CalleeSavedRegs<(add V0, V1, FP,
322 (sequence "A%u", 3, 0), (sequence "S%u", 7, 0),
323 (sequence "D%u", 15, 10))>;