1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for Mips architecture.
10 //===----------------------------------------------------------------------===//
12 /// CCIfSubtarget - Match if the current subtarget has a feature F.
13 class CCIfSubtarget<string F, CCAction A, string Invert = "">
14 : CCIf<!strconcat(Invert,
15 "static_cast<const MipsSubtarget&>"
16 "(State.getMachineFunction().getSubtarget()).",
20 // The inverse of CCIfSubtarget
21 class CCIfSubtargetNot<string F, CCAction A> : CCIfSubtarget<F, A, "!">;
23 // For soft-float, f128 values are returned in A0_64 rather than V1_64.
24 def RetCC_F128SoftFloat : CallingConv<[
25 CCAssignToReg<[V0_64, A0_64]>
28 // For hard-float, f128 values are returned as a pair of f64's rather than a
30 def RetCC_F128HardFloat : CallingConv<[
31 CCBitConvertToType<f64>,
33 // Contrary to the ABI documentation, a struct containing a long double is
34 // returned in $f0, and $f1 instead of the usual $f0, and $f2. This is to
35 // match the de facto ABI as implemented by GCC.
36 CCIfInReg<CCAssignToReg<[D0_64, D1_64]>>,
38 CCAssignToReg<[D0_64, D2_64]>
41 // Handle F128 specially since we can't identify the original type during the
42 // tablegen-erated code.
43 def RetCC_F128 : CallingConv<[
44 CCIfSubtarget<"abiUsesSoftFloat()",
45 CCIfType<[i64], CCDelegateTo<RetCC_F128SoftFloat>>>,
46 CCIfSubtargetNot<"abiUsesSoftFloat()",
47 CCIfType<[i64], CCDelegateTo<RetCC_F128HardFloat>>>
50 //===----------------------------------------------------------------------===//
51 // Mips O32 Calling Convention
52 //===----------------------------------------------------------------------===//
54 // Only the return rules are defined here for O32. The rules for argument
55 // passing are defined in MipsISelLowering.cpp.
56 def RetCC_MipsO32 : CallingConv<[
57 // i32 are returned in registers V0, V1, A0, A1
58 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>,
60 // f32 are returned in registers F0, F2
61 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
63 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
64 // in D0 and D1 in FP32bit mode.
65 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>,
66 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", CCAssignToReg<[D0, D1]>>>
69 def CC_MipsO32_FP32 : CustomCallingConv;
70 def CC_MipsO32_FP64 : CustomCallingConv;
72 def CC_MipsO32_FP : CallingConv<[
73 CCIfSubtargetNot<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP32>>,
74 CCIfSubtarget<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP64>>
77 //===----------------------------------------------------------------------===//
78 // Mips N32/64 Calling Convention
79 //===----------------------------------------------------------------------===//
81 def CC_MipsN : CallingConv<[
82 // Promote i8/i16 arguments to i32.
83 CCIfType<[i8, i16], CCPromoteToType<i32>>,
85 // Integer arguments are passed in integer registers.
86 CCIfType<[i32], CCAssignToRegWithShadow<[A0, A1, A2, A3,
89 F16, F17, F18, F19]>>,
91 CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
92 T0_64, T1_64, T2_64, T3_64],
93 [D12_64, D13_64, D14_64, D15_64,
94 D16_64, D17_64, D18_64, D19_64]>>,
96 // f32 arguments are passed in single precision FP registers.
97 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,
99 [A0_64, A1_64, A2_64, A3_64,
100 T0_64, T1_64, T2_64, T3_64]>>,
102 // f64 arguments are passed in double precision FP registers.
103 CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64,
104 D16_64, D17_64, D18_64, D19_64],
105 [A0_64, A1_64, A2_64, A3_64,
106 T0_64, T1_64, T2_64, T3_64]>>,
108 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
109 CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
110 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
113 // N32/64 variable arguments.
114 // All arguments are passed in integer registers.
115 def CC_MipsN_VarArg : CallingConv<[
116 // Promote i8/i16 arguments to i32.
117 CCIfType<[i8, i16], CCPromoteToType<i32>>,
119 CCIfType<[i32, f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
121 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
122 T0_64, T1_64, T2_64, T3_64]>>,
124 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
125 CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
126 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
129 def RetCC_MipsN : CallingConv<[
130 // f128 needs to be handled similarly to f32 and f64. However, f128 is not
131 // legal and is lowered to i128 which is further lowered to a pair of i64's.
132 // This presents us with a problem for the calling convention since hard-float
133 // still needs to pass them in FPU registers, and soft-float needs to use $v0,
134 // and $a0 instead of the usual $v0, and $v1. We therefore resort to a
135 // pre-analyze (see PreAnalyzeReturnForF128()) step to pass information on
136 // whether the result was originally an f128 into the tablegen-erated code.
138 // f128 should only occur for the N64 ABI where long double is 128-bit. On
139 // N32, long double is equivalent to double.
141 CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)",
142 CCDelegateTo<RetCC_F128>>>,
144 // Aggregate returns are positioned at the lowest address in the slot for
145 // both little and big-endian targets. When passing in registers, this
146 // requires that big-endian targets shift the value into the upper bits.
147 CCIfSubtarget<"isLittle()",
148 CCIfType<[i8, i16, i32, i64], CCIfInReg<CCPromoteToType<i64>>>>,
149 CCIfSubtargetNot<"isLittle()",
150 CCIfType<[i8, i16, i32, i64],
151 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,
153 // i64 are returned in registers V0_64, V1_64
154 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>,
156 // f32 are returned in registers F0, F2
157 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
159 // f64 are returned in registers D0, D2
160 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>
163 //===----------------------------------------------------------------------===//
164 // Mips EABI Calling Convention
165 //===----------------------------------------------------------------------===//
167 def CC_MipsEABI : CallingConv<[
168 // Promote i8/i16 arguments to i32.
169 CCIfType<[i8, i16], CCPromoteToType<i32>>,
171 // Integer arguments are passed in integer registers.
172 CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
174 // Single fp arguments are passed in pairs within 32-bit mode
175 CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
176 CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>,
178 CCIfType<[f32], CCIfSubtargetNot<"isSingleFloat()",
179 CCAssignToReg<[F12, F14, F16, F18]>>>,
181 // The first 4 double fp arguments are passed in single fp registers.
182 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()",
183 CCAssignToReg<[D6, D7, D8, D9]>>>,
185 // Integer values get stored in stack slots that are 4 bytes in
186 // size and 4-byte aligned.
187 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
189 // Integer values get stored in stack slots that are 8 bytes in
190 // size and 8-byte aligned.
191 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToStack<8, 8>>>
194 def RetCC_MipsEABI : CallingConv<[
195 // i32 are returned in registers V0, V1
196 CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
198 // f32 are returned in registers F0, F1
199 CCIfType<[f32], CCAssignToReg<[F0, F1]>>,
201 // f64 are returned in register D0
202 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToReg<[D0]>>>
205 //===----------------------------------------------------------------------===//
206 // Mips FastCC Calling Convention
207 //===----------------------------------------------------------------------===//
208 def CC_MipsO32_FastCC : CallingConv<[
209 // f64 arguments are passed in double-precision floating pointer registers.
210 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()",
211 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6,
213 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"useOddSPReg()",
214 CCAssignToReg<[D0_64, D1_64, D2_64, D3_64,
215 D4_64, D5_64, D6_64, D7_64,
216 D8_64, D9_64, D10_64, D11_64,
217 D12_64, D13_64, D14_64, D15_64,
218 D16_64, D17_64, D18_64,
220 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"noOddSPReg()",
221 CCAssignToReg<[D0_64, D2_64, D4_64, D6_64,
222 D8_64, D10_64, D12_64, D14_64,
225 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned.
226 CCIfType<[f64], CCAssignToStack<8, 8>>
229 def CC_MipsN_FastCC : CallingConv<[
230 // Integer arguments are passed in integer registers.
231 CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64,
232 T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
235 // f64 arguments are passed in double-precision floating pointer registers.
236 CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64,
237 D6_64, D7_64, D8_64, D9_64, D10_64, D11_64,
238 D12_64, D13_64, D14_64, D15_64, D16_64, D17_64,
241 // Stack parameter slots for i64 and f64 are 64-bit doublewords and
243 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
246 def CC_Mips_FastCC : CallingConv<[
247 // Handles byval parameters.
248 CCIfByVal<CCPassByVal<4, 4>>,
250 // Promote i8/i16 arguments to i32.
251 CCIfType<[i8, i16], CCPromoteToType<i32>>,
253 // Integer arguments are passed in integer registers. All scratch registers,
254 // except for AT, V0 and T9, are available to be used as argument registers.
255 CCIfType<[i32], CCIfSubtargetNot<"isTargetNaCl()",
256 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>,
258 // In NaCl, T6, T7 and T8 are reserved and not available as argument
259 // registers for fastcc. T6 contains the mask for sandboxing control flow
260 // (indirect jumps and calls). T7 contains the mask for sandboxing memory
261 // accesses (loads and stores). T8 contains the thread pointer.
262 CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()",
263 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>,
265 // f32 arguments are passed in single-precision floating pointer registers.
266 CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",
267 CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13,
268 F14, F15, F16, F17, F18, F19]>>>,
270 // Don't use odd numbered single-precision registers for -mno-odd-spreg.
271 CCIfType<[f32], CCIfSubtarget<"noOddSPReg()",
272 CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>,
274 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
275 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
277 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
278 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,
279 CCDelegateTo<CC_MipsN_FastCC>
284 def CC_Mips16RetHelper : CallingConv<[
285 // Integer arguments are passed in integer registers.
286 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
289 //===----------------------------------------------------------------------===//
290 // Mips Calling Convention Dispatch
291 //===----------------------------------------------------------------------===//
293 def RetCC_Mips : CallingConv<[
294 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>,
295 CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
296 CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
297 CCDelegateTo<RetCC_MipsO32>
300 def CC_Mips_FixedArg : CallingConv<[
301 // f128 needs to be handled similarly to f32 and f64 on hard-float. However,
302 // f128 is not legal and is lowered to i128 which is further lowered to a pair
304 // This presents us with a problem for the calling convention since hard-float
305 // still needs to pass them in FPU registers. We therefore resort to a
306 // pre-analyze (see PreAnalyzeFormalArgsForF128()) step to pass information on
307 // whether the argument was originally an f128 into the tablegen-erated code.
309 // f128 should only occur for the N64 ABI where long double is 128-bit. On
310 // N32, long double is equivalent to double.
312 CCIfSubtargetNot<"abiUsesSoftFloat()",
313 CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)",
314 CCBitConvertToType<f64>>>>,
316 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>,
318 // FIXME: There wasn't an EABI case in the original code and it seems unlikely
319 // that it's the same as CC_MipsN
320 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
321 CCDelegateTo<CC_MipsN>
324 def CC_Mips_VarArg : CallingConv<[
325 // FIXME: There wasn't an EABI case in the original code and it seems unlikely
326 // that it's the same as CC_MipsN_VarArg
327 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
328 CCDelegateTo<CC_MipsN_VarArg>
331 //===----------------------------------------------------------------------===//
332 // Callee-saved register lists.
333 //===----------------------------------------------------------------------===//
335 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
336 (sequence "S%u", 7, 0))>;
338 def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
339 (sequence "S%u", 7, 0))> {
340 let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2));
343 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
344 (sequence "S%u", 7, 0))>;
347 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
348 (sequence "S%u", 7, 0))>;
350 def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64,
351 D30_64, RA_64, FP_64, GP_64,
352 (sequence "S%u_64", 7, 0))>;
354 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
355 GP_64, (sequence "S%u_64", 7, 0))>;
357 def CSR_Mips16RetHelper :
358 CalleeSavedRegs<(add V0, V1, FP,
359 (sequence "A%u", 3, 0), (sequence "S%u", 7, 0),
360 (sequence "D%u", 15, 10))>;