1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for Mips architecture.
10 //===----------------------------------------------------------------------===//
12 /// CCIfSubtarget - Match if the current subtarget has a feature F.
13 class CCIfSubtarget<string F, CCAction A, string Invert = "">
14 : CCIf<!strconcat(Invert,
15 "static_cast<const MipsSubtarget&>"
16 "(State.getMachineFunction().getSubtarget()).",
20 // The inverse of CCIfSubtarget
21 class CCIfSubtargetNot<string F, CCAction A> : CCIfSubtarget<F, A, "!">;
23 //===----------------------------------------------------------------------===//
24 // Mips O32 Calling Convention
25 //===----------------------------------------------------------------------===//
27 // Only the return rules are defined here for O32. The rules for argument
28 // passing are defined in MipsISelLowering.cpp.
29 def RetCC_MipsO32 : CallingConv<[
30 // i32 are returned in registers V0, V1, A0, A1
31 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>,
33 // f32 are returned in registers F0, F2
34 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
36 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
37 // in D0 and D1 in FP32bit mode.
38 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>,
39 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", CCAssignToReg<[D0, D1]>>>
42 //===----------------------------------------------------------------------===//
43 // Mips N32/64 Calling Convention
44 //===----------------------------------------------------------------------===//
46 def CC_MipsN : CallingConv<[
47 // Promote i8/i16 arguments to i32.
48 CCIfType<[i8, i16], CCPromoteToType<i32>>,
50 // Integer arguments are passed in integer registers.
51 CCIfType<[i32], CCAssignToRegWithShadow<[A0, A1, A2, A3,
54 F16, F17, F18, F19]>>,
56 CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
57 T0_64, T1_64, T2_64, T3_64],
58 [D12_64, D13_64, D14_64, D15_64,
59 D16_64, D17_64, D18_64, D19_64]>>,
61 // f32 arguments are passed in single precision FP registers.
62 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15,
64 [A0_64, A1_64, A2_64, A3_64,
65 T0_64, T1_64, T2_64, T3_64]>>,
67 // f64 arguments are passed in double precision FP registers.
68 CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64,
69 D16_64, D17_64, D18_64, D19_64],
70 [A0_64, A1_64, A2_64, A3_64,
71 T0_64, T1_64, T2_64, T3_64]>>,
73 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
74 CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
75 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
78 // N32/64 variable arguments.
79 // All arguments are passed in integer registers.
80 def CC_MipsN_VarArg : CallingConv<[
81 // Promote i8/i16 arguments to i32.
82 CCIfType<[i8, i16], CCPromoteToType<i32>>,
84 CCIfType<[i32, f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
86 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64,
87 T0_64, T1_64, T2_64, T3_64]>>,
89 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned.
90 CCIfType<[i32, f32], CCAssignToStack<4, 8>>,
91 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
94 def RetCC_MipsN : CallingConv<[
95 // i32 are returned in registers V0, V1
96 CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
98 // i64 are returned in registers V0_64, V1_64
99 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>,
101 // f32 are returned in registers F0, F2
102 CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
104 // f64 are returned in registers D0, D2
105 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>>
108 // In soft-mode, register A0_64, instead of V1_64, is used to return a long
110 def RetCC_F128Soft : CallingConv<[
111 CCIfType<[i64], CCAssignToReg<[V0_64, A0_64]>>
114 //===----------------------------------------------------------------------===//
115 // Mips EABI Calling Convention
116 //===----------------------------------------------------------------------===//
118 def CC_MipsEABI : CallingConv<[
119 // Promote i8/i16 arguments to i32.
120 CCIfType<[i8, i16], CCPromoteToType<i32>>,
122 // Integer arguments are passed in integer registers.
123 CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
125 // Single fp arguments are passed in pairs within 32-bit mode
126 CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
127 CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>,
129 CCIfType<[f32], CCIfSubtargetNot<"isSingleFloat()",
130 CCAssignToReg<[F12, F14, F16, F18]>>>,
132 // The first 4 double fp arguments are passed in single fp registers.
133 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()",
134 CCAssignToReg<[D6, D7, D8, D9]>>>,
136 // Integer values get stored in stack slots that are 4 bytes in
137 // size and 4-byte aligned.
138 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
140 // Integer values get stored in stack slots that are 8 bytes in
141 // size and 8-byte aligned.
142 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToStack<8, 8>>>
145 def RetCC_MipsEABI : CallingConv<[
146 // i32 are returned in registers V0, V1
147 CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
149 // f32 are returned in registers F0, F1
150 CCIfType<[f32], CCAssignToReg<[F0, F1]>>,
152 // f64 are returned in register D0
153 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToReg<[D0]>>>
156 //===----------------------------------------------------------------------===//
157 // Mips FastCC Calling Convention
158 //===----------------------------------------------------------------------===//
159 def CC_MipsO32_FastCC : CallingConv<[
160 // f64 arguments are passed in double-precision floating pointer registers.
161 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()",
162 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6,
164 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"useOddSPReg()",
165 CCAssignToReg<[D0_64, D1_64, D2_64, D3_64,
166 D4_64, D5_64, D6_64, D7_64,
167 D8_64, D9_64, D10_64, D11_64,
168 D12_64, D13_64, D14_64, D15_64,
169 D16_64, D17_64, D18_64,
171 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"noOddSPReg()",
172 CCAssignToReg<[D0_64, D2_64, D4_64, D6_64,
173 D8_64, D10_64, D12_64, D14_64,
176 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned.
177 CCIfType<[f64], CCAssignToStack<8, 8>>
180 def CC_MipsN_FastCC : CallingConv<[
181 // Integer arguments are passed in integer registers.
182 CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64,
183 T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
186 // f64 arguments are passed in double-precision floating pointer registers.
187 CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64,
188 D6_64, D7_64, D8_64, D9_64, D10_64, D11_64,
189 D12_64, D13_64, D14_64, D15_64, D16_64, D17_64,
192 // Stack parameter slots for i64 and f64 are 64-bit doublewords and
194 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
197 def CC_Mips_FastCC : CallingConv<[
198 // Handles byval parameters.
199 CCIfByVal<CCPassByVal<4, 4>>,
201 // Promote i8/i16 arguments to i32.
202 CCIfType<[i8, i16], CCPromoteToType<i32>>,
204 // Integer arguments are passed in integer registers. All scratch registers,
205 // except for AT, V0 and T9, are available to be used as argument registers.
206 CCIfType<[i32], CCIfSubtargetNot<"isTargetNaCl()",
207 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>,
209 // In NaCl, T6, T7 and T8 are reserved and not available as argument
210 // registers for fastcc. T6 contains the mask for sandboxing control flow
211 // (indirect jumps and calls). T7 contains the mask for sandboxing memory
212 // accesses (loads and stores). T8 contains the thread pointer.
213 CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()",
214 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>,
216 // f32 arguments are passed in single-precision floating pointer registers.
217 CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",
218 CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13,
219 F14, F15, F16, F17, F18, F19]>>>,
221 // Don't use odd numbered single-precision registers for -mno-odd-spreg.
222 CCIfType<[f32], CCIfSubtarget<"noOddSPReg()",
223 CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>,
225 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned.
226 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
228 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>,
229 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>,
230 CCDelegateTo<CC_MipsN_FastCC>
235 def CC_Mips16RetHelper : CallingConv<[
236 // Integer arguments are passed in integer registers.
237 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
240 //===----------------------------------------------------------------------===//
241 // Mips Calling Convention Dispatch
242 //===----------------------------------------------------------------------===//
244 def RetCC_Mips : CallingConv<[
245 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>,
246 CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>,
247 CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>,
248 CCDelegateTo<RetCC_MipsO32>
251 //===----------------------------------------------------------------------===//
252 // Callee-saved register lists.
253 //===----------------------------------------------------------------------===//
255 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
256 (sequence "S%u", 7, 0))>;
258 def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
259 (sequence "S%u", 7, 0))> {
260 let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2));
263 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
264 (sequence "S%u", 7, 0))>;
267 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
268 (sequence "S%u", 7, 0))>;
270 def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64,
271 D30_64, RA_64, FP_64, GP_64,
272 (sequence "S%u_64", 7, 0))>;
274 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
275 GP_64, (sequence "S%u_64", 7, 0))>;
277 def CSR_Mips16RetHelper :
278 CalleeSavedRegs<(add V0, V1, FP,
279 (sequence "A%u", 3, 0), (sequence "S%u", 7, 0),
280 (sequence "D%u", 15, 10))>;