1 //===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the Conditional Moves implementation.
12 //===----------------------------------------------------------------------===//
15 // These instructions are expanded in
16 // MipsISelLowering::EmitInstrWithCustomInserter if target does not have
17 // conditional move instructions.
19 class CondMovIntInt<RegisterClass CRC, RegisterClass DRC, bits<6> funct,
21 FR<0, funct, (outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
22 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], NoItinerary> {
24 let Constraints = "$F = $rd";
27 // cond:int, data:float
28 class CondMovIntFP<RegisterClass CRC, RegisterClass DRC, bits<5> fmt,
29 bits<6> func, string instr_asm> :
30 FFR<0x11, func, fmt, (outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
31 !strconcat(instr_asm, "\t$fd, $fs, $rt"), []> {
34 let Constraints = "$F = $fd";
37 // cond:float, data:int
38 class CondMovFPInt<RegisterClass RC, SDNode cmov, bits<1> tf,
40 FCMOV<tf, (outs RC:$rd), (ins RC:$rs, RC:$F),
41 !strconcat(instr_asm, "\t$rd, $rs, $$fcc0"),
42 [(set RC:$rd, (cmov RC:$rs, RC:$F))]> {
45 let Constraints = "$F = $rd";
48 // cond:float, data:float
49 class CondMovFPFP<RegisterClass RC, SDNode cmov, bits<5> fmt, bits<1> tf,
51 FFCMOV<fmt, tf, (outs RC:$fd), (ins RC:$fs, RC:$F),
52 !strconcat(instr_asm, "\t$fd, $fs, $$fcc0"),
53 [(set RC:$fd, (cmov RC:$fs, RC:$F))]> {
56 let Constraints = "$F = $fd";
60 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
61 Instruction MOVZInst, Instruction SLTOp,
62 Instruction SLTuOp, Instruction SLTiOp,
63 Instruction SLTiuOp> {
64 def : Pat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
65 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
66 def : Pat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
67 (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
68 def : Pat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
69 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
70 def : Pat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
71 (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
72 def : Pat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
73 (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
74 def : Pat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
75 (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
78 multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
79 Instruction MOVZInst, Instruction XOROp> {
80 def : Pat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
81 (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
82 def : Pat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
83 (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
86 multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
88 def : Pat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
89 (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
90 def : Pat<(select CRC:$cond, DRC:$T, DRC:$F),
91 (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
92 def : Pat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
93 (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
96 // Instantiation of instructions.
97 def MOVZ_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0a, "movz">;
98 let Predicates = [HasMips64] in {
99 def MOVZ_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0a, "movz">;
100 def MOVZ_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0a, "movz">;
101 def MOVZ_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0a, "movz">;
104 def MOVN_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0b, "movn">;
105 let Predicates = [HasMips64] in {
106 def MOVN_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0b, "movn">;
107 def MOVN_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0b, "movn">;
108 def MOVN_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0b, "movn">;
111 def MOVZ_I_S : CondMovIntFP<CPURegs, FGR32, 16, 18, "movz.s">;
112 def MOVZ_I64_S : CondMovIntFP<CPU64Regs, FGR32, 16, 18, "movz.s">,
113 Requires<[HasMips64]>;
115 def MOVN_I_S : CondMovIntFP<CPURegs, FGR32, 16, 19, "movn.s">;
116 def MOVN_I64_S : CondMovIntFP<CPU64Regs, FGR32, 16, 19, "movn.s">,
117 Requires<[HasMips64]>;
119 let Predicates = [NotFP64bit] in {
120 def MOVZ_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 18, "movz.d">;
121 def MOVN_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 19, "movn.d">;
123 let Predicates = [IsFP64bit] in {
124 def MOVZ_I_D64 : CondMovIntFP<CPURegs, FGR64, 17, 18, "movz.d">;
125 def MOVZ_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 18, "movz.d">;
126 def MOVN_I_D64 : CondMovIntFP<CPURegs, FGR64, 17, 19, "movn.d">;
127 def MOVN_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 19, "movn.d">;
130 def MOVT_I : CondMovFPInt<CPURegs, MipsCMovFP_T, 1, "movt">;
131 def MOVT_I64 : CondMovFPInt<CPU64Regs, MipsCMovFP_T, 1, "movt">,
132 Requires<[HasMips64]>;
134 def MOVF_I : CondMovFPInt<CPURegs, MipsCMovFP_F, 0, "movf">;
135 def MOVF_I64 : CondMovFPInt<CPU64Regs, MipsCMovFP_F, 0, "movf">,
136 Requires<[HasMips64]>;
138 def MOVT_S : CondMovFPFP<FGR32, MipsCMovFP_T, 16, 1, "movt.s">;
139 def MOVF_S : CondMovFPFP<FGR32, MipsCMovFP_F, 16, 0, "movf.s">;
141 let Predicates = [NotFP64bit] in {
142 def MOVT_D32 : CondMovFPFP<AFGR64, MipsCMovFP_T, 17, 1, "movt.d">;
143 def MOVF_D32 : CondMovFPFP<AFGR64, MipsCMovFP_F, 17, 0, "movf.d">;
145 let Predicates = [IsFP64bit] in {
146 def MOVT_D64 : CondMovFPFP<FGR64, MipsCMovFP_T, 17, 1, "movt.d">;
147 def MOVF_D64 : CondMovFPFP<FGR64, MipsCMovFP_F, 17, 0, "movf.d">;
150 // Instantiation of conditional move patterns.
151 defm : MovzPats0<CPURegs, CPURegs, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
152 defm : MovzPats1<CPURegs, CPURegs, MOVZ_I_I, XOR>;
153 let Predicates = [HasMips64] in {
154 defm : MovzPats0<CPURegs, CPU64Regs, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
155 defm : MovzPats0<CPU64Regs, CPURegs, MOVZ_I_I, SLT64, SLTu64, SLTi64,
157 defm : MovzPats0<CPU64Regs, CPU64Regs, MOVZ_I_I64, SLT64, SLTu64, SLTi64,
159 defm : MovzPats1<CPURegs, CPU64Regs, MOVZ_I_I64, XOR>;
160 defm : MovzPats1<CPU64Regs, CPURegs, MOVZ_I64_I, XOR64>;
161 defm : MovzPats1<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XOR64>;
164 defm : MovnPats<CPURegs, CPURegs, MOVN_I_I, XOR>;
165 let Predicates = [HasMips64] in {
166 defm : MovnPats<CPURegs, CPU64Regs, MOVN_I_I64, XOR>;
167 defm : MovnPats<CPU64Regs, CPURegs, MOVN_I64_I, XOR64>;
168 defm : MovnPats<CPU64Regs, CPU64Regs, MOVN_I64_I64, XOR64>;
171 defm : MovzPats0<CPURegs, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
172 defm : MovzPats1<CPURegs, FGR32, MOVZ_I_S, XOR>;
173 defm : MovnPats<CPURegs, FGR32, MOVN_I_S, XOR>;
174 let Predicates = [HasMips64] in {
175 defm : MovzPats0<CPU64Regs, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
177 defm : MovzPats1<CPU64Regs, FGR32, MOVZ_I64_S, XOR64>;
178 defm : MovnPats<CPU64Regs, FGR32, MOVN_I64_S, XOR64>;
181 let Predicates = [NotFP64bit] in {
182 defm : MovzPats0<CPURegs, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
183 defm : MovzPats1<CPURegs, AFGR64, MOVZ_I_D32, XOR>;
184 defm : MovnPats<CPURegs, AFGR64, MOVN_I_D32, XOR>;
186 let Predicates = [IsFP64bit] in {
187 defm : MovzPats0<CPURegs, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
188 defm : MovzPats0<CPU64Regs, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
190 defm : MovzPats1<CPURegs, FGR64, MOVZ_I_D64, XOR>;
191 defm : MovzPats1<CPU64Regs, FGR64, MOVZ_I64_D64, XOR64>;
192 defm : MovnPats<CPURegs, FGR64, MOVN_I_D64, XOR>;
193 defm : MovnPats<CPU64Regs, FGR64, MOVN_I64_D64, XOR64>;