2 // These instructions are expanded in
3 // MipsISelLowering::EmitInstrWithCustomInserter if target does not have
4 // conditional move instructions.
6 class CondMovIntInt<RegisterClass CRC, RegisterClass DRC, bits<6> funct,
8 FR<0, funct, (outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
9 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], NoItinerary> {
11 let Constraints = "$F = $rd";
14 // cond:int, data:float
15 class CondMovIntFP<RegisterClass CRC, RegisterClass DRC, bits<5> fmt,
16 bits<6> func, string instr_asm> :
17 FFR<0x11, func, fmt, (outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
18 !strconcat(instr_asm, "\t$fd, $fs, $rt"), []> {
21 let Constraints = "$F = $fd";
24 // cond:float, data:int
25 class CondMovFPInt<RegisterClass RC, SDNode cmov, bits<1> tf,
27 FCMOV<tf, (outs RC:$rd), (ins RC:$rs, RC:$F),
28 !strconcat(instr_asm, "\t$rd, $rs, $$fcc0"),
29 [(set RC:$rd, (cmov RC:$rs, RC:$F))]> {
32 let Constraints = "$F = $rd";
35 // cond:float, data:float
36 class CondMovFPFP<RegisterClass RC, SDNode cmov, bits<5> fmt, bits<1> tf,
38 FFCMOV<fmt, tf, (outs RC:$fd), (ins RC:$fs, RC:$F),
39 !strconcat(instr_asm, "\t$fd, $fs, $$fcc0"),
40 [(set RC:$fd, (cmov RC:$fs, RC:$F))]> {
43 let Constraints = "$F = $fd";
47 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
48 Instruction MOVZInst, Instruction SLTOp,
49 Instruction SLTuOp, Instruction SLTiOp,
50 Instruction SLTiuOp> {
51 def : Pat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
52 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
53 def : Pat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
54 (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
55 def : Pat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
56 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
57 def : Pat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
58 (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
59 def : Pat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
60 (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
61 def : Pat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
62 (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
65 multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
66 Instruction MOVZInst, Instruction XOROp> {
67 def : Pat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
68 (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
69 def : Pat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
70 (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
73 multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
75 def : Pat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
76 (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
77 def : Pat<(select CRC:$cond, DRC:$T, DRC:$F),
78 (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
79 def : Pat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
80 (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
83 // Instantiation of instructions.
84 def MOVZ_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0a, "movz">;
85 let Predicates = [HasMips64] in {
86 def MOVZ_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0a, "movz">;
87 def MOVZ_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0a, "movz">;
88 def MOVZ_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0a, "movz">;
91 def MOVN_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0b, "movn">;
92 let Predicates = [HasMips64] in {
93 def MOVN_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0b, "movn">;
94 def MOVN_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0b, "movn">;
95 def MOVN_I64_I64 : CondMovIntInt<CPU64Regs, CPU64Regs, 0x0b, "movn">;
98 def MOVZ_I_S : CondMovIntFP<CPURegs, FGR32, 16, 18, "movz.s">;
99 def MOVZ_I64_S : CondMovIntFP<CPU64Regs, FGR32, 16, 18, "movz.s">,
100 Requires<[HasMips64]>;
102 def MOVN_I_S : CondMovIntFP<CPURegs, FGR32, 16, 19, "movn.s">;
103 def MOVN_I64_S : CondMovIntFP<CPU64Regs, FGR32, 16, 19, "movn.s">,
104 Requires<[HasMips64]>;
106 let Predicates = [NotFP64bit] in {
107 def MOVZ_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 18, "movz.d">;
108 def MOVN_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 19, "movn.d">;
110 let Predicates = [IsFP64bit] in {
111 def MOVZ_I_D64 : CondMovIntFP<CPURegs, FGR64, 17, 18, "movz.d">;
112 def MOVZ_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 18, "movz.d">;
113 def MOVN_I_D64 : CondMovIntFP<CPURegs, FGR64, 17, 19, "movn.d">;
114 def MOVN_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 19, "movn.d">;
117 def MOVT_I : CondMovFPInt<CPURegs, MipsCMovFP_T, 1, "movt">;
118 def MOVT_I64 : CondMovFPInt<CPU64Regs, MipsCMovFP_T, 1, "movt">,
119 Requires<[HasMips64]>;
121 def MOVF_I : CondMovFPInt<CPURegs, MipsCMovFP_F, 0, "movf">;
122 def MOVF_I64 : CondMovFPInt<CPU64Regs, MipsCMovFP_F, 0, "movf">,
123 Requires<[HasMips64]>;
125 def MOVT_S : CondMovFPFP<FGR32, MipsCMovFP_T, 16, 1, "movt.s">;
126 def MOVF_S : CondMovFPFP<FGR32, MipsCMovFP_F, 16, 0, "movf.s">;
128 let Predicates = [NotFP64bit] in {
129 def MOVT_D32 : CondMovFPFP<AFGR64, MipsCMovFP_T, 17, 1, "movt.d">;
130 def MOVF_D32 : CondMovFPFP<AFGR64, MipsCMovFP_F, 17, 0, "movf.d">;
132 let Predicates = [IsFP64bit] in {
133 def MOVT_D64 : CondMovFPFP<FGR64, MipsCMovFP_T, 17, 1, "movt.d">;
134 def MOVF_D64 : CondMovFPFP<FGR64, MipsCMovFP_F, 17, 0, "movf.d">;
137 // Instantiation of conditional move patterns.
138 defm : MovzPats0<CPURegs, CPURegs, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
139 defm : MovzPats1<CPURegs, CPURegs, MOVZ_I_I, XOR>;
140 let Predicates = [HasMips64] in {
141 defm : MovzPats0<CPURegs, CPU64Regs, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
142 defm : MovzPats0<CPU64Regs, CPURegs, MOVZ_I_I, SLT64, SLTu64, SLTi64,
144 defm : MovzPats0<CPU64Regs, CPU64Regs, MOVZ_I_I64, SLT64, SLTu64, SLTi64,
146 defm : MovzPats1<CPURegs, CPU64Regs, MOVZ_I_I64, XOR>;
147 defm : MovzPats1<CPU64Regs, CPURegs, MOVZ_I64_I, XOR64>;
148 defm : MovzPats1<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XOR64>;
151 defm : MovnPats<CPURegs, CPURegs, MOVN_I_I, XOR>;
152 let Predicates = [HasMips64] in {
153 defm : MovnPats<CPURegs, CPU64Regs, MOVN_I_I64, XOR>;
154 defm : MovnPats<CPU64Regs, CPURegs, MOVN_I64_I, XOR64>;
155 defm : MovnPats<CPU64Regs, CPU64Regs, MOVN_I64_I64, XOR64>;
158 defm : MovzPats0<CPURegs, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
159 defm : MovzPats1<CPURegs, FGR32, MOVZ_I_S, XOR>;
160 defm : MovnPats<CPURegs, FGR32, MOVN_I_S, XOR>;
161 let Predicates = [HasMips64] in {
162 defm : MovzPats0<CPU64Regs, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
164 defm : MovzPats1<CPU64Regs, FGR32, MOVZ_I64_S, XOR64>;
165 defm : MovnPats<CPU64Regs, FGR32, MOVN_I64_S, XOR64>;
168 let Predicates = [NotFP64bit] in {
169 defm : MovzPats0<CPURegs, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
170 defm : MovzPats1<CPURegs, AFGR64, MOVZ_I_D32, XOR>;
171 defm : MovnPats<CPURegs, AFGR64, MOVN_I_D32, XOR>;
173 let Predicates = [IsFP64bit] in {
174 defm : MovzPats0<CPURegs, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
175 defm : MovzPats0<CPU64Regs, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
177 defm : MovzPats1<CPURegs, FGR64, MOVZ_I_D64, XOR>;
178 defm : MovzPats1<CPU64Regs, FGR64, MOVZ_I64_D64, XOR64>;
179 defm : MovnPats<CPURegs, FGR64, MOVN_I_D64, XOR>;
180 defm : MovnPats<CPU64Regs, FGR64, MOVN_I64_D64, XOR64>;