1 //===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the Conditional Moves implementation.
12 //===----------------------------------------------------------------------===//
15 // These instructions are expanded in
16 // MipsISelLowering::EmitInstrWithCustomInserter if target does not have
17 // conditional move instructions.
19 class CMov_I_I_FT<string opstr, RegisterClass CRC, RegisterClass DRC,
20 InstrItinClass Itin> :
21 InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
22 !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR> {
23 let Constraints = "$F = $rd";
26 // cond:int, data:float
27 class CMov_I_F_FT<string opstr, RegisterClass CRC, RegisterClass DRC,
28 InstrItinClass Itin> :
29 InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
30 !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR> {
31 let Constraints = "$F = $fd";
34 // cond:float, data:int
35 class CMov_F_I_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
36 SDPatternOperator OpNode = null_frag> :
37 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$F),
38 !strconcat(opstr, "\t$rd, $rs, $$fcc0"),
39 [(set RC:$rd, (OpNode RC:$rs, RC:$F))], Itin, FrmFR> {
41 let Constraints = "$F = $rd";
44 // cond:float, data:float
45 class CMov_F_F_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
46 SDPatternOperator OpNode = null_frag> :
47 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$F),
48 !strconcat(opstr, "\t$fd, $fs, $$fcc0"),
49 [(set RC:$fd, (OpNode RC:$fs, RC:$F))], Itin, FrmFR> {
51 let Constraints = "$F = $fd";
55 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
56 Instruction MOVZInst, Instruction SLTOp,
57 Instruction SLTuOp, Instruction SLTiOp,
58 Instruction SLTiuOp> {
59 def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
60 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
61 def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
62 (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
63 def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
64 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>;
65 def : MipsPat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F),
66 (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>;
67 def : MipsPat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
68 (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
69 def : MipsPat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
70 (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
71 def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)),
73 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>;
74 def : MipsPat<(select (i32 (setugt CRC:$lhs, immSExt16Plus1:$rhs)),
76 (MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)),
80 multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
81 Instruction MOVZInst, Instruction XOROp> {
82 def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
83 (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
84 def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F),
85 (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>;
88 multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
89 Instruction MOVZInst, Instruction XORiOp> {
91 (select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F),
92 (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>;
95 multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
97 def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
98 (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>;
99 def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F),
100 (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>;
101 def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F),
102 (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>;
105 // Instantiation of instructions.
106 def MOVZ_I_I : CMov_I_I_FT<"movz", CPURegs, CPURegs, NoItinerary>,
108 let Predicates = [HasStdEnc],
109 DecoderNamespace = "Mips64" in {
110 def MOVZ_I_I64 : CMov_I_I_FT<"movz", CPURegs, CPU64Regs, NoItinerary>,
112 def MOVZ_I64_I : CMov_I_I_FT<"movz", CPU64Regs, CPURegs, NoItinerary>,
114 let isCodeGenOnly = 1;
116 def MOVZ_I64_I64 : CMov_I_I_FT<"movz", CPU64Regs, CPU64Regs, NoItinerary>,
118 let isCodeGenOnly = 1;
122 def MOVN_I_I : CMov_I_I_FT<"movn", CPURegs, CPURegs, NoItinerary>,
124 let Predicates = [HasStdEnc],
125 DecoderNamespace = "Mips64" in {
126 def MOVN_I_I64 : CMov_I_I_FT<"movn", CPURegs, CPU64Regs, NoItinerary>,
128 def MOVN_I64_I : CMov_I_I_FT<"movn", CPU64Regs, CPURegs, NoItinerary>,
130 let isCodeGenOnly = 1;
132 def MOVN_I64_I64 : CMov_I_I_FT<"movn", CPU64Regs, CPU64Regs, NoItinerary>,
134 let isCodeGenOnly = 1;
138 def MOVZ_I_S : CMov_I_F_FT<"movz.s", CPURegs, FGR32, IIFmove>,
140 def MOVZ_I64_S : CMov_I_F_FT<"movz.s", CPU64Regs, FGR32, IIFmove>,
141 CMov_I_F_FM<18, 16>, Requires<[HasMips64, HasStdEnc]> {
142 let DecoderNamespace = "Mips64";
145 def MOVN_I_S : CMov_I_F_FT<"movn.s", CPURegs, FGR32, IIFmove>,
147 def MOVN_I64_S : CMov_I_F_FT<"movn.s", CPU64Regs, FGR32, IIFmove>,
148 CMov_I_F_FM<19, 16>, Requires<[HasMips64, HasStdEnc]> {
149 let DecoderNamespace = "Mips64";
152 let Predicates = [NotFP64bit, HasStdEnc] in {
153 def MOVZ_I_D32 : CMov_I_F_FT<"movz.d", CPURegs, AFGR64, IIFmove>,
155 def MOVN_I_D32 : CMov_I_F_FT<"movn.d", CPURegs, AFGR64, IIFmove>,
158 let Predicates = [IsFP64bit, HasStdEnc],
159 DecoderNamespace = "Mips64" in {
160 def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", CPURegs, FGR64, IIFmove>,
162 def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", CPU64Regs, FGR64, IIFmove>,
163 CMov_I_F_FM<18, 17> {
164 let isCodeGenOnly = 1;
166 def MOVN_I_D64 : CMov_I_F_FT<"movn.d", CPURegs, FGR64, IIFmove>,
168 def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", CPU64Regs, FGR64, IIFmove>,
169 CMov_I_F_FM<19, 17> {
170 let isCodeGenOnly = 1;
174 def MOVT_I : CMov_F_I_FT<"movt", CPURegs, IIAlu, MipsCMovFP_T>, CMov_F_I_FM<1>;
175 def MOVT_I64 : CMov_F_I_FT<"movt", CPU64Regs, IIAlu, MipsCMovFP_T>,
176 CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]> {
177 let DecoderNamespace = "Mips64";
180 def MOVF_I : CMov_F_I_FT<"movf", CPURegs, IIAlu, MipsCMovFP_F>, CMov_F_I_FM<0>;
181 def MOVF_I64 : CMov_F_I_FT<"movf", CPU64Regs, IIAlu, MipsCMovFP_F>,
182 CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]> {
183 let DecoderNamespace = "Mips64";
186 def MOVT_S : CMov_F_F_FT<"movt.s", FGR32, IIFmove, MipsCMovFP_T>,
188 def MOVF_S : CMov_F_F_FT<"movf.s", FGR32, IIFmove, MipsCMovFP_F>,
191 let Predicates = [NotFP64bit, HasStdEnc] in {
192 def MOVT_D32 : CMov_F_F_FT<"movt.d", AFGR64, IIFmove, MipsCMovFP_T>,
194 def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64, IIFmove, MipsCMovFP_F>,
197 let Predicates = [IsFP64bit, HasStdEnc],
198 DecoderNamespace = "Mips64" in {
199 def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64, IIFmove, MipsCMovFP_T>,
201 def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64, IIFmove, MipsCMovFP_F>,
205 // Instantiation of conditional move patterns.
206 defm : MovzPats0<CPURegs, CPURegs, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
207 defm : MovzPats1<CPURegs, CPURegs, MOVZ_I_I, XOR>;
208 defm : MovzPats2<CPURegs, CPURegs, MOVZ_I_I, XORi>;
209 let Predicates = [HasMips64, HasStdEnc] in {
210 defm : MovzPats0<CPURegs, CPU64Regs, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
211 defm : MovzPats0<CPU64Regs, CPURegs, MOVZ_I_I, SLT64, SLTu64, SLTi64,
213 defm : MovzPats0<CPU64Regs, CPU64Regs, MOVZ_I_I64, SLT64, SLTu64, SLTi64,
215 defm : MovzPats1<CPURegs, CPU64Regs, MOVZ_I_I64, XOR>;
216 defm : MovzPats1<CPU64Regs, CPURegs, MOVZ_I64_I, XOR64>;
217 defm : MovzPats1<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XOR64>;
218 defm : MovzPats2<CPURegs, CPU64Regs, MOVZ_I_I64, XORi>;
219 defm : MovzPats2<CPU64Regs, CPURegs, MOVZ_I64_I, XORi64>;
220 defm : MovzPats2<CPU64Regs, CPU64Regs, MOVZ_I64_I64, XORi64>;
223 defm : MovnPats<CPURegs, CPURegs, MOVN_I_I, XOR>;
224 let Predicates = [HasMips64, HasStdEnc] in {
225 defm : MovnPats<CPURegs, CPU64Regs, MOVN_I_I64, XOR>;
226 defm : MovnPats<CPU64Regs, CPURegs, MOVN_I64_I, XOR64>;
227 defm : MovnPats<CPU64Regs, CPU64Regs, MOVN_I64_I64, XOR64>;
230 defm : MovzPats0<CPURegs, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
231 defm : MovzPats1<CPURegs, FGR32, MOVZ_I_S, XOR>;
232 defm : MovnPats<CPURegs, FGR32, MOVN_I_S, XOR>;
233 let Predicates = [HasMips64, HasStdEnc] in {
234 defm : MovzPats0<CPU64Regs, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
236 defm : MovzPats1<CPU64Regs, FGR32, MOVZ_I64_S, XOR64>;
237 defm : MovnPats<CPU64Regs, FGR32, MOVN_I64_S, XOR64>;
240 let Predicates = [NotFP64bit, HasStdEnc] in {
241 defm : MovzPats0<CPURegs, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
242 defm : MovzPats1<CPURegs, AFGR64, MOVZ_I_D32, XOR>;
243 defm : MovnPats<CPURegs, AFGR64, MOVN_I_D32, XOR>;
245 let Predicates = [IsFP64bit, HasStdEnc] in {
246 defm : MovzPats0<CPURegs, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
247 defm : MovzPats0<CPU64Regs, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
249 defm : MovzPats1<CPURegs, FGR64, MOVZ_I_D64, XOR>;
250 defm : MovzPats1<CPU64Regs, FGR64, MOVZ_I64_D64, XOR64>;
251 defm : MovnPats<CPURegs, FGR64, MOVN_I_D64, XOR>;
252 defm : MovnPats<CPU64Regs, FGR64, MOVN_I64_D64, XOR64>;